OV - exec - Loop 192

	Loop Id: 192	Module: exec	Source: field_summary_kernel.f90:57-71	Coverage: 0.33%

0x420b0c ADD	W5, W10, W4

0x420b10 ADD	W4, W4, W11

0x420b14 SBFM	X5, X5, #0, #31

0x420b18 CMP	W16, W4

0x420b1c SUB	X5, X5, X21

0x420b20 ADD	X6, X5, X2

0x420b24 LD1D	{Z27.D}, P1/Z, [X0, X5,LSL #3]    [7]

0x420b28 ADD	X7, X20, X6,LSL #3

0x420b2c LD1D	{Z21.D}, P1/Z, [X20, X6,LSL #3]    [5]

0x420b30 LD1D	{Z23.D}, P1/Z, [X19, X6,LSL #3]    [18]

0x420b34 LD1D	{Z22.D}, P1/Z, [X7, X13,LSL #3]    [4]

0x420b38 ADD	X7, X19, X6,LSL #3

0x420b3c ADD	X6, X5, #1

0x420b40 LD1D	{Z24.D}, P1/Z, [X7, X13,LSL #3]    [3]

0x420b44 ADD	X7, X6, X2

0x420b48 ADD	X6, X6, X3

0x420b4c ADD	X27, X20, X7,LSL #3

0x420b50 LD1D	{Z25.D}, P1/Z, [X19, X7,LSL #3]    [18]

0x420b54 FMUL	Z21.D, Z21.D, Z21.D

0x420b58 FMUL	Z23.D, Z23.D, Z23.D

0x420b5c FMUL	Z22.D, Z22.D, Z22.D

0x420b60 FMUL	Z24.D, Z24.D, Z24.D

0x420b64 FADD	Z21.D, Z23.D, Z21.D

0x420b68 LD1D	{Z23.D}, P1/Z, [X20, X7,LSL #3]    [5]

0x420b6c FMUL	Z25.D, Z25.D, Z25.D

0x420b70 FADD	Z22.D, Z24.D, Z22.D

0x420b74 LD1D	{Z24.D}, P1/Z, [X27, X13,LSL #3]    [17]

0x420b78 ADD	X27, X19, X7,LSL #3

0x420b7c ADD	X7, X5, X3

0x420b80 LD1D	{Z26.D}, P1/Z, [X27, X13,LSL #3]    [16]

0x420b84 ADD	X27, X20, X7,LSL #3

0x420b88 FMUL	Z23.D, Z23.D, Z23.D

0x420b8c FMUL	Z24.D, Z24.D, Z24.D

0x420b90 FMUL	Z26.D, Z26.D, Z26.D

0x420b94 FADD	Z23.D, Z25.D, Z23.D

0x420b98 LD1D	{Z25.D}, P1/Z, [X19, X7,LSL #3]    [18]

0x420b9c FADD	Z21.D, Z23.D, Z21.D

0x420ba0 LD1D	{Z23.D}, P1/Z, [X20, X7,LSL #3]    [5]

0x420ba4 FADD	Z24.D, Z26.D, Z24.D

0x420ba8 FADD	Z22.D, Z24.D, Z22.D

0x420bac LD1D	{Z24.D}, P1/Z, [X27, X13,LSL #3]    [15]

0x420bb0 ADD	X27, X19, X7,LSL #3

0x420bb4 ADD	X7, X20, X6,LSL #3

0x420bb8 LD1D	{Z26.D}, P1/Z, [X27, X13,LSL #3]    [14]

0x420bbc FMUL	Z25.D, Z25.D, Z25.D

0x420bc0 FMUL	Z23.D, Z23.D, Z23.D

0x420bc4 FMUL	Z24.D, Z24.D, Z24.D

0x420bc8 FADD	Z23.D, Z25.D, Z23.D

0x420bcc LD1D	{Z25.D}, P1/Z, [X19, X6,LSL #3]    [18]

0x420bd0 FMUL	Z26.D, Z26.D, Z26.D

0x420bd4 FADD	Z21.D, Z23.D, Z21.D

0x420bd8 LD1D	{Z23.D}, P1/Z, [X20, X6,LSL #3]    [5]

0x420bdc FADD	Z24.D, Z26.D, Z24.D

0x420be0 FADD	Z22.D, Z24.D, Z22.D

0x420be4 LD1D	{Z24.D}, P1/Z, [X7, X13,LSL #3]    [2]

0x420be8 ADD	X7, X19, X6,LSL #3

0x420bec FMUL	Z25.D, Z25.D, Z25.D

0x420bf0 ADD	X6, X5, X18

0x420bf4 LD1D	{Z26.D}, P1/Z, [X7, X13,LSL #3]    [1]

0x420bf8 ADD	X7, X25, X6,LSL #3

0x420bfc FMUL	Z23.D, Z23.D, Z23.D

0x420c00 FADD	Z23.D, Z25.D, Z23.D

0x420c04 LD1D	{Z25.D}, P1/Z, [X26, X6,LSL #3]    [8]

0x420c08 FMUL	Z24.D, Z24.D, Z24.D

0x420c0c FMUL	Z26.D, Z26.D, Z26.D

0x420c10 FADD	Z21.D, Z23.D, Z21.D

0x420c14 LD1D	{Z23.D}, P1/Z, [X25, X6,LSL #3]    [6]

0x420c18 FMUL	Z21.D, Z21.D, Z2.D

0x420c1c FADD	Z24.D, Z26.D, Z24.D

0x420c20 FADD	Z22.D, Z24.D, Z22.D

0x420c24 LD1D	{Z24.D}, P1/Z, [X7, X13,LSL #3]    [13]

0x420c28 ADD	X7, X26, X6,LSL #3

0x420c2c ADD	X6, X0, X5,LSL #3

0x420c30 LD1D	{Z26.D}, P1/Z, [X7, X13,LSL #3]    [12]

0x420c34 FMUL	Z25.D, Z25.D, Z23.D

0x420c38 LD1D	{Z28.D}, P1/Z, [X6, X13,LSL #3]    [10]

0x420c3c ADD	X6, X1, X5,LSL #3

0x420c40 FADD	Z3.D, Z3.D, Z23.D

0x420c44 FMUL	Z22.D, Z22.D, Z2.D

0x420c48 FMLA	Z16.D, P1/M, Z21.D, Z25.D

0x420c4c LD1D	{Z21.D}, P1/Z, [X1, X5,LSL #3]    [11]

0x420c50 FMLA	Z4.D, P1/M, Z27.D, Z25.D

0x420c54 FADD	Z6.D, Z6.D, Z25.D

0x420c58 FADD	Z20.D, Z20.D, Z24.D

0x420c5c FMUL	Z26.D, Z26.D, Z24.D

0x420c60 FMLA	Z19.D, P1/M, Z22.D, Z26.D

0x420c64 LD1D	{Z22.D}, P1/Z, [X6, X13,LSL #3]    [9]

0x420c68 FMLA	Z18.D, P1/M, Z28.D, Z26.D

0x420c6c FMLA	Z5.D, P1/M, Z21.D, Z23.D

0x420c70 FADD	Z17.D, Z17.D, Z26.D

0x420c74 FMLA	Z7.D, P1/M, Z22.D, Z24.D

0x420c78 B.NE	420b0c

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 57 - 71

--------------------------------------------------------------------------------

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.26+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	field_summary_kernel	field_summary_kernel.f90:77	exec
○	field_summary	field_summary.f90:81	exec
○	hydro	hydro.f90:81	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.83
Bottlenecks	P6, P7, P8, P9,
Function	_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par
Source	field_summary_kernel.f90:57-71
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	22.00
CQA cycles if fully vectorized	22.00
Front-end cycles	11.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	5.75
P6 cycles	22.00
P7 cycles	22.00
P8 cycles	22.00
P9 cycles	22.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	92.00
Nb uops	92.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.09
Nb FLOP add-sub	72.00
Nb FLOP mul	80.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.91
Bytes prefetched	0.00
Bytes loaded	768.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	6.00
Vectorization ratio all	97.14
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	94.74
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	97.50
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.39
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.83
Bottlenecks	P6, P7, P8, P9,
Function	_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par
Source	field_summary_kernel.f90:57-71
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	22.00
CQA cycles if fully vectorized	22.00
Front-end cycles	11.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	5.75
P6 cycles	22.00
P7 cycles	22.00
P8 cycles	22.00
P9 cycles	22.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	92.00
Nb uops	92.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	9.09
Nb FLOP add-sub	72.00
Nb FLOP mul	80.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.91
Bytes prefetched	0.00
Bytes loaded	768.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	6.00
Vectorization ratio all	97.14
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	94.74
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	97.50
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	95.39
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par
Source file and lines	field_summary_kernel.f90:57-71
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:57-71.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

97% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 12 occurrence(s)
Irregular (variable stride) or indirect: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 200 FP arithmetical operations:

96: addition or subtraction (24 inside FMA instructions)
104: multiply (24 inside FMA instructions)

The binary loop is loading 768 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	92
nb uops	92
loop length	368
used w registers	5
used x registers	15
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	19
nb stack references	0
ADD-SUB / MUL ratio	0.90

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.75	5.75	5.75	5.75	22.00	22.00	0.00	0.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	5.75	5.75	5.75	5.75	22.00	22.00	22.00	22.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	11.50
Dispatch	22.00
Data deps.	2.00
Overall L1	22.00

Vectorization ratios

INT

all	92%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	94%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	95%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.00 cycles. At this rate:

36% of peak load performance is reached (34.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 420b0c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
ADD W5, W10, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD W4, W4, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SBFM X5, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP W16, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
SUB X5, X5, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X6, X5, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z27.D}, P1/Z, [X0, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X20, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z21.D}, P1/Z, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X19, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X6, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z24.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X6, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X27, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z25.D}, P1/Z, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z21.D, Z21.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z22.D, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z21.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X19, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X5, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z23.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z21.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z24.D, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X19, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X20, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z23.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z21.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z24.D, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X19, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
ADD X6, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X25, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z23.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z21.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z21.D, Z21.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z24.D, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X26, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X6, X0, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z25.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z28.D}, P1/Z, [X6, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X6, X1, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FADD Z3.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z22.D, Z22.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z16.D, P1/M, Z21.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z21.D}, P1/Z, [X1, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z4.D, P1/M, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z6.D, Z6.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z20.D, Z20.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z19.D, P1/M, Z22.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z22.D}, P1/Z, [X6, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z5.D, P1/M, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z7.D, P1/M, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
B.NE 420b0c <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par
Source file and lines	field_summary_kernel.f90:57-71
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

97% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 12 occurrence(s)
Irregular (variable stride) or indirect: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 200 FP arithmetical operations:

96: addition or subtraction (24 inside FMA instructions)
104: multiply (24 inside FMA instructions)

The binary loop is loading 768 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	92
nb uops	92
loop length	368
used w registers	5
used x registers	15
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	19
nb stack references	0
ADD-SUB / MUL ratio	0.90

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.75	5.75	5.75	5.75	22.00	22.00	0.00	0.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	5.75	5.75	5.75	5.75	22.00	22.00	22.00	22.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	11.50
Dispatch	22.00
Data deps.	2.00
Overall L1	22.00

Vectorization ratios

INT

all	92%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	94%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	95%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.00 cycles. At this rate:

36% of peak load performance is reached (34.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 420b0c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
ADD W5, W10, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD W4, W4, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SBFM X5, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP W16, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
SUB X5, X5, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X6, X5, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z27.D}, P1/Z, [X0, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X20, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z21.D}, P1/Z, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X19, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X6, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z24.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X6, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X27, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z25.D}, P1/Z, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z21.D, Z21.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z22.D, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z21.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X19, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X5, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z23.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z21.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z24.D, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X27, X19, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X20, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z23.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z21.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z24.D, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X19, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z25.D, Z25.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
ADD X6, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X25, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z23.D, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z23.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P1/Z, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z24.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z21.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P1/Z, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z21.D, Z21.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADD Z24.D, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z22.D, Z24.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X7, X26, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X6, X0, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z25.D, Z25.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
LD1D {Z28.D}, P1/Z, [X6, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X6, X1, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FADD Z3.D, Z3.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z22.D, Z22.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z16.D, P1/M, Z21.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z21.D}, P1/Z, [X1, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z4.D, P1/M, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z6.D, Z6.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FADD Z20.D, Z20.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMUL Z26.D, Z26.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z19.D, P1/M, Z22.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z22.D}, P1/Z, [X6, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMLA Z18.D, P1/M, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z5.D, P1/M, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z7.D, P1/M, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
B.NE 420b0c <_QMfield_summary_kernel_modulePfield_summary_kernel..omp_par+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code