OV - exec - Loop 205

	Loop Id: 205	Module: exec	Source: flux_calc_kernel.f90:55-59	Coverage: 4.60%

0x421980 SBFM	X4, X2, #0, #31

0x421984 SUB	X7, X18, X20

0x421988 ADD	W3, W3, W16

0x42198c SUB	X4, X4, X20

0x421990 ADD	X5, X4, X18

0x421994 ADD	X6, X4, X0

0x421998 ADD	X4, X4, X1

0x42199c LD1D	{Z3.D}, P1/Z, [X23, X5,LSL #3]    [2]

0x4219a0 LD1D	{Z4.D}, P1/Z, [X23, X6,LSL #3]    [2]

0x4219a4 LD1D	{Z5.D}, P1/Z, [X24, X5,LSL #3]    [3]

0x4219a8 LD1D	{Z2.D}, P1/Z, [X22, X5,LSL #3]    [1]

0x4219ac FADD	Z3.D, Z4.D, Z3.D

0x4219b0 LD1D	{Z4.D}, P1/Z, [X24, X6,LSL #3]    [3]

0x4219b4 FMUL	Z2.D, Z1.D, Z2.D

0x4219b8 ADD	W6, W2, #1

0x4219bc ADD	W2, W2, W16

0x4219c0 ADD	X6, X7, W6,SXTW

0x4219c4 FADD	Z4.D, Z5.D, Z4.D

0x4219c8 LD1D	{Z5.D}, P1/Z, [X26, X4,LSL #3]    [5]

0x4219cc FADD	Z3.D, Z3.D, Z4.D

0x4219d0 LD1D	{Z4.D}, P1/Z, [X27, X5,LSL #3]    [6]

0x4219d4 FMUL	Z2.D, Z2.D, Z3.D

0x4219d8 LD1D	{Z3.D}, P1/Z, [X28, X5,LSL #3]    [7]

0x4219dc FMUL	Z5.D, Z5.D, Z1.D

0x4219e0 ST1D	{Z2.D}, P1, [X25, X5,LSL #3]    [4]

0x4219e4 LD1D	{Z2.D}, P1/Z, [X27, X6,LSL #3]    [6]

0x4219e8 FADD	Z2.D, Z2.D, Z4.D

0x4219ec LD1D	{Z4.D}, P1/Z, [X28, X6,LSL #3]    [7]

0x4219f0 FADD	Z3.D, Z3.D, Z4.D

0x4219f4 FADD	Z2.D, Z2.D, Z3.D

0x4219f8 FMUL	Z2.D, Z5.D, Z2.D

0x4219fc ST1D	{Z2.D}, P1, [X19, X4,LSL #3]    [8]

0x421a00 WHILELO	P1.D, W3, W17

0x421a04 B.MI	421980

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90: 55 - 59

--------------------------------------------------------------------------------

55:     !$OMP SIMD

56:       DO j=x_min,x_max+1

57:         vol_flux_x(j,k)=0.25_8*dt*xarea(j,k)                  &

58:           *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1))

59:         vol_flux_y(j,k)=0.25_8*dt*yarea(j,k)                  &

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	flux_calc_kernel	flux_calc_kernel.f90:67	exec
○	flux_calc	flux_calc.f90:41	exec
○	hydro	hydro.f90:62	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P10, P11,
Function	_QMflux_calc_kernel_modulePflux_calc_kernel..omp_par
Source	flux_calc_kernel.f90:55-59
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	4.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.67
Nb FLOP add-sub	24.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	8.00
Vectorization ratio all	91.67
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	93.23
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	79.69
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P10, P11,
Function	_QMflux_calc_kernel_modulePflux_calc_kernel..omp_par
Source	flux_calc_kernel.f90:55-59
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	4.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.67
Nb FLOP add-sub	24.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	8.00
Vectorization ratio all	91.67
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	93.23
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	79.69
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMflux_calc_kernel_modulePflux_calc_kernel..omp_par
Source file and lines	flux_calc_kernel.f90:55-59
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:55-59.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

91% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU addition or subtraction instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction
16: multiply

The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	34
nb uops	34
loop length	136
used w registers	5
used x registers	17
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	5
nb stack references	0
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.75	2.75	2.75	2.75	5.00	5.00	1.00	1.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	2.75	2.75	2.75	2.75	5.00	5.00	5.00	5.00	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	91%
load	100%
store	100%
mul	100%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	88%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	93%
load	100%
store	100%
mul	100%
add-sub	79%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

55% of peak load performance is reached (53.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 421980

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X4, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X18, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W3, W3, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X4, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z3.D}, P1/Z, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X23, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P1/Z, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P1/Z, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X24, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z2.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD W6, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W2, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X6, X7, W6,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	2	0.50	N/A
FADD Z4.D, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z5.D}, P1/Z, [X26, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X27, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z3.D}, P1/Z, [X28, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z5.D, Z5.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z2.D}, P1, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z2.D}, P1/Z, [X27, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X28, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z2.D, Z5.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z2.D}, P1, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P1.D, W3, W17	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 421980 <_QMflux_calc_kernel_modulePflux_calc_kernel..omp_par+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMflux_calc_kernel_modulePflux_calc_kernel..omp_par
Source file and lines	flux_calc_kernel.f90:55-59
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

91% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU addition or subtraction instructions are used in vector version.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction
16: multiply

The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	34
nb uops	34
loop length	136
used w registers	5
used x registers	17
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	5
nb stack references	0
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.75	2.75	2.75	2.75	5.00	5.00	1.00	1.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	2.75	2.75	2.75	2.75	5.00	5.00	5.00	5.00	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	91%
load	100%
store	100%
mul	100%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	88%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	93%
load	100%
store	100%
mul	100%
add-sub	79%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

55% of peak load performance is reached (53.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 421980

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SBFM X4, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X18, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W3, W3, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X4, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z3.D}, P1/Z, [X23, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X23, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P1/Z, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P1/Z, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X24, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z2.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ADD W6, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W2, W2, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X6, X7, W6,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	2	0.50	N/A
FADD Z4.D, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z5.D}, P1/Z, [X26, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X27, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z3.D}, P1/Z, [X28, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z5.D, Z5.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z2.D}, P1, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z2.D}, P1/Z, [X27, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X28, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z2.D, Z5.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z2.D}, P1, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P1.D, W3, W17	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 421980 <_QMflux_calc_kernel_modulePflux_calc_kernel..omp_par+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code