OV - exec - Loop 21

	Loop Id: 21	Module: exec	Source: build_field.f90:103-115	Coverage: 0.04%

0x4129a8 LDRSW	X16, [X20]    [7]

0x4129ac SUB	X15, X15, #1

0x4129b0 CMP	X15, #1

0x4129b4 SUB	X16, X16, X10

0x4129b8 MADD	X16, X16, X12, X9

0x4129bc LDR	X17, [X16, #1080]    [23]

0x4129c0 LDR	X18, [X16, #1104]    [23]

0x4129c4 LDR	X0, [X16, #1112]    [23]

0x4129c8 LDR	X16, [X16, #1128]    [23]

0x4129cc SUB	X16, X13, X16

0x4129d0 SUB	X17, X17, X18,LSL #3

0x4129d4 MUL	X16, X0, X16

0x4129d8 ADD	X16, X17, X16,LSL #3

0x4129dc STR	XZR, [X16, X14]    [22]

0x4129e0 LDRSW	X16, [X20]    [7]

0x4129e4 SUB	X16, X16, X10

0x4129e8 MADD	X16, X16, X12, X9

0x4129ec LDR	X17, [X16, #1152]    [21]

0x4129f0 LDR	X18, [X16, #1176]    [21]

0x4129f4 LDR	X0, [X16, #1184]    [21]

0x4129f8 LDR	X16, [X16, #1200]    [21]

0x4129fc SUB	X16, X13, X16

0x412a00 SUB	X17, X17, X18,LSL #3

0x412a04 MUL	X16, X0, X16

0x412a08 ADD	X16, X17, X16,LSL #3

0x412a0c STR	XZR, [X16, X14]    [15]

0x412a10 LDRSW	X16, [X20]    [7]

0x412a14 SUB	X16, X16, X10

0x412a18 MADD	X16, X16, X12, X9

0x412a1c LDR	X17, [X16, #1224]    [14]

0x412a20 LDR	X18, [X16, #1248]    [14]

0x412a24 LDR	X0, [X16, #1256]    [14]

0x412a28 LDR	X16, [X16, #1272]    [14]

0x412a2c SUB	X16, X13, X16

0x412a30 SUB	X17, X17, X18,LSL #3

0x412a34 MUL	X16, X0, X16

0x412a38 ADD	X16, X17, X16,LSL #3

0x412a3c STR	XZR, [X16, X14]    [13]

0x412a40 LDRSW	X16, [X20]    [7]

0x412a44 SUB	X16, X16, X10

0x412a48 MADD	X16, X16, X12, X9

0x412a4c LDR	X17, [X16, #1296]    [6]

0x412a50 LDR	X18, [X16, #1320]    [6]

0x412a54 LDR	X0, [X16, #1328]    [6]

0x412a58 LDR	X16, [X16, #1344]    [6]

0x412a5c SUB	X16, X13, X16

0x412a60 SUB	X17, X17, X18,LSL #3

0x412a64 MUL	X16, X0, X16

0x412a68 ADD	X16, X17, X16,LSL #3

0x412a6c STR	XZR, [X16, X14]    [5]

0x412a70 LDRSW	X16, [X20]    [7]

0x412a74 SUB	X16, X16, X10

0x412a78 MADD	X16, X16, X12, X9

0x412a7c LDR	X17, [X16, #1368]    [4]

0x412a80 LDR	X18, [X16, #1392]    [4]

0x412a84 LDR	X0, [X16, #1400]    [4]

0x412a88 LDR	X16, [X16, #1416]    [4]

0x412a8c SUB	X16, X13, X16

0x412a90 SUB	X17, X17, X18,LSL #3

0x412a94 MUL	X16, X0, X16

0x412a98 ADD	X16, X17, X16,LSL #3

0x412a9c STR	XZR, [X16, X14]    [20]

0x412aa0 LDRSW	X16, [X20]    [7]

0x412aa4 SUB	X16, X16, X10

0x412aa8 MADD	X16, X16, X12, X9

0x412aac LDR	X17, [X16, #1440]    [19]

0x412ab0 LDR	X18, [X16, #1464]    [19]

0x412ab4 LDR	X0, [X16, #1472]    [19]

0x412ab8 LDR	X16, [X16, #1488]    [19]

0x412abc SUB	X16, X13, X16

0x412ac0 SUB	X17, X17, X18,LSL #3

0x412ac4 MUL	X16, X0, X16

0x412ac8 ADD	X16, X17, X16,LSL #3

0x412acc STR	XZR, [X16, X14]    [12]

0x412ad0 LDRSW	X16, [X20]    [7]

0x412ad4 SUB	X16, X16, X10

0x412ad8 MADD	X16, X16, X12, X9

0x412adc LDR	X17, [X16, #1512]    [11]

0x412ae0 LDR	X18, [X16, #1536]    [11]

0x412ae4 LDR	X0, [X16, #1544]    [11]

0x412ae8 LDR	X16, [X16, #1560]    [11]

0x412aec SUB	X16, X13, X16

0x412af0 SUB	X17, X17, X18,LSL #3

0x412af4 MUL	X16, X0, X16

0x412af8 ADD	X16, X17, X16,LSL #3

0x412afc STR	XZR, [X16, X14]    [10]

0x412b00 LDRSW	X16, [X20]    [7]

0x412b04 SUB	X16, X16, X10

0x412b08 MADD	X16, X16, X12, X9

0x412b0c LDR	X17, [X16, #504]    [3]

0x412b10 LDR	X18, [X16, #528]    [3]

0x412b14 LDR	X0, [X16, #536]    [3]

0x412b18 LDR	X16, [X16, #552]    [3]

0x412b1c SUB	X16, X13, X16

0x412b20 SUB	X17, X17, X18,LSL #3

0x412b24 MUL	X16, X0, X16

0x412b28 ADD	X16, X17, X16,LSL #3

0x412b2c STR	XZR, [X16, X14]    [2]

0x412b30 LDRSW	X16, [X20]    [7]

0x412b34 SUB	X16, X16, X10

0x412b38 MADD	X16, X16, X12, X9

0x412b3c LDR	X17, [X16, #576]    [1]

0x412b40 LDR	X18, [X16, #600]    [1]

0x412b44 LDR	X0, [X16, #608]    [1]

0x412b48 LDR	X16, [X16, #624]    [1]

0x412b4c SUB	X16, X13, X16

0x412b50 SUB	X17, X17, X18,LSL #3

0x412b54 MUL	X16, X0, X16

0x412b58 ADD	X16, X17, X16,LSL #3

0x412b5c STR	XZR, [X16, X14]    [18]

0x412b60 LDRSW	X16, [X20]    [7]

0x412b64 SUB	X16, X16, X10

0x412b68 MADD	X16, X16, X12, X9

0x412b6c LDR	X17, [X16, #648]    [17]

0x412b70 LDR	X18, [X16, #672]    [17]

0x412b74 LDR	X0, [X16, #680]    [17]

0x412b78 LDR	X16, [X16, #696]    [17]

0x412b7c SUB	X16, X13, X16

0x412b80 SUB	X17, X17, X18,LSL #3

0x412b84 MUL	X16, X0, X16

0x412b88 ADD	X16, X17, X16,LSL #3

0x412b8c STR	XZR, [X16, X14]    [16]

0x412b90 LDRSW	X16, [X20]    [7]

0x412b94 SUB	X16, X16, X10

0x412b98 MADD	X16, X16, X12, X9

0x412b9c LDR	X17, [X16, #720]    [9]

0x412ba0 LDR	X18, [X16, #744]    [9]

0x412ba4 LDR	X0, [X16, #752]    [9]

0x412ba8 LDR	X16, [X16, #768]    [9]

0x412bac SUB	X16, X13, X16

0x412bb0 SUB	X17, X17, X18,LSL #3

0x412bb4 MUL	X16, X0, X16

0x412bb8 ADD	X16, X17, X16,LSL #3

0x412bbc STR	XZR, [X16, X14]    [8]

0x412bc0 ADD	X14, X14, #8

0x412bc4 B.HI	4129a8

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/build_field.f90: 103 - 115

--------------------------------------------------------------------------------

103:       DO j=chunk%tiles(tile)%t_xmin-2,chunk%tiles(tile)%t_xmax+3

104:         chunk%tiles(tile)%field%work_array1(j,k)=0.0

105:         chunk%tiles(tile)%field%work_array2(j,k)=0.0

106:         chunk%tiles(tile)%field%work_array3(j,k)=0.0

107:         chunk%tiles(tile)%field%work_array4(j,k)=0.0

108:         chunk%tiles(tile)%field%work_array5(j,k)=0.0

109:         chunk%tiles(tile)%field%work_array6(j,k)=0.0

110:         chunk%tiles(tile)%field%work_array7(j,k)=0.0

111:

112:         chunk%tiles(tile)%field%xvel0(j,k)=0.0

113:         chunk%tiles(tile)%field%xvel1(j,k)=0.0

114:         chunk%tiles(tile)%field%yvel0(j,k)=0.0

115:         chunk%tiles(tile)%field%yvel1(j,k)=0.0

Coverage (%)	Name	Module
►99.15+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	build_field_..omp_par
Source	build_field.f90:103-115
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.17
CQA cycles if no scalar integer	22.17
CQA cycles if FP arith vectorized	22.17
CQA cycles if fully vectorized	5.54
Front-end cycles	17.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	17.25
P3 cycles	17.25
P4 cycles	17.25
P5 cycles	17.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	22.17
P11 cycles	21.83
P12 cycles	22.00
P13 cycles	5.50
P14 cycles	5.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	136.00
Nb uops	136.00
Nb loads	NA
Nb stores	11.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.49
Bytes prefetched	0.00
Bytes loaded	33.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	11.00
Stride unknown	11.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	build_field_..omp_par
Source	build_field.f90:103-115
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.17
CQA cycles if no scalar integer	22.17
CQA cycles if FP arith vectorized	22.17
CQA cycles if fully vectorized	5.54
Front-end cycles	17.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	17.25
P3 cycles	17.25
P4 cycles	17.25
P5 cycles	17.25
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	22.17
P11 cycles	21.83
P12 cycles	22.00
P13 cycles	5.50
P14 cycles	5.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	136.00
Nb uops	136.00
Nb loads	NA
Nb stores	11.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.49
Bytes prefetched	0.00
Bytes loaded	33.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	11.00
Stride unknown	11.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	build_field_..omp_par
Source file and lines	build_field.f90:103-115
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/build_field.f90:103-115.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 22.17 to 5.54 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 11 occurrence(s)
Constant non-unit stride: 11 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 33 bytes.

General properties

nb instructions	136
nb uops	136
loop length	544
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	17.25	17.25	17.25	17.25	0.00	0.00	0.00	0.00	22.17	21.83	22.00	5.50	5.50
cycles	0.50	0.50	17.25	17.25	17.25	17.25	0.00	0.00	0.00	0.00	22.17	21.83	22.00	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.00
Dispatch	22.17
Data deps.	1.00
Overall L1	22.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.17 cycles. At this rate:

1% of peak load performance is reached (1.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4129a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1080]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1328]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1344]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1368]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1392]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1400]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1440]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1464]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1472]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1488]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1512]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1536]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1544]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1560]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #528]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #536]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #552]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #576]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #600]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #608]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #624]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #648]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #672]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #680]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #696]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #720]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #744]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #752]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #768]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B.HI 4129a8 <build_field_..omp_par+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	build_field_..omp_par
Source file and lines	build_field.f90:103-115
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 11 occurrence(s)
Constant non-unit stride: 11 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 33 bytes.

General properties

nb instructions	136
nb uops	136
loop length	544
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	17.25	17.25	17.25	17.25	0.00	0.00	0.00	0.00	22.17	21.83	22.00	5.50	5.50
cycles	0.50	0.50	17.25	17.25	17.25	17.25	0.00	0.00	0.00	0.00	22.17	21.83	22.00	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.00
Dispatch	22.17
Data deps.	1.00
Overall L1	22.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.17 cycles. At this rate:

1% of peak load performance is reached (1.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4129a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1080]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1328]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1344]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1368]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1392]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1400]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1440]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1464]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1472]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1488]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #1512]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #1536]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #1544]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #1560]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #528]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #536]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #552]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #576]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #600]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #608]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #624]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #648]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #672]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #680]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #696]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDRSW X16, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X16, X16, X12, X9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X17, [X16, #720]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X16, #744]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X16, #752]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16, #768]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X17, X17, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X16, X0, X16	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X16, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR XZR, [X16, X14]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B.HI 4129a8 <build_field_..omp_par+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code