OV - exec - Loop 214

	Loop Id: 214	Module: exec	Source: generate_chunk_kernel.f90:127-155 [...]	Coverage: 0.03%

0x422d04 AND	P5.B, P3/Z, P3.B, P11.B

0x422d08 ADD	Z4.D, Z2.D, Z0.D

0x422d0c LDR	X14, [SP, #280]    [9]

0x422d10 LDR	X26, [SP, #312]    [9]

0x422d14 ADD	W8, W8, W21

0x422d18 ADD	Z2.D, Z2.D, Z19.D

0x422d1c FMOV	W20, S4

0x422d20 PTRUE	P2.D, ALL

0x422d24 LD1W	{Z3.D}, P5/Z, [X1, Z21.D,LSL #2]    [20]

0x422d28 MOVPRFX	Z5, Z4

0x422d2c SXTW	Z5.D, P2/M, Z4.D

0x422d30 AND	P0.B, P3/Z, P3.B, P9.B

0x422d34 ADD	W20, W20, #1

0x422d38 SUB	Z5.D, Z5.D, Z18.D

0x422d3c LD1D	{Z6.D}, P0/Z, [X25, Z21.D,LSL #3]    [16]

0x422d40 LD1D	{Z7.D}, P0/Z, [X0, Z21.D,LSL #3]    [17]

0x422d44 SBFM	X20, X20, #0, #31

0x422d48 SUB	X20, X20, X19

0x422d4c FMOV	X18, D5

0x422d50 LD1D	{Z4.D}, P0/Z, [X23, X20,LSL #3]    [13]

0x422d54 LD1D	{Z17.D}, P0/Z, [X23, X18,LSL #3]    [13]

0x422d58 AND	Z3.D, Z3.D, #0x0

0x422d5c CMPEQ	P4.D, P2/Z, Z1.D, Z3.D

0x422d60 CMPNE	P7.D, P2/Z, Z1.D, Z3.D

0x422d64 FCMGE	P1.D, P2/Z, Z4.D, Z6.D

0x422d68 FCMGT	P1.D, P1/Z, Z7.D, Z17.D

0x422d6c AND	P6.B, P5/Z, P5.B, P4.B

0x422d70 AND	P5.B, P5/Z, P5.B, P7.B

0x422d74 AND	P4.B, P11/Z, P11.B, P4.B

0x422d78 AND	P0.B, P0/Z, P0.B, P1.B

0x422d7c LD1W	{Z3.D}, P5/Z, [X14, Z21.D,LSL #2]    [8]

0x422d80 LDR	X14, [SP, #272]    [9]

0x422d84 AND	P1.B, P9/Z, P9.B, P1.B

0x422d88 LD1D	{Z7.D}, P6/Z, [X14, X18,LSL #3]    [7]

0x422d8c LDR	X14, [SP, #296]    [9]

0x422d90 LD1D	{Z16.D}, P6/Z, [X26, Z21.D,LSL #3]    [19]

0x422d94 LD1D	{Z4.D}, P6/Z, [X30, Z21.D,LSL #3]    [11]

0x422d98 LD1D	{Z6.D}, P6/Z, [X27, Z21.D,LSL #3]    [22]

0x422d9c FSUB	Z4.D, Z4.D, Z6.D

0x422da0 AND	Z3.D, Z3.D, #0x0

0x422da4 FSUB	Z7.D, Z7.D, Z16.D

0x422da8 FMUL	Z6.D, Z7.D, Z7.D

0x422dac LD1D	{Z16.D}, P0/Z, [X10, Z21.D,LSL #3]    [10]

0x422db0 CMPEQ	P10.D, P2/Z, Z1.D, Z3.D

0x422db4 FMAD	Z4.D, P2/M, Z4.D, Z6.D

0x422db8 FSQRT	Z4.D, P2/M, Z4.D

0x422dbc LD1D	{Z6.D}, P0/Z, [X22, Z21.D,LSL #3]    [12]

0x422dc0 LD1D	{Z3.D}, P6/Z, [X14, Z21.D,LSL #3]    [6]

0x422dc4 LDR	X14, [SP, #288]    [9]

0x422dc8 LD1D	{Z7.D}, P0/Z, [X14, Z21.D,LSL #3]    [5]

0x422dcc LDR	X14, [SP, #304]    [9]

0x422dd0 FCMGE	P6.D, P2/Z, Z16.D, Z6.D

0x422dd4 LD1D	{Z6.D}, P0/Z, [X5, Z21.D,LSL #3]    [1]

0x422dd8 AND	P0.B, P5/Z, P5.B, P10.B

0x422ddc FCMGT	P5.D, P6/Z, Z7.D, Z6.D

0x422de0 LD1D	{Z7.D}, P0/Z, [X23, X18,LSL #3]    [13]

0x422de4 SBFM	X18, X2, #0, #31

0x422de8 LD1D	{Z6.D}, P0/Z, [X26, Z21.D,LSL #3]    [19]

0x422dec ADD	W2, W2, W21

0x422df0 SUB	X18, X18, X19

0x422df4 AND	P1.B, P1/Z, P1.B, P5.B

0x422df8 ADD	X20, X18, X11

0x422dfc FCMEQ	P6.D, P2/Z, Z7.D, Z6.D

0x422e00 LD1D	{Z6.D}, P0/Z, [X5, Z21.D,LSL #3]    [1]

0x422e04 LD1D	{Z7.D}, P0/Z, [X27, Z21.D,LSL #3]    [22]

0x422e08 FCMGE	P0.D, P2/Z, Z3.D, Z4.D

0x422e0c SEL	P0.B, P1, P1.B, P0.B

0x422e10 SEL	P0.B, P4, P0.B, P1.B

0x422e14 FCMEQ	P5.D, P6/Z, Z6.D, Z7.D

0x422e18 AND	P6.B, P11/Z, P11.B, P7.B

0x422e1c AND	P1.B, P6/Z, P6.B, P10.B

0x422e20 SEL	P4.B, P0, P0.B, P5.B

0x422e24 SEL	P0.B, P1, P4.B, P0.B

0x422e28 AND	P0.B, P3/Z, P3.B, P0.B

0x422e2c WHILELO	P3.D, W8, W3

0x422e30 LD1D	{Z3.D}, P0/Z, [X14, Z21.D,LSL #3]    [4]

0x422e34 ST1D	{Z3.D}, P0, [X6, Z5.D,LSL #3]    [2]

0x422e38 LD1D	{Z3.D}, P0/Z, [X15, Z21.D,LSL #3]    [15]

0x422e3c ST1D	{Z3.D}, P0, [X7, Z5.D,LSL #3]    [3]

0x422e40 LD1D	{Z3.D}, P0/Z, [X16, Z21.D,LSL #3]    [18]

0x422e44 LD1D	{Z4.D}, P0/Z, [X17, Z21.D,LSL #3]    [21]

0x422e48 ST1D	{Z3.D}, P0, [X28, X20,LSL #3]    [23]

0x422e4c ST1D	{Z4.D}, P0, [X24, X20,LSL #3]    [14]

0x422e50 ADD	X20, X18, #1

0x422e54 ADD	X18, X18, X13

0x422e58 ADD	X26, X20, X11

0x422e5c ADD	X20, X20, X13

0x422e60 ST1D	{Z3.D}, P0, [X28, X26,LSL #3]    [23]

0x422e64 ST1D	{Z4.D}, P0, [X24, X26,LSL #3]    [14]

0x422e68 ST1D	{Z3.D}, P0, [X28, X18,LSL #3]    [23]

0x422e6c ST1D	{Z4.D}, P0, [X24, X18,LSL #3]    [14]

0x422e70 ST1D	{Z3.D}, P0, [X28, X20,LSL #3]    [23]

0x422e74 ST1D	{Z4.D}, P0, [X24, X20,LSL #3]    [14]

0x422e78 B.MI	422d04

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 127 - 155

--------------------------------------------------------------------------------

127:       !$OMP SIMD

128:         DO j=x_min-2,x_max+2

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

[...]

142:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

[...]

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

Coverage (%)	Name	Source Location	Module
►98.44+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:50	exec
○	start	start.f90:106	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P4,
Function	_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par
Source	generate_chunk_kernel.f90:127-131,generate_chunk_kernel.f90:142-144,generate_chunk_kernel.f90:154-155
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	21.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	21.00
CQA cycles if fully vectorized	16.50
Front-end cycles	11.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	21.00
P5 cycles	4.00
P6 cycles	12.00
P7 cycles	12.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	16.50
P11 cycles	16.50
P12 cycles	6.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	94.00
Nb loads	NA
Nb stores	10.00
Nb stack references	6.00
FLOP/cycle	1.14
Nb FLOP add-sub	8.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	50.29
Bytes prefetched	0.00
Bytes loaded	736.00
Bytes stored	320.00
Stride 0	12.00
Stride 1	0.00
Stride n	0.00
Stride unknown	5.00
Stride indirect	6.00
Vectorization ratio all	92.11
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	71.43
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	87.88
Vector-efficiency ratio all	81.74
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	75.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	63.26

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P4,
Function	_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par
Source	generate_chunk_kernel.f90:127-131,generate_chunk_kernel.f90:142-144,generate_chunk_kernel.f90:154-155
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	21.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	21.00
CQA cycles if fully vectorized	16.50
Front-end cycles	11.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	21.00
P5 cycles	4.00
P6 cycles	12.00
P7 cycles	12.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	16.50
P11 cycles	16.50
P12 cycles	6.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	94.00
Nb loads	NA
Nb stores	10.00
Nb stack references	6.00
FLOP/cycle	1.14
Nb FLOP add-sub	8.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	50.29
Bytes prefetched	0.00
Bytes loaded	736.00
Bytes stored	320.00
Stride 0	12.00
Stride 1	0.00
Stride n	0.00
Stride unknown	5.00
Stride indirect	6.00
Vectorization ratio all	92.11
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	71.43
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	87.88
Vector-efficiency ratio all	81.74
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	75.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	63.26

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par
Source file and lines	generate_chunk_kernel.f90:127-155
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:127-131,142-144,154-155.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.00 to 20.00 cycles (1.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is highly vectorized. 81% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 21.00 to 16.50 cycles (1.27x speedup).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

71% of VPU addition or subtraction instructions are used in vector version.
87% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 5 occurrence(s)
Irregular (variable stride) or indirect: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
4: square root

The binary loop is loading 736 bytes. The binary loop is storing 320 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	94
loop length	376
used w registers	5
used x registers	24
used b registers	0
used h registers	0
used s registers	2
used d registers	1
used q registers	0
used v registers	0
used z registers	13
nb stack references	6
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.00	4.00	21.00	4.00	12.00	12.00	5.00	5.00	16.50	16.50	6.00	0.00	0.00
cycles	0.50	0.50	4.00	4.00	21.00	4.00	12.00	12.00	5.00	5.00	16.50	16.50	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.75
Dispatch	21.00
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	21.00

Vectorization ratios

INT

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	60%
fma	NA (no fma vectorizable/vectorized instructions)
other	91%

all	85%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	77%

INT+FP

all	92%
load	100%
store	100%
mul	100%
add-sub	71%
fma	100%
div/sqrt	100%
other	87%

Vector efficiency ratios

INT

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
other	56%

all	88%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	81%

INT+FP

all	81%
load	100%
store	100%
mul	100%
add-sub	75%
fma	100%
div/sqrt	100%
other	63%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.00 cycles. At this rate:

36% of peak load performance is reached (35.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 422d04

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
AND P5.B, P3/Z, P3.B, P11.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADD Z4.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR X14, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X26, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W8, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD Z2.D, Z2.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMOV W20, S4	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (12.5%)
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1W {Z3.D}, P5/Z, [X1, Z21.D,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z5.D, P2/M, Z4.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
AND P0.B, P3/Z, P3.B, P9.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB Z5.D, Z5.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z6.D}, P0/Z, [X25, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z7.D}, P0/Z, [X0, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SBFM X20, X20, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X20, X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X18, D5	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LD1D {Z4.D}, P0/Z, [X23, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z17.D}, P0/Z, [X23, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
AND Z3.D, Z3.D, #0x0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
CMPEQ P4.D, P2/Z, Z1.D, Z3.D	1	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
CMPNE P7.D, P2/Z, Z1.D, Z3.D	1	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
FCMGE P1.D, P2/Z, Z4.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P1.D, P1/Z, Z7.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
AND P6.B, P5/Z, P5.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P5.B, P5/Z, P5.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P4.B, P11/Z, P11.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P0.B, P0/Z, P0.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1W {Z3.D}, P5/Z, [X14, Z21.D,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR X14, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
AND P1.B, P9/Z, P9.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z7.D}, P6/Z, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR X14, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LD1D {Z16.D}, P6/Z, [X26, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P6/Z, [X30, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z6.D}, P6/Z, [X27, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z4.D, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
AND Z3.D, Z3.D, #0x0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z6.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z16.D}, P0/Z, [X10, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
CMPEQ P10.D, P2/Z, Z1.D, Z3.D	1	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
FMAD Z4.D, P2/M, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z4.D, P2/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
LD1D {Z6.D}, P0/Z, [X22, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z3.D}, P6/Z, [X14, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR X14, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LD1D {Z7.D}, P0/Z, [X14, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR X14, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FCMGE P6.D, P2/Z, Z16.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z6.D}, P0/Z, [X5, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
AND P0.B, P5/Z, P5.B, P10.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FCMGT P5.D, P6/Z, Z7.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z7.D}, P0/Z, [X23, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SBFM X18, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z6.D}, P0/Z, [X26, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD W2, W2, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X18, X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
AND P1.B, P1/Z, P1.B, P5.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADD X20, X18, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FCMEQ P6.D, P2/Z, Z7.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z6.D}, P0/Z, [X5, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z7.D}, P0/Z, [X27, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FCMGE P0.D, P2/Z, Z3.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
SEL P0.B, P1, P1.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (100.0%)
SEL P0.B, P4, P0.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (100.0%)
FCMEQ P5.D, P6/Z, Z6.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
AND P6.B, P11/Z, P11.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P1.B, P6/Z, P6.B, P10.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL P4.B, P0, P0.B, P5.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (100.0%)
SEL P0.B, P1, P4.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (100.0%)
AND P0.B, P3/Z, P3.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
WHILELO P3.D, W8, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LD1D {Z3.D}, P0/Z, [X14, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P0/Z, [X15, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X7, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P0/Z, [X16, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P0/Z, [X17, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X28, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z4.D}, P0, [X24, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X20, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X18, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X26, X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X20, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ST1D {Z3.D}, P0, [X28, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z4.D}, P0, [X24, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X28, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z4.D}, P0, [X24, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X28, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z4.D}, P0, [X24, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
B.MI 422d04 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0xb14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par
Source file and lines	generate_chunk_kernel.f90:127-155
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

71% of VPU addition or subtraction instructions are used in vector version.
87% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 5 occurrence(s)
Irregular (variable stride) or indirect: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
4: square root

The binary loop is loading 736 bytes. The binary loop is storing 320 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	94
loop length	376
used w registers	5
used x registers	24
used b registers	0
used h registers	0
used s registers	2
used d registers	1
used q registers	0
used v registers	0
used z registers	13
nb stack references	6
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.00	4.00	21.00	4.00	12.00	12.00	5.00	5.00	16.50	16.50	6.00	0.00	0.00
cycles	0.50	0.50	4.00	4.00	21.00	4.00	12.00	12.00	5.00	5.00	16.50	16.50	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.75
Dispatch	21.00
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	21.00

Vectorization ratios

INT

all	93%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	60%
fma	NA (no fma vectorizable/vectorized instructions)
other	91%

all	85%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	77%

INT+FP

all	92%
load	100%
store	100%
mul	100%
add-sub	71%
fma	100%
div/sqrt	100%
other	87%

Vector efficiency ratios

INT

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
other	56%

all	88%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	81%

INT+FP

all	81%
load	100%
store	100%
mul	100%
add-sub	75%
fma	100%
div/sqrt	100%
other	63%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.00 cycles. At this rate:

36% of peak load performance is reached (35.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 422d04

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
AND P5.B, P3/Z, P3.B, P11.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADD Z4.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR X14, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X26, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W8, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD Z2.D, Z2.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMOV W20, S4	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (12.5%)
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1W {Z3.D}, P5/Z, [X1, Z21.D,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z5.D, P2/M, Z4.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
AND P0.B, P3/Z, P3.B, P9.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB Z5.D, Z5.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z6.D}, P0/Z, [X25, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z7.D}, P0/Z, [X0, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SBFM X20, X20, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X20, X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X18, D5	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LD1D {Z4.D}, P0/Z, [X23, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z17.D}, P0/Z, [X23, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
AND Z3.D, Z3.D, #0x0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
CMPEQ P4.D, P2/Z, Z1.D, Z3.D	1	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
CMPNE P7.D, P2/Z, Z1.D, Z3.D	1	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
FCMGE P1.D, P2/Z, Z4.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P1.D, P1/Z, Z7.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
AND P6.B, P5/Z, P5.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P5.B, P5/Z, P5.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P4.B, P11/Z, P11.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P0.B, P0/Z, P0.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1W {Z3.D}, P5/Z, [X14, Z21.D,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR X14, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
AND P1.B, P9/Z, P9.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z7.D}, P6/Z, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR X14, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LD1D {Z16.D}, P6/Z, [X26, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P6/Z, [X30, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z6.D}, P6/Z, [X27, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z4.D, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
AND Z3.D, Z3.D, #0x0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z6.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z16.D}, P0/Z, [X10, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
CMPEQ P10.D, P2/Z, Z1.D, Z3.D	1	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
FMAD Z4.D, P2/M, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z4.D, P2/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
LD1D {Z6.D}, P0/Z, [X22, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z3.D}, P6/Z, [X14, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR X14, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LD1D {Z7.D}, P0/Z, [X14, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR X14, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FCMGE P6.D, P2/Z, Z16.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z6.D}, P0/Z, [X5, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
AND P0.B, P5/Z, P5.B, P10.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FCMGT P5.D, P6/Z, Z7.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z7.D}, P0/Z, [X23, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SBFM X18, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z6.D}, P0/Z, [X26, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD W2, W2, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X18, X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
AND P1.B, P1/Z, P1.B, P5.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADD X20, X18, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FCMEQ P6.D, P2/Z, Z7.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z6.D}, P0/Z, [X5, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z7.D}, P0/Z, [X27, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FCMGE P0.D, P2/Z, Z3.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
SEL P0.B, P1, P1.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (100.0%)
SEL P0.B, P4, P0.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (100.0%)
FCMEQ P5.D, P6/Z, Z6.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
AND P6.B, P11/Z, P11.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P1.B, P6/Z, P6.B, P10.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL P4.B, P0, P0.B, P5.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (100.0%)
SEL P0.B, P1, P4.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (100.0%)
AND P0.B, P3/Z, P3.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
WHILELO P3.D, W8, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LD1D {Z3.D}, P0/Z, [X14, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P0/Z, [X15, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X7, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P0/Z, [X16, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P0/Z, [X17, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X28, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z4.D}, P0, [X24, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X20, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X18, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X26, X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X20, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ST1D {Z3.D}, P0, [X28, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z4.D}, P0, [X24, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X28, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z4.D}, P0, [X24, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z3.D}, P0, [X28, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
ST1D {Z4.D}, P0, [X24, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
B.MI 422d04 <_QMgenerate_chunk_kernel_modulePgenerate_chunk_kernel..omp_par+0xb14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code