OV - exec - Loop 250

	Loop Id: 250	Module: exec	Source: ideal_gas_kernel.f90:48-55	Coverage: 4.19%

0x423f80 ADD	X18, X15, W16,SXTW

0x423f84 ADD	W17, W17, W12

0x423f88 ADD	W16, W16, W12

0x423f8c LD1D	{Z3.D}, P2/Z, [X21, X18,LSL #3]    [1]

0x423f90 LD1D	{Z6.D}, P2/Z, [X22, X18,LSL #3]    [2]

0x423f94 FMUL	Z5.D, Z3.D, Z2.D

0x423f98 MOVPRFX	Z4, Z1

0x423f9c FDIV	Z4.D, P1/M, Z4.D, Z3.D

0x423fa0 FMUL	Z3.D, Z3.D, Z0.D

0x423fa4 FMUL	Z5.D, Z5.D, Z6.D

0x423fa8 FMUL	Z3.D, Z3.D, Z5.D

0x423fac ST1D	{Z5.D}, P2, [X23, X18,LSL #3]    [3]

0x423fb0 FSQRT	Z3.D, P1/M, Z3.D

0x423fb4 FABS	Z4.D, P1/M, Z4.D

0x423fb8 FMUL	Z3.D, Z3.D, Z4.D

0x423fbc ST1D	{Z3.D}, P2, [X24, X18,LSL #3]    [4]

0x423fc0 WHILELO	P2.D, W17, W13

0x423fc4 B.MI	423f80

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90: 48 - 55

--------------------------------------------------------------------------------

48:     !$OMP SIMD

49:       DO j=x_min,x_max

50:         v=1.0_8/density(j,k)

51:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

52:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

53:         pressurebyvolume=-density(j,k)*pressure(j,k)

54:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

55:         soundspeed(j,k)=SQRT(sound_speed_squared)

Coverage (%)	Name	Module
►98.44+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.11 - 6.26
Bottlenecks	P6, P8,
Function	_QMideal_gas_kernel_modulePideal_gas_kernel..omp_par
Source	ideal_gas_kernel.f90:48-55
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.99 - 28.17
CQA cycles if no scalar integer	13.99 - 28.17
CQA cycles if FP arith vectorized	13.99 - 28.17
CQA cycles if fully vectorized	13.99 - 28.17
Front-end cycles	2.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.00 - 0.99
Nb FLOP add-sub	0.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.54 - 9.15
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	85.71
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	93.75
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.11 - 6.26
Bottlenecks	P6, P8,
Function	_QMideal_gas_kernel_modulePideal_gas_kernel..omp_par
Source	ideal_gas_kernel.f90:48-55
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.99 - 28.17
CQA cycles if no scalar integer	13.99 - 28.17
CQA cycles if FP arith vectorized	13.99 - 28.17
CQA cycles if fully vectorized	13.99 - 28.17
Front-end cycles	2.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.00 - 0.99
Nb FLOP add-sub	0.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.54 - 9.15
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	85.71
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	93.75
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMideal_gas_kernel_modulePideal_gas_kernel..omp_par
Source file and lines	ideal_gas_kernel.f90:48-55
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:48-55.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

85% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 3.50 cycles (8.05x speedup).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

20: multiply
4: divide
4: square root

The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	18
nb uops	18
loop length	72
used w registers	4
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	7
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	4.50	4.50	1.00	1.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	4.50	4.50	2.50	2.50	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Dispatch	4.50
DIV/SQRT	13.99-28.17
Data deps.	1.00
Overall L1	13.99-28.17

Vectorization ratios

INT

all	66%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	85%
load	100%
store	100%
mul	100%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	93%
load	100%
store	100%
mul	100%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.17 cycles. At this rate:

2% of peak load performance is reached (2.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 423f80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD X18, X15, W16,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	2	0.50	N/A
ADD W17, W17, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W16, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
LD1D {Z3.D}, P2/Z, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z5.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z4, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z4.D, P1/M, Z4.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z3.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z3.D, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z5.D}, P2, [X23, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FSQRT Z3.D, P1/M, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FABS Z4.D, P1/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z3.D}, P2, [X24, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W17, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 423f80 <_QMideal_gas_kernel_modulePideal_gas_kernel..omp_par+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMideal_gas_kernel_modulePideal_gas_kernel..omp_par
Source file and lines	ideal_gas_kernel.f90:48-55
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

85% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 3.50 cycles (8.05x speedup).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

20: multiply
4: divide
4: square root

The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	18
nb uops	18
loop length	72
used w registers	4
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	7
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	4.50	4.50	1.00	1.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	4.50	4.50	2.50	2.50	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Dispatch	4.50
DIV/SQRT	13.99-28.17
Data deps.	1.00
Overall L1	13.99-28.17

Vectorization ratios

INT

all	66%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	85%
load	100%
store	100%
mul	100%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	93%
load	100%
store	100%
mul	100%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.17 cycles. At this rate:

2% of peak load performance is reached (2.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 423f80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ADD X18, X15, W16,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	2	0.50	N/A
ADD W17, W17, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W16, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
LD1D {Z3.D}, P2/Z, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z5.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z4, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z4.D, P1/M, Z4.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z3.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z3.D, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z5.D}, P2, [X23, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FSQRT Z3.D, P1/M, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FABS Z4.D, P1/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z3.D}, P2, [X24, X18,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P2.D, W17, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 423f80 <_QMideal_gas_kernel_modulePideal_gas_kernel..omp_par+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code