OV - exec - Loop 55

	Loop Id: 55	Module: exec	Source: accelerate_kernel.f90:61-75 [...]	Coverage: 7.01%

0x418180 SUB	W15, W7, #1

0x418184 SBFM	X12, X7, #0, #31

0x418188 SBFM	X15, X15, #0, #31

0x41818c SUB	X12, X12, X24

0x418190 SUB	X15, X15, X24

0x418194 ADD	X8, X12, X18

0x418198 ADD	X14, X12, X0

0x41819c ADD	X13, X12, X1

0x4181a0 LD1D	{Z20.D}, P2/Z, [X3, X12,LSL #3]    [14]

0x4181a4 LD1D	{Z17.D}, P2/Z, [X2, X12,LSL #3]    [12]

0x4181a8 ADD	X10, X15, X18

0x4181ac LD1D	{Z5.D}, P2/Z, [X23, X8,LSL #3]    [8]

0x4181b0 ADD	X9, X15, X0

0x4181b4 LD1D	{Z6.D}, P2/Z, [X26, X14,LSL #3]    [10]

0x4181b8 LD1D	{Z18.D}, P2/Z, [X26, X8,LSL #3]    [10]

0x4181bc LD1D	{Z21.D}, P2/Z, [X3, X15,LSL #3]    [14]

0x4181c0 LD1D	{Z3.D}, P2/Z, [X22, X10,LSL #3]    [7]

0x4181c4 LD1D	{Z4.D}, P2/Z, [X23, X10,LSL #3]    [8]

0x4181c8 LD1D	{Z7.D}, P2/Z, [X26, X9,LSL #3]    [10]

0x4181cc LD1D	{Z19.D}, P2/Z, [X26, X10,LSL #3]    [10]

0x4181d0 FMUL	Z3.D, Z4.D, Z3.D

0x4181d4 LD1D	{Z4.D}, P2/Z, [X22, X8,LSL #3]    [7]

0x4181d8 FSUB	Z16.D, Z7.D, Z6.D

0x4181dc FSUB	Z18.D, Z19.D, Z18.D

0x4181e0 LD1D	{Z19.D}, P2/Z, [X19, X14,LSL #3]    [15]

0x4181e4 FSUB	Z6.D, Z20.D, Z6.D

0x4181e8 LD1D	{Z20.D}, P2/Z, [X19, X9,LSL #3]    [15]

0x4181ec FSUB	Z7.D, Z21.D, Z7.D

0x4181f0 CNTD	X8, ALL

0x4181f4 ADD	W30, W30, W8

0x4181f8 ADD	W7, W7, W8

0x4181fc LDUR	W8, [X29, #488]    [16]

0x418200 FMLA	Z3.D, P1/M, Z5.D, Z4.D

0x418204 LD1D	{Z4.D}, P2/Z, [X22, X14,LSL #3]    [7]

0x418208 LD1D	{Z5.D}, P2/Z, [X23, X14,LSL #3]    [8]

0x41820c FMUL	Z6.D, Z6.D, Z19.D

0x418210 FMLA	Z6.D, P1/M, Z7.D, Z20.D

0x418214 LD1D	{Z7.D}, P2/Z, [X4, X15,LSL #3]    [1]

0x418218 FMLA	Z3.D, P1/M, Z5.D, Z4.D

0x41821c LD1D	{Z4.D}, P2/Z, [X22, X9,LSL #3]    [7]

0x418220 LD1D	{Z5.D}, P2/Z, [X23, X9,LSL #3]    [8]

0x418224 FMLA	Z3.D, P1/M, Z5.D, Z4.D

0x418228 LD1D	{Z5.D}, P2/Z, [X25, X13,LSL #3]    [9]

0x41822c LD1D	{Z4.D}, P2/Z, [X11, X13,LSL #3]    [5]

0x418230 FMUL	Z3.D, Z3.D, Z1.D

0x418234 FMUL	Z16.D, Z16.D, Z5.D

0x418238 FDIVR	Z3.D, P1/M, Z3.D, Z2.D

0x41823c FMLA	Z16.D, P1/M, Z18.D, Z17.D

0x418240 LD1D	{Z18.D}, P2/Z, [X28, X13,LSL #3]    [13]

0x418244 FMAD	Z6.D, P1/M, Z3.D, Z18.D

0x418248 LD1D	{Z18.D}, P2/Z, [X5, X15,LSL #3]    [2]

0x41824c ST1D	{Z6.D}, P2, [X21, X13,LSL #3]    [6]

0x418250 LD1D	{Z6.D}, P2/Z, [X4, X12,LSL #3]    [1]

0x418254 FSUB	Z6.D, Z7.D, Z6.D

0x418258 LD1D	{Z7.D}, P2/Z, [X5, X12,LSL #3]    [2]

0x41825c FMAD	Z5.D, P1/M, Z6.D, Z16.D

0x418260 LD1D	{Z6.D}, P2/Z, [X20, X9,LSL #3]    [4]

0x418264 FSUB	Z21.D, Z18.D, Z7.D

0x418268 FMLA	Z5.D, P1/M, Z21.D, Z17.D

0x41826c FSUB	Z6.D, Z18.D, Z6.D

0x418270 FMLA	Z4.D, P1/M, Z5.D, Z3.D

0x418274 LD1D	{Z5.D}, P2/Z, [X20, X14,LSL #3]    [4]

0x418278 FSUB	Z5.D, Z7.D, Z5.D

0x41827c ST1D	{Z4.D}, P2, [X27, X13,LSL #3]    [11]

0x418280 LD1D	{Z4.D}, P2/Z, [X6, X12,LSL #3]    [3]

0x418284 FMUL	Z5.D, Z5.D, Z19.D

0x418288 FMLA	Z5.D, P1/M, Z6.D, Z20.D

0x41828c FMAD	Z3.D, P1/M, Z5.D, Z4.D

0x418290 ST1D	{Z3.D}, P2, [X6, X12,LSL #3]    [3]

0x418294 WHILELO	P2.D, W30, W8

0x418298 B.MI	418180

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 61 - 75

--------------------------------------------------------------------------------

61:     !$OMP SIMD

62:       DO j=x_min,x_max+1

63:         stepbymass_s=halfdt/((density0(j-1,k-1)*volume(j-1,k-1)  &

[...]

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	accelerate_kernel	accelerate_kernel.f90:83	exec
○	accelerate	accelerate.f90:41	exec
○	hydro	hydro.f90:58	exec
○	main	clover_leaf.f90:76	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par
Source	accelerate_kernel.f90:61-63,accelerate_kernel.f90:69-75
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	15.00
Front-end cycles	8.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	3.50
P6 cycles	12.50
P7 cycles	12.50
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	15.00
P11 cycles	15.00
P12 cycles	1.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	71.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	9.60
Nb FLOP add-sub	32.00
Nb FLOP mul	20.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.20
Bytes prefetched	0.00
Bytes loaded	867.00
Bytes stored	96.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	15.00
Vectorization ratio all	98.21
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	98.44
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	90.28
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P10, P11,
Function	_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par
Source	accelerate_kernel.f90:61-63,accelerate_kernel.f90:69-75
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	15.00
Front-end cycles	8.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	3.50
P6 cycles	12.50
P7 cycles	12.50
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	15.00
P11 cycles	15.00
P12 cycles	1.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	71.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	9.60
Nb FLOP add-sub	32.00
Nb FLOP mul	20.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.20
Bytes prefetched	0.00
Bytes loaded	867.00
Bytes stored	96.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	15.00
Vectorization ratio all	98.21
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	98.44
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	90.28
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par
Source file and lines	accelerate_kernel.f90:61-75
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:61-63,69-75.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU addition or subtraction instructions are used in vector version.

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 15 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

76: addition or subtraction (44 inside FMA instructions)
64: multiply (44 inside FMA instructions)
4: divide

The binary loop is loading 867 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	71
nb uops	71
loop length	284
used w registers	4
used x registers	28
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	13
nb stack references	0
ADD-SUB / MUL ratio	1.60

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.88 cycles
front end	8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.50	3.50	3.50	3.50	12.50	12.50	1.50	1.50	15.00	15.00	1.00	0.00	0.00
cycles	0.50	0.50	3.50	3.50	3.50	3.50	12.50	12.50	12.00	12.00	15.00	15.00	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.88
Dispatch	15.00
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	15.00

Vectorization ratios

INT

all	96%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	88%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	97%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	90%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

60% of peak load performance is reached (57.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 418180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SUB W15, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X12, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X15, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X12, X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X15, X15, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z20.D}, P2/Z, [X3, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X10, X15, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z5.D}, P2/Z, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X9, X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z6.D}, P2/Z, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X3, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X23, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X26, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X26, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X22, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z16.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z18.D, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z6.D, Z20.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X19, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z7.D, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W30, W30, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FMLA Z3.D, P1/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X23, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z6.D, Z6.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z6.D, P1/M, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X4, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z3.D, P1/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X22, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X23, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z3.D, P1/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X25, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X11, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z3.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z3.D, P1/M, Z3.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLA Z16.D, P1/M, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X28, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z6.D, P1/M, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X5, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z6.D}, P2, [X21, X13,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z6.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X5, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z5.D, P1/M, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z21.D, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z5.D, P1/M, Z21.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FSUB Z6.D, Z18.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z4.D, P1/M, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z5.D, Z7.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z4.D}, P2, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X6, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z5.D, Z5.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z5.D, P1/M, Z6.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z3.D, P1/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z3.D}, P2, [X6, X12,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
WHILELO P2.D, W30, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 418180 <_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par
Source file and lines	accelerate_kernel.f90:61-75
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU addition or subtraction instructions are used in vector version.

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 15 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

76: addition or subtraction (44 inside FMA instructions)
64: multiply (44 inside FMA instructions)
4: divide

The binary loop is loading 867 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	71
nb uops	71
loop length	284
used w registers	4
used x registers	28
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	13
nb stack references	0
ADD-SUB / MUL ratio	1.60

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.88 cycles
front end	8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.50	3.50	3.50	3.50	12.50	12.50	1.50	1.50	15.00	15.00	1.00	0.00	0.00
cycles	0.50	0.50	3.50	3.50	3.50	3.50	12.50	12.50	12.00	12.00	15.00	15.00	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.88
Dispatch	15.00
DIV/SQRT	6.99-14.08
Data deps.	1.00
Overall L1	15.00

Vectorization ratios

INT

all	96%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	88%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	97%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	90%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

60% of peak load performance is reached (57.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 418180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SUB W15, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X12, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X15, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X12, X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X15, X15, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z20.D}, P2/Z, [X3, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z17.D}, P2/Z, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X10, X15, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z5.D}, P2/Z, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X9, X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z6.D}, P2/Z, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z21.D}, P2/Z, [X3, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z3.D}, P2/Z, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X23, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X26, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X26, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X22, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z16.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z18.D, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z19.D}, P2/Z, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z6.D, Z20.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z20.D}, P2/Z, [X19, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z7.D, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W30, W30, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W7, W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FMLA Z3.D, P1/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X23, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z6.D, Z6.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z6.D, P1/M, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X4, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z3.D, P1/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X22, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X23, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMLA Z3.D, P1/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X25, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X11, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z3.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z16.D, Z16.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z3.D, P1/M, Z3.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLA Z16.D, P1/M, Z18.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X28, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z6.D, P1/M, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z18.D}, P2/Z, [X5, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z6.D}, P2, [X21, X13,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z6.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z7.D}, P2/Z, [X5, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z5.D, P1/M, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z6.D}, P2/Z, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z21.D, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z5.D, P1/M, Z21.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FSUB Z6.D, Z18.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z4.D, P1/M, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z5.D}, P2/Z, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z5.D, Z7.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z4.D}, P2, [X27, X13,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LD1D {Z4.D}, P2/Z, [X6, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z5.D, Z5.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z5.D, P1/M, Z6.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z3.D, P1/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z3.D}, P2, [X6, X12,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
WHILELO P2.D, W30, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 418180 <_QMaccelerate_kernel_modulePaccelerate_kernel..omp_par+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code