| Loop Id: 62 | Module: exec | Source: advec_cell_kernel.f90:161-170 | Coverage: 3.61% |
|---|
| Loop Id: 62 | Module: exec | Source: advec_cell_kernel.f90:161-170 | Coverage: 3.61% |
|---|
(63) 0x419c88 CMP W9, W8 |
(63) 0x419c8c ADD W9, W9, #1 |
(63) 0x419c90 B.EQ 419de0 |
(63) 0x419c94 CBZ W13, 419c88 |
(63) 0x419c98 LDP X0, X1, [SP, #120] |
(63) 0x419c9c ADD W18, W10, W9 |
(63) 0x419ca0 CMP W15, W14 |
(63) 0x419ca4 SUB X3, XZR, X16 |
(63) 0x419ca8 ORR P2.B, P0/Z, P0.B, P0.B |
(63) 0x419cac ORR W2, WZR, W11 |
(63) 0x419cb0 SBFM X18, X18, #0, #31 |
(63) 0x419cb4 SUB X0, X18, X0 |
(63) 0x419cb8 LDR X18, [SP, #136] |
(63) 0x419cbc MUL X18, X0, X18 |
(63) 0x419cc0 MUL X0, X0, X1 |
(63) 0x419cc4 ADD X1, X22, X18,LSL #3 |
(63) 0x419cc8 B.GE 419d60 |
(63) 0x419ccc SUB X3, X0, X24 |
(63) 0x419cd0 ORR W2, WZR, WZR |
(63) 0x419cd4 HINT #0 |
(63) 0x419cd8 HINT #0 |
(63) 0x419cdc HINT #0 |
(64) 0x419ce0 ADD W4, W11, W2 |
(64) 0x419ce4 ADD W2, W2, #1 |
(64) 0x419ce8 SBFM X5, X4, #0, #31 |
(64) 0x419cec ADD W4, W4, #1 |
(64) 0x419cf0 CMP W12, W2 |
(64) 0x419cf4 SUB X5, X5, X24 |
(64) 0x419cf8 ADD X4, X3, W4,SXTW |
(64) 0x419cfc ADD X6, X5, X18 |
(64) 0x419d00 ADD X7, X5, X0 |
(64) 0x419d04 LDR D0, [X20, X6,LSL #3] |
(64) 0x419d08 LDR D1, [X21, X7,LSL #3] |
(64) 0x419d0c LDR D2, [X25, X7,LSL #3] |
(64) 0x419d10 LDR D3, [X25, X4,LSL #3] |
(64) 0x419d14 LDR D4, [X22, X6,LSL #3] |
(64) 0x419d18 FMUL D0, D1, D0 |
(64) 0x419d1c FADD D2, D0, D2 |
(64) 0x419d20 FSUB D2, D2, S3 |
(64) 0x419d24 LDR D3, [X26, X7,LSL #3] |
(64) 0x419d28 FMADD D0, D4, D0, D3 |
(64) 0x419d2c LDR D3, [X26, X4,LSL #3] |
(64) 0x419d30 FSUB D0, D0, S3 |
(64) 0x419d34 LDR D3, [X19, X7,LSL #3] |
(64) 0x419d38 FDIV D0, D0, D2 |
(64) 0x419d3c FADD D1, D3, D1 |
(64) 0x419d40 LDR D3, [X19, X4,LSL #3] |
(64) 0x419d44 FSUB D1, D1, S3 |
(64) 0x419d48 FDIV D1, D2, D1 |
(64) 0x419d4c STR D0, [X1, X5,LSL #3] |
(64) 0x419d50 STR D1, [X20, X6,LSL #3] |
(64) 0x419d54 B.HI 419ce0 |
(63) 0x419d58 B 419c88 |
0x419d60 SBFM X4, X2, #0, #31 |
0x419d64 ADD W7, W2, #1 |
0x419d68 SUB X23, X0, X24 |
0x419d6c ADD W3, W3, W16 |
0x419d70 ADD W2, W2, W16 |
0x419d74 SUB X4, X4, X24 |
0x419d78 ADD X7, X23, W7,SXTW |
0x419d7c ADD X5, X4, X18 |
0x419d80 ADD X6, X4, X0 |
0x419d84 LD1D {Z0.D}, P2/Z, [X20, X5,LSL #3] |
0x419d88 LD1D {Z1.D}, P2/Z, [X21, X6,LSL #3] |
0x419d8c LD1D {Z2.D}, P2/Z, [X25, X6,LSL #3] |
0x419d90 LD1D {Z3.D}, P2/Z, [X25, X7,LSL #3] |
0x419d94 LD1D {Z4.D}, P2/Z, [X26, X6,LSL #3] |
0x419d98 FMUL Z0.D, Z1.D, Z0.D |
0x419d9c FADD Z2.D, Z0.D, Z2.D |
0x419da0 FSUB Z2.D, Z2.D, Z3.D |
0x419da4 LD1D {Z3.D}, P2/Z, [X22, X5,LSL #3] |
0x419da8 FMAD Z0.D, P1/M, Z3.D, Z4.D |
0x419dac LD1D {Z3.D}, P2/Z, [X26, X7,LSL #3] |
0x419db0 FSUB Z0.D, Z0.D, Z3.D |
0x419db4 LD1D {Z3.D}, P2/Z, [X19, X6,LSL #3] |
0x419db8 FDIV Z0.D, P1/M, Z0.D, Z2.D |
0x419dbc FADD Z1.D, Z3.D, Z1.D |
0x419dc0 LD1D {Z3.D}, P2/Z, [X19, X7,LSL #3] |
0x419dc4 FSUB Z1.D, Z1.D, Z3.D |
0x419dc8 FDIVR Z1.D, P1/M, Z1.D, Z2.D |
0x419dcc ST1D {Z0.D}, P2, [X1, X4,LSL #3] |
0x419dd0 ST1D {Z1.D}, P2, [X20, X5,LSL #3] |
0x419dd4 WHILELO P2.D, W3, W17 |
0x419dd8 B.MI 419d60 |
0x419ddc B 419c88 |
/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 161 - 170 |
-------------------------------------------------------------------------------- |
161: !$OMP DO PRIVATE(pre_mass_s,post_mass_s,post_ener_s,advec_vol_s) |
162: DO k=y_min,y_max |
163: !$OMP SIMD |
164: DO j=x_min,x_max |
165: pre_mass_s=density1(j,k)*pre_vol(j,k) |
166: post_mass_s=pre_mass_s+mass_flux_x(j,k)-mass_flux_x(j+1,k) |
167: post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j+1,k))/post_mass_s |
168: advec_vol_s=pre_vol(j,k)+vol_flux_x(j,k)-vol_flux_x(j+1,k) |
169: density1(j,k)=post_mass_s/advec_vol_s |
170: energy1(j,k)=post_ener_s |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.44+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_launch_thread | libomp.so | |
| ○ | __kmp_launch_worker(void*) | libomp.so | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.54 - 5.12 |
| Bottlenecks | P6, P8, |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source | advec_cell_kernel.f90:163-170 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 13.99 - 28.17 |
| CQA cycles if no scalar integer | 13.99 - 28.17 |
| CQA cycles if FP arith vectorized | 13.99 - 28.17 |
| CQA cycles if fully vectorized | 13.99 - 28.17 |
| Front-end cycles | 4.00 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 2.50 |
| P3 cycles | 2.50 |
| P4 cycles | 2.50 |
| P5 cycles | 2.50 |
| P6 cycles | 4.50 |
| P7 cycles | 4.50 |
| P8 cycles | 3.50 |
| P9 cycles | 3.50 |
| P10 cycles | 5.50 |
| P11 cycles | 5.50 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 13.99 - 28.17 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 32.00 |
| Nb uops | 32.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.86 - 1.42 |
| Nb FLOP add-sub | 20.00 |
| Nb FLOP mul | 4.00 |
| Nb FLOP fma | 4.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.50 - 25.17 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 288.00 |
| Bytes stored | 64.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 90.91 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 71.43 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 92.61 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 76.79 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.54 - 5.12 |
| Bottlenecks | P6, P8, |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source | advec_cell_kernel.f90:163-170 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 13.99 - 28.17 |
| CQA cycles if no scalar integer | 13.99 - 28.17 |
| CQA cycles if FP arith vectorized | 13.99 - 28.17 |
| CQA cycles if fully vectorized | 13.99 - 28.17 |
| Front-end cycles | 4.00 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 2.50 |
| P3 cycles | 2.50 |
| P4 cycles | 2.50 |
| P5 cycles | 2.50 |
| P6 cycles | 4.50 |
| P7 cycles | 4.50 |
| P8 cycles | 3.50 |
| P9 cycles | 3.50 |
| P10 cycles | 5.50 |
| P11 cycles | 5.50 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 13.99 - 28.17 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 32.00 |
| Nb uops | 32.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.86 - 1.42 |
| Nb FLOP add-sub | 20.00 |
| Nb FLOP mul | 4.00 |
| Nb FLOP fma | 4.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.50 - 25.17 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 288.00 |
| Bytes stored | 64.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 90.91 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 71.43 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 92.61 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 76.79 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source file and lines | advec_cell_kernel.f90:161-170 |
| Module | exec |
| nb instructions | 32 |
| nb uops | 32 |
| loop length | 128 |
| used w registers | 5 |
| used x registers | 16 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 5 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 4.00 cycles |
| front end | 4.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 2.50 | 2.50 | 2.50 | 2.50 | 4.50 | 4.50 | 1.00 | 1.00 | 5.50 | 5.50 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 2.50 | 2.50 | 2.50 | 2.50 | 4.50 | 4.50 | 3.50 | 3.50 | 5.50 | 5.50 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 13.99-28.17 |
| Front-end | 4.00 |
| Dispatch | 5.50 |
| DIV/SQRT | 13.99-28.17 |
| Overall L1 | 13.99-28.17 |
| all | 84% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 90% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 71% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 87% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 18% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 92% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 76% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SBFM X4, X2, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W7, W2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X23, X0, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD W3, W3, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W2, W2, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SUB X4, X4, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X7, X23, W7,SXTW | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| ADD X5, X4, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X6, X4, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z0.D}, P2/Z, [X20, X5,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z1.D}, P2/Z, [X21, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z2.D}, P2/Z, [X25, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X25, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z4.D}, P2/Z, [X26, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMUL Z0.D, Z1.D, Z0.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| FADD Z2.D, Z0.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| FSUB Z2.D, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X22, X5,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMAD Z0.D, P1/M, Z3.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X26, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FSUB Z0.D, Z0.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X19, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FDIV Z0.D, P1/M, Z0.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 6.99-14.08 | vect (100.0%) |
| FADD Z1.D, Z3.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X19, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FSUB Z1.D, Z1.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| FDIVR Z1.D, P1/M, Z1.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 6.99-14.08 | vect (100.0%) |
| ST1D {Z0.D}, P2, [X1, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ST1D {Z1.D}, P2, [X20, X5,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| WHILELO P2.D, W3, W17 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 419d60 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x1280> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 419c88 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x11a8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Function | _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par |
| Source file and lines | advec_cell_kernel.f90:161-170 |
| Module | exec |
| nb instructions | 32 |
| nb uops | 32 |
| loop length | 128 |
| used w registers | 5 |
| used x registers | 16 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 0 |
| used z registers | 5 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 4.00 cycles |
| front end | 4.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 2.50 | 2.50 | 2.50 | 2.50 | 4.50 | 4.50 | 1.00 | 1.00 | 5.50 | 5.50 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 2.50 | 2.50 | 2.50 | 2.50 | 4.50 | 4.50 | 3.50 | 3.50 | 5.50 | 5.50 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 13.99-28.17 |
| Front-end | 4.00 |
| Dispatch | 5.50 |
| DIV/SQRT | 13.99-28.17 |
| Overall L1 | 13.99-28.17 |
| all | 84% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 90% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 71% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 87% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 18% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 92% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 76% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SBFM X4, X2, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W7, W2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SUB X23, X0, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (25.0%) |
| ADD W3, W3, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD W2, W2, W16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| SUB X4, X4, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X7, X23, W7,SXTW | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| ADD X5, X4, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X6, X4, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| LD1D {Z0.D}, P2/Z, [X20, X5,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z1.D}, P2/Z, [X21, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z2.D}, P2/Z, [X25, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X25, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| LD1D {Z4.D}, P2/Z, [X26, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMUL Z0.D, Z1.D, Z0.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| FADD Z2.D, Z0.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| FSUB Z2.D, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X22, X5,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FMAD Z0.D, P1/M, Z3.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X26, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FSUB Z0.D, Z0.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X19, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FDIV Z0.D, P1/M, Z0.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 6.99-14.08 | vect (100.0%) |
| FADD Z1.D, Z3.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z3.D}, P2/Z, [X19, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| FSUB Z1.D, Z1.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| FDIVR Z1.D, P1/M, Z1.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 6.99-14.08 | vect (100.0%) |
| ST1D {Z0.D}, P2, [X1, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ST1D {Z1.D}, P2, [X20, X5,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| WHILELO P2.D, W3, W17 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 419d60 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x1280> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| B 419c88 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x11a8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
