OV - exec - Loop 67

	Loop Id: 67	Module: exec	Source: advec_cell_kernel.f90:107-155 [...]	Coverage: 2.76%

  (65) 0x4199ec CMP	W9, W8

  (65) 0x4199f0 ADD	W9, W9, #1

  (65) 0x4199f4 ADD	W2, W2, #1

  (65) 0x4199f8 B.EQ	419bbc

  (65) 0x4199fc TBNZ	X17, #63, 4199ec

0x419a00 LDP	X18, X12, [SP, #104]

0x419a04 LDR	X7, [SP, #128]

0x419a08 ADD	X27, X17, #2

0x419a0c ORR	X3, XZR, XZR

0x419a10 ORR	X28, XZR, X13

0x419a14 ADD	X16, X12, W2,SXTW

0x419a18 SUB	X12, X13, X24

0x419a1c MADD	X16, X7, X16, X12

0x419a20 LDUR	W12, [X29, #368]

0x419a24 ADD	X4, X18, X16,LSL #3

0x419a28 LDR	X18, [SP, #120]

0x419a2c ADD	X5, X25, X16,LSL #3

0x419a30 ADD	X6, X19, X16,LSL #3

0x419a34 ADD	W16, W12, W9

0x419a38 SBFM	X16, X16, #0, #31

0x419a3c SUB	X16, X16, X18

0x419a40 MUL	X18, X16, X7

0x419a44 ADD	X7, X21, X18,LSL #3

0x419a48 LDR	X18, [SP, #136]

0x419a4c MUL	X26, X16, X18

0x419a50 B	419a7c

0x419a60 FMUL	D3, D16, D3

0x419a64 SUB	X27, X27, #1

0x419a68 ADD	X28, X28, #1

0x419a6c CMP	X27, #1

0x419a70 STR	D3, [X4, X3,LSL #3]

0x419a74 ADD	X3, X3, #1

0x419a78 B.LE	4199ec

0x419a7c LDR	D3, [X6, X3,LSL #3]

0x419a80 FCMP	D3, #0

0x419a84 B.LE	419aa0

0x419a88 ADD	W30, W1, W3

0x419a8c SUB	W18, W28, #1

0x419a90 ADD	W23, W0, W3

0x419a94 ORR	X16, XZR, X28

0x419a98 B	419abc

0x419abc SBFM	X18, X18, #0, #31

0x419ac0 FABS	D5, D3

0x419ac4 LDR	X12, [SP, #152]

0x419ac8 SBFM	X23, X23, #0, #31

0x419acc SUB	X18, X18, X24

0x419ad0 SUB	X23, X23, X24

0x419ad4 LDR	D4, [X7, X18,LSL #3]

0x419ad8 LDR	D6, [X12, X23,LSL #3]

0x419adc ADD	X23, X18, X26

0x419ae0 SUB	X18, X26, X24

0x419ae4 ADD	X30, X18, W30,SXTW

0x419ae8 ADD	X16, X18, W16,SXTW

0x419aec LDR	D7, [X20, X23,LSL #3]

0x419af0 LDR	D17, [X20, X30,LSL #3]

0x419af4 LDR	D18, [X20, X16,LSL #3]

0x419af8 FDIV	D16, D5, D4

0x419afc LDR	D5, [X14, X3,LSL #3]

0x419b00 FSUB	D17, D7, S17

0x419b04 FSUB	D18, D18, S7

0x419b08 FMUL	D19, D18, D17

0x419b0c FCMP	D19, #0

0x419b10 FMOV	D19, D7

0x419b14 FMADD	D5, D16, D5, D5

0x419b18 FDIV	D5, D5, D6

0x419b1c FSUB	D6, D0, S16

0x419b20 B.LE	419b54

0x419b24 FSUB	D16, D1, S16

0x419b28 FCMP	D18, #0

0x419b2c FABS	D17, D17

0x419b30 FABS	D18, D18

0x419b34 FNEG	D19, D16

0x419b38 FCSEL	D16, D16, D19, #12

0x419b3c FMUL	D19, D17, D5

0x419b40 FMINNM	D17, D17, D18

0x419b44 FMADD	D19, D18, D6, D19

0x419b48 FMUL	D19, D19, D2

0x419b4c FMINNM	D17, D17, D19

0x419b50 FMADD	D19, D17, D16, D7

0x419b54 LDR	D16, [X22, X23,LSL #3]

0x419b58 LDR	D17, [X22, X30,LSL #3]

0x419b5c LDR	D18, [X22, X16,LSL #3]

0x419b60 FMUL	D3, D19, D3

0x419b64 FSUB	D17, D16, S17

0x419b68 FSUB	D18, D18, S16

0x419b6c STR	D3, [X5, X3,LSL #3]

0x419b70 FMUL	D19, D18, D17

0x419b74 FCMP	D19, #0

0x419b78 B.LE	419a60

0x419b7c FMUL	D4, D7, D4

0x419b80 FABS	D19, D3

0x419b84 FCMP	D18, #0

0x419b88 FDIV	D4, D19, D4

0x419b8c FSUB	D4, D1, S4

0x419b90 FNEG	D7, D4

0x419b94 FCSEL	D4, D4, D7, #12

0x419b98 FABS	D7, D17

0x419b9c FABS	D17, D18

0x419ba0 FMUL	D5, D7, D5

0x419ba4 FMADD	D5, D17, D6, D5

0x419ba8 FMINNM	D6, D7, D17

0x419bac FMUL	D5, D5, D2

0x419bb0 FMINNM	D5, D6, D5

0x419bb4 FMADD	D16, D5, D4, D16

0x419bb8 B	419a60

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 107 - 155

--------------------------------------------------------------------------------

107:       !$OMP DO PRIVATE(upwind,donor,downwind,dif,sigmat,sigma3,sigma4,sigmav,sigma,sigmam, &

108:       !$OMP            diffuw,diffdw,limiter,wind)

109:       DO k=y_min,y_max

110:         DO j=x_min,x_max+2

111:

112:           IF(vol_flux_x(j,k).GT.0.0)THEN

113:             upwind   =j-2

114:             donor    =j-1

[...]

124:           sigmat=ABS(vol_flux_x(j,k))/pre_vol(donor,k)

125:           sigma3=(1.0_8+sigmat)*(vertexdx(j)/vertexdx(dif))

126:           sigma4=2.0_8-sigmat

127:

128:           sigma=sigmat

129:           sigmav=sigmat

130:

131:           diffuw=density1(donor,k)-density1(upwind,k)

132:           diffdw=density1(downwind,k)-density1(donor,k)

133:           wind=1.0_8

134:           IF(diffdw.LE.0.0) wind=-1.0_8

135:           IF(diffuw*diffdw.GT.0.0)THEN

136:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

137:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

138:           ELSE

139:             limiter=0.0

140:           ENDIF

141:           mass_flux_x(j,k)=vol_flux_x(j,k)*(density1(donor,k)+limiter)

142:

143:           sigmam=ABS(mass_flux_x(j,k))/(density1(donor,k)*pre_vol(donor,k))

144:           diffuw=energy1(donor,k)-energy1(upwind,k)

145:           diffdw=energy1(downwind,k)-energy1(donor,k)

146:           wind=1.0_8

147:           IF(diffdw.LE.0.0) wind=-1.0_8

148:           IF(diffuw*diffdw.GT.0.0)THEN

149:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

[...]

155:           ener_flux(j,k)=mass_flux_x(j,k)*(energy1(donor,k)+limiter)

Coverage (%)	Name	Module
►98.41+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.13
CQA speedup if FP arith vectorized	1.83
CQA speedup if fully vectorized	4.00 - 2.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source	advec_cell_kernel.f90:107-107,advec_cell_kernel.f90:110-114,advec_cell_kernel.f90:124-126,advec_cell_kernel.f90:131-132,advec_cell_kernel.f90:135-136,advec_cell_kernel.f90:141-145,advec_cell_kernel.f90:148-149,advec_cell_kernel.f90:155-155
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	6.81
CQA cycles if fully vectorized	3.13 - 5.24
Front-end cycles	12.50
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	7.75
P3 cycles	7.75
P4 cycles	7.75
P5 cycles	7.75
P6 cycles	11.50
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	11.50
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	100.00
Nb loads	NA
Nb stores	2.00
Nb stack references	5.00
FLOP/cycle	2.32
Nb FLOP add-sub	7.00
Nb FLOP mul	9.00
Nb FLOP fma	5.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.24
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	3.13
CQA speedup if FP arith vectorized	1.83
CQA speedup if fully vectorized	4.00 - 2.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source	advec_cell_kernel.f90:107-107,advec_cell_kernel.f90:110-114,advec_cell_kernel.f90:124-126,advec_cell_kernel.f90:131-132,advec_cell_kernel.f90:135-136,advec_cell_kernel.f90:141-145,advec_cell_kernel.f90:148-149,advec_cell_kernel.f90:155-155
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	6.81
CQA cycles if fully vectorized	3.13 - 5.24
Front-end cycles	12.50
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	7.75
P3 cycles	7.75
P4 cycles	7.75
P5 cycles	7.75
P6 cycles	11.50
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	11.50
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	100.00
Nb loads	NA
Nb stores	2.00
Nb stack references	5.00
FLOP/cycle	2.32
Nb FLOP add-sub	7.00
Nb FLOP mul	9.00
Nb FLOP fma	5.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.24
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source file and lines	advec_cell_kernel.f90:107-155
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:107-114,124-149,155.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:107,110-114,124-126,131-132,135-136,141-145,148-149,155.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 4.00 cycles (3.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 12.50 to 5.24 cycles (2.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 5 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

12: addition or subtraction (5 inside FMA instructions)
14: multiply (5 inside FMA instructions)
3: divide

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 9.67 FP operations per loaded or stored byte.

General properties

nb instructions	100
nb uops	100
loop length	400
used w registers	11
used x registers	24
used b registers	0
used h registers	0
used s registers	5
used d registers	12
used q registers	0
used v registers	0
used z registers	0
nb stack references	5
ADD-SUB / MUL ratio	0.78

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	7.75	7.75	7.75	7.75	11.50	11.50	11.50	11.50	6.00	6.00	6.00	0.00	0.00
cycles	3.50	3.50	7.75	7.75	7.75	7.75	11.50	11.50	11.50	11.50	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	12.50
Dispatch	11.50
DIV/SQRT	5.25-10.49
Overall L1	12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.50 to 11.50 cycles (1.09x speedup).

ASM code

In the binary file, the address of the loop is: 419abc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDP X18, X12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X27, X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, W2,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
SUB X12, X13, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X7, X16, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDUR W12, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X4, X18, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X5, X25, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X19, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X16, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL X18, X16, X7	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X7, X21, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X26, X16, X18	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 419a7c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xf9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D3, D16, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
SUB X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR D3, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.LE 4199ec <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xf0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D3, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 419aa0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xfc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W30, W1, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W18, W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W23, W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X16, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 419abc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xfdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X18, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FABS D5, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SBFM X23, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X18, X18, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X23, X23, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D6, [X12, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X23, X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X18, X26, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X18, W30,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X16, X18, W16,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR D7, [X20, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D17, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D18, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D16, D5, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D5, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D17, D7, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D18, D18, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D19, D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D5, D16, D5, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D5, D5, D6	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D6, D0, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
B.LE 419b54 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x1074>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FSUB D16, D1, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FABS D17, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D18, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNEG D19, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D16, D16, D19, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL D19, D17, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D17, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D19, D18, D6, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D19, D19, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D17, D17, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D19, D17, D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDR D16, [X22, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D17, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D18, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D3, D19, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FSUB D17, D16, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D18, D18, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D3, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
FMUL D19, D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 419a60 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D4, D7, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FABS D19, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FDIV D4, D19, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D4, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNEG D7, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D4, D4, D7, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FABS D7, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D5, D7, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D5, D17, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMINNM D6, D7, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D5, D5, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D5, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D16, D5, D4, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
B 419a60 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source file and lines	advec_cell_kernel.f90:107-155
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 4.00 cycles (3.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 5 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

12: addition or subtraction (5 inside FMA instructions)
14: multiply (5 inside FMA instructions)
3: divide

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 9.67 FP operations per loaded or stored byte.

General properties

nb instructions	100
nb uops	100
loop length	400
used w registers	11
used x registers	24
used b registers	0
used h registers	0
used s registers	5
used d registers	12
used q registers	0
used v registers	0
used z registers	0
nb stack references	5
ADD-SUB / MUL ratio	0.78

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	7.75	7.75	7.75	7.75	11.50	11.50	11.50	11.50	6.00	6.00	6.00	0.00	0.00
cycles	3.50	3.50	7.75	7.75	7.75	7.75	11.50	11.50	11.50	11.50	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	12.50
Dispatch	11.50
DIV/SQRT	5.25-10.49
Overall L1	12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 419abc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDP X18, X12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X27, X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, W2,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
SUB X12, X13, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X16, X7, X16, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDUR W12, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X4, X18, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X5, X25, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X19, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W16, W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X16, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL X18, X16, X7	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X7, X21, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X26, X16, X18	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 419a7c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xf9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D3, D16, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
SUB X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR D3, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.LE 4199ec <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xf0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D3, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 419aa0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xfc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W30, W1, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W18, W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W23, W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X16, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 419abc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xfdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X18, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FABS D5, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SBFM X23, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X18, X18, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X23, X23, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X7, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D6, [X12, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X23, X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X18, X26, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X18, W30,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X16, X18, W16,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR D7, [X20, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D17, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D18, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FDIV D16, D5, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D5, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D17, D7, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D18, D18, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D19, D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D5, D16, D5, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D5, D5, D6	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D6, D0, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
B.LE 419b54 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x1074>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FSUB D16, D1, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FABS D17, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D18, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNEG D19, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D16, D16, D19, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL D19, D17, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D17, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D19, D18, D6, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D19, D19, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D17, D17, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D19, D17, D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDR D16, [X22, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D17, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D18, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D3, D19, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FSUB D17, D16, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D18, D18, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D3, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
FMUL D19, D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 419a60 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D4, D7, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FABS D19, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FDIV D4, D19, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D4, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNEG D7, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D4, D4, D7, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FABS D7, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D5, D7, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D5, D17, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMINNM D6, D7, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D5, D5, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D5, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D16, D5, D4, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
B 419a60 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code