OV - exec - Loop 71

	Loop Id: 71	Module: exec	Source: advec_cell_kernel.f90:199-246 [...]	Coverage: 3.66%

  (70) 0x419300 LDR	W8, [SP, #92]

  (70) 0x419304 LDR	W9, [SP, #152]

  (70) 0x419308 ADD	W3, W3, #1

  (70) 0x41930c CMP	W9, W8

  (70) 0x419310 ADD	W8, W9, #1

  (70) 0x419314 LDR	W9, [SP, #112]

  (70) 0x419318 STR	W8, [SP, #152]

  (70) 0x41931c ADD	W9, W9, #1

  (70) 0x419320 STR	W9, [SP, #112]

  (70) 0x419324 B.EQ	41951c

  (70) 0x419328 LDR	X8, [SP, #96]

  (70) 0x41932c TBNZ	X8, #63, 419300

0x419330 LDR	X9, [SP, #64]

0x419334 LDR	W8, [SP, #112]

0x419338 LDR	X10, [SP, #136]

0x41933c ORR	X4, XZR, XZR

0x419340 ADD	X8, X9, W8,SXTW

0x419344 LDP	X13, X11, [SP, #40]

0x419348 MADD	X5, X10, X8, X11

0x41934c ADD	X8, X9, W3,SXTW

0x419350 LDR	X9, [SP, #56]

0x419354 MADD	X6, X9, X8, X13

0x419358 MADD	X8, X10, X8, X11

0x41935c LDR	W9, [SP, #152]

0x419360 LDR	X11, [SP, #128]

0x419364 ADD	X7, X28, X8,LSL #3

0x419368 ADD	X25, X27, X8,LSL #3

0x41936c LDR	W8, [SP, #76]

0x419370 ADD	W8, W8, W9

0x419374 SBFM	X9, X8, #0, #31

0x419378 ADD	W30, W8, #1

0x41937c SUB	W19, W8, #2

0x419380 SUB	X9, X9, X14

0x419384 MUL	X26, X9, X10

0x419388 SUB	W10, W8, #1

0x41938c LDUR	X8, [X29, #368]

0x419390 MUL	X23, X9, X11

0x419394 LDR	D3, [X8, X9,LSL #3]

0x419398 SBFM	X8, X10, #0, #31

0x41939c LDR	X9, [SP, #80]

0x4193a0 SUB	X16, X8, X14

0x4193a4 LDR	X8, [SP, #96]

0x4193a8 MUL	X13, X16, X11

0x4193ac ADD	X17, X8, #2

0x4193b0 B	4193dc

0x4193c0 FMUL	D4, D17, D4

0x4193c4 SUB	X17, X17, #1

0x4193c8 ADD	X9, X9, #1

0x4193cc CMP	X17, #1

0x4193d0 STR	D4, [X6, X4,LSL #3]

0x4193d4 ADD	X4, X4, #1

0x4193d8 B.LE	419300

0x4193dc LDR	D4, [X25, X4,LSL #3]

0x4193e0 SUB	X8, X9, X24

0x4193e4 ADD	X10, X8, X26

0x4193e8 FCMP	D4, #0

0x4193ec B.LE	419404

0x4193f0 ADD	X8, X5, X4

0x4193f4 ORR	X15, XZR, X16

0x4193f8 ORR	X12, XZR, X13

0x4193fc ORR	W11, WZR, W19

0x419400 B	41942c

0x419404 LDR	X8, [SP, #144]

0x419408 ORR	X12, XZR, X23

0x41940c LDR	W8, [X8]

0x419410 ADD	W8, W8, #2

0x419414 CMP	W30, W8

0x419418 CSEL	W11, W30, W8, #11

0x41941c SBFM	X8, X11, #0, #31

0x419420 SUB	X15, X8, X14

0x419424 ORR	X8, XZR, X10

0x419428 ADD	X10, X5, X4

0x41942c ADD	X12, X18, X12,LSL #3

0x419430 FABS	D5, D4

0x419434 SBFM	X11, X11, #0, #31

0x419438 LDR	D16, [X20, X8,LSL #3]

0x41943c LDR	D19, [X20, X10,LSL #3]

0x419440 LDR	D7, [X12, X4,LSL #3]

0x419444 LDUR	X12, [X29, #368]

0x419448 FSUB	D19, D19, S16

0x41944c FDIV	D17, D5, D7

0x419450 LDR	D5, [X12, X15,LSL #3]

0x419454 SUB	X15, X11, X14

0x419458 MADD	X11, X0, X15, X2

0x41945c LDR	D18, [X11, X4,LSL #3]

0x419460 FSUB	D18, D16, S18

0x419464 FMUL	D20, D19, D18

0x419468 FCMP	D20, #0

0x41946c FMOV	D20, D16

0x419470 FMADD	D6, D17, D3, D3

0x419474 FDIV	D5, D6, D5

0x419478 FSUB	D6, D0, S17

0x41947c B.LE	4194b0

0x419480 FSUB	D17, D1, S17

0x419484 FCMP	D19, #0

0x419488 FABS	D18, D18

0x41948c FABS	D19, D19

0x419490 FNEG	D20, D17

0x419494 FCSEL	D17, D17, D20, #12

0x419498 FMUL	D20, D18, D5

0x41949c FMINNM	D18, D18, D19

0x4194a0 FMADD	D20, D19, D6, D20

0x4194a4 FMUL	D20, D20, D2

0x4194a8 FMINNM	D18, D18, D20

0x4194ac FMADD	D20, D18, D17, D16

0x4194b0 LDR	D17, [X22, X8,LSL #3]

0x4194b4 MADD	X8, X0, X15, X1

0x4194b8 LDR	D19, [X22, X10,LSL #3]

0x4194bc FMUL	D4, D20, D4

0x4194c0 LDR	D18, [X8, X4,LSL #3]

0x4194c4 STR	D4, [X7, X4,LSL #3]

0x4194c8 FSUB	D19, D19, S17

0x4194cc FSUB	D18, D17, S18

0x4194d0 FMUL	D20, D19, D18

0x4194d4 FCMP	D20, #0

0x4194d8 B.LE	4193c0

0x4194dc FMUL	D7, D16, D7

0x4194e0 FABS	D20, D4

0x4194e4 FCMP	D19, #0

0x4194e8 FDIV	D7, D20, D7

0x4194ec FSUB	D7, D1, S7

0x4194f0 FNEG	D16, D7

0x4194f4 FCSEL	D7, D7, D16, #12

0x4194f8 FABS	D16, D18

0x4194fc FABS	D18, D19

0x419500 FMUL	D5, D16, D5

0x419504 FMADD	D5, D18, D6, D5

0x419508 FMINNM	D6, D16, D18

0x41950c FMUL	D5, D5, D2

0x419510 FMINNM	D5, D6, D5

0x419514 FMADD	D17, D5, D7, D17

0x419518 B	4193c0

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 199 - 246

--------------------------------------------------------------------------------

199:       !$OMP DO PRIVATE(upwind,donor,downwind,dif,sigmat,sigma3,sigma4,sigmav,sigma,sigmam, &

200:       !$OMP            diffuw,diffdw,limiter,wind)

201:       DO k=y_min,y_max+2

202:         DO j=x_min,x_max

203:

204:           IF(vol_flux_y(j,k).GT.0.0)THEN

[...]

210:             upwind   =MIN(k+1,y_max+2)

[...]

216:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

217:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

218:           sigma4=2.0_8-sigmat

219:

220:           sigma=sigmat

221:           sigmav=sigmat

222:

223:           diffuw=density1(j,donor)-density1(j,upwind)

224:           diffdw=density1(j,downwind)-density1(j,donor)

225:           wind=1.0_8

226:           IF(diffdw.LE.0.0) wind=-1.0_8

227:           IF(diffuw*diffdw.GT.0.0)THEN

228:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

229:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

230:           ELSE

231:             limiter=0.0

232:           ENDIF

233:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

234:

235:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

236:           diffuw=energy1(j,donor)-energy1(j,upwind)

237:           diffdw=energy1(j,downwind)-energy1(j,donor)

238:           wind=1.0_8

239:           IF(diffdw.LE.0.0) wind=-1.0_8

240:           IF(diffuw*diffdw.GT.0.0)THEN

241:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

242:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

243:           ELSE

244:             limiter=0.0

245:           ENDIF

246:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

Coverage (%)	Name	Module
►98.43+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.75
CQA speedup if FP arith vectorized	1.95
CQA speedup if fully vectorized	5.22 - 2.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	micro-operation queue,
Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source	advec_cell_kernel.f90:199-199,advec_cell_kernel.f90:202-204,advec_cell_kernel.f90:210-210,advec_cell_kernel.f90:216-218,advec_cell_kernel.f90:223-224,advec_cell_kernel.f90:227-228,advec_cell_kernel.f90:233-237,advec_cell_kernel.f90:240-241,advec_cell_kernel.f90:246-246
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	7.69
CQA cycles if fully vectorized	2.88 - 5.24
Front-end cycles	15.00
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	10.75
P3 cycles	10.75
P4 cycles	10.75
P5 cycles	10.75
P6 cycles	11.50
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	11.50
P10 cycles	8.67
P11 cycles	8.67
P12 cycles	8.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	120.00
Nb uops	120.00
Nb loads	NA
Nb stores	2.00
Nb stack references	11.00
FLOP/cycle	1.93
Nb FLOP add-sub	7.00
Nb FLOP mul	9.00
Nb FLOP fma	5.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.80
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	24.43

Metric	Value
CQA speedup if no scalar integer	3.75
CQA speedup if FP arith vectorized	1.95
CQA speedup if fully vectorized	5.22 - 2.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	micro-operation queue,
Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source	advec_cell_kernel.f90:199-199,advec_cell_kernel.f90:202-204,advec_cell_kernel.f90:210-210,advec_cell_kernel.f90:216-218,advec_cell_kernel.f90:223-224,advec_cell_kernel.f90:227-228,advec_cell_kernel.f90:233-237,advec_cell_kernel.f90:240-241,advec_cell_kernel.f90:246-246
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	7.69
CQA cycles if fully vectorized	2.88 - 5.24
Front-end cycles	15.00
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	10.75
P3 cycles	10.75
P4 cycles	10.75
P5 cycles	10.75
P6 cycles	11.50
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	11.50
P10 cycles	8.67
P11 cycles	8.67
P12 cycles	8.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	120.00
Nb uops	120.00
Nb loads	NA
Nb stores	2.00
Nb stack references	11.00
FLOP/cycle	1.93
Nb FLOP add-sub	7.00
Nb FLOP mul	9.00
Nb FLOP fma	5.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.80
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	24.43

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source file and lines	advec_cell_kernel.f90:199-246
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:199-204,210,216-246.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:199,202-204,210,216-218,223-224,227-228,233-237,240-241,246.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 4.00 cycles (3.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 15.00 to 5.24 cycles (2.86x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 5 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

12: addition or subtraction (5 inside FMA instructions)
14: multiply (5 inside FMA instructions)
3: divide

The binary loop is loading 12 bytes.

Arithmetic intensity

Arithmetic intensity is 2.42 FP operations per loaded or stored byte.

General properties

nb instructions	120
nb uops	120
loop length	480
used w registers	8
used x registers	28
used b registers	0
used h registers	0
used s registers	5
used d registers	13
used q registers	0
used v registers	0
used z registers	0
nb stack references	11
ADD-SUB / MUL ratio	0.78

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	10.75	10.75	10.75	10.75	11.50	11.50	11.50	11.50	8.67	8.67	8.67	0.00	0.00
cycles	3.50	3.50	10.75	10.75	10.75	10.75	11.50	11.50	11.50	11.50	8.67	8.67	8.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	15.00
Dispatch	11.50
DIV/SQRT	5.25-10.49
Overall L1	15.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	23%
load	25%
store	25%
mul	25%
add-sub	20%
fma	25%
other	18%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	24%
load	25%
store	25%
mul	25%
add-sub	22%
fma	25%
div/sqrt	25%
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

0% of peak load performance is reached (0.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 11.50 cycles (1.30x speedup).

ASM code

In the binary file, the address of the loop is: 4193c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR W8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORR X4, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X9, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDP X13, X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
MADD X5, X10, X8, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X8, X9, W3,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MADD X6, X9, X8, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X8, X10, X8, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR W9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X11, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X7, X28, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X27, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X9, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W19, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X9, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL X26, X9, X10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SUB W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X23, X9, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR D3, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SBFM X8, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SUB X16, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X13, X16, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X17, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4193dc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x8fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D4, D17, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
SUB X17, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR D4, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.LE 419300 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x820>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X25, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SUB X8, X9, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FCMP D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 419404 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x924>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X15, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X12, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 41942c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x94c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORR X12, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W30, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W11, W30, W8, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X8, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X15, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X18, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FABS D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SBFM X11, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X20, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D7, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDUR X12, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FSUB D19, D19, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FDIV D17, D5, D7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D5, [X12, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SUB X15, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X11, X0, X15, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D18, [X11, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D18, D16, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D20, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV D20, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D6, D17, D3, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D5, D6, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D6, D0, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
B.LE 4194b0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x9d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FSUB D17, D1, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FABS D18, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNEG D20, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D17, D17, D20, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL D20, D18, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D18, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D20, D19, D6, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D20, D20, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D18, D18, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D20, D18, D17, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDR D17, [X22, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MADD X8, X0, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D19, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D4, D20, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D18, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D4, [X7, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
FSUB D19, D19, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D18, D17, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D20, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 4193c0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x8e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D7, D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FABS D20, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FDIV D7, D20, D7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D7, D1, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D7, D7, D16, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FABS D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D5, D16, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D5, D18, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMINNM D6, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D5, D5, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D5, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D17, D5, D7, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
B 4193c0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x8e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par
Source file and lines	advec_cell_kernel.f90:199-246
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 4.00 cycles (3.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 5 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

12: addition or subtraction (5 inside FMA instructions)
14: multiply (5 inside FMA instructions)
3: divide

The binary loop is loading 12 bytes.

Arithmetic intensity

Arithmetic intensity is 2.42 FP operations per loaded or stored byte.

General properties

nb instructions	120
nb uops	120
loop length	480
used w registers	8
used x registers	28
used b registers	0
used h registers	0
used s registers	5
used d registers	13
used q registers	0
used v registers	0
used z registers	0
nb stack references	11
ADD-SUB / MUL ratio	0.78

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	10.75	10.75	10.75	10.75	11.50	11.50	11.50	11.50	8.67	8.67	8.67	0.00	0.00
cycles	3.50	3.50	10.75	10.75	10.75	10.75	11.50	11.50	11.50	11.50	8.67	8.67	8.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	15.00
Dispatch	11.50
DIV/SQRT	5.25-10.49
Overall L1	15.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	23%
load	25%
store	25%
mul	25%
add-sub	20%
fma	25%
other	18%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	24%
load	25%
store	25%
mul	25%
add-sub	22%
fma	25%
div/sqrt	25%
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

0% of peak load performance is reached (0.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4193c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR W8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORR X4, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X9, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDP X13, X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
MADD X5, X10, X8, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X8, X9, W3,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MADD X6, X9, X8, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X8, X10, X8, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR W9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X11, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X7, X28, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X27, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X9, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD W30, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W19, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X9, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL X26, X9, X10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SUB W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X23, X9, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR D3, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SBFM X8, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SUB X16, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MUL X13, X16, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X17, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4193dc <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x8fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D4, D17, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
SUB X17, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR D4, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B.LE 419300 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x820>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X25, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SUB X8, X9, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FCMP D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 419404 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x924>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X15, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X12, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR W11, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 41942c <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x94c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ORR X12, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W30, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W11, W30, W8, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X8, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X15, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X18, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FABS D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SBFM X11, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X20, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D7, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDUR X12, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FSUB D19, D19, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FDIV D17, D5, D7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR D5, [X12, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
SUB X15, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X11, X0, X15, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D18, [X11, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FSUB D18, D16, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D20, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV D20, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D6, D17, D3, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D5, D6, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D6, D0, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
B.LE 4194b0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x9d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FSUB D17, D1, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FABS D18, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNEG D20, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D17, D17, D20, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL D20, D18, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D18, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D20, D19, D6, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMUL D20, D20, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D18, D18, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D20, D18, D17, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDR D17, [X22, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MADD X8, X0, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D19, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D4, D20, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR D18, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D4, [X7, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
FSUB D19, D19, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FSUB D18, D17, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D20, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FCMP D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 4193c0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x8e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D7, D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FABS D20, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCMP D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
FDIV D7, D20, D7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FSUB D7, D1, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FCSEL D7, D7, D16, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FABS D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FABS D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D5, D16, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D5, D18, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMINNM D6, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D5, D5, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMINNM D5, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMADD D17, D5, D7, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
B 4193c0 <_QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par+0x8e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code