OV - exec - Function __viscosity_kernel_module_MOD_viscosity_kernel._omp

	Function: __viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0	Module: exec	Source: viscosity_kernel.f90:50-89	Coverage (incl. loops): 2.49% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 50 - 89

--------------------------------------------------------------------------------

50:     !$OMP PARALLEL

51:

52:     !$OMP DO PRIVATE(ugrad,vgrad,div,strain2,pgradx,pgrady,pgradx2,pgrady2,limiter,pgrad,xgrad,ygrad,grad,grad2,dirx,diry)

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

0x444620 STP	X29, X30, [SP, #880]!

0x444624 ADD	X29, SP, #0

0x444628 STP	X19, X20, [SP, #16]

0x44462c ORR	X20, XZR, X0

0x444630 STP	X21, X22, [SP, #32]

0x444634 LDR	X0, [X0, #16]

0x444638 LDR	W21, [X0]

0x44463c BL	410110

0x444640 ORR	W19, WZR, W0

0x444644 BL	410130

0x444648 LDR	X1, [X20, #24]

0x44464c ORR	W2, WZR, W0

0x444650 LDR	W3, [X1]

0x444654 ADD	W4, W3, #1

0x444658 SUB	W5, W4, W21

0x44465c SDIV	W6, W5, W19

0x444660 MSUB	W7, W6, W19, W5

0x444664 CMP	W0, W7

0x444668 B.LT	4449e8

0x44466c MADD	W8, W6, W2, W7

0x444670 ADD	W9, W6, W8

0x444674 CMP	W8, W9

0x444678 B.GE	4449d8

0x44467c STP	X23, X24, [SP, #48]

0x444680 ADD	W2, W21, W8

0x444684 ADD	W17, W21, W9

0x444688 SBFM	X1, X2, #0, #31

0x44468c MOVZ	W13, #0

0x444690 PTRUE	P7.B, ALL

0x444694 CNTD	X19, ALL

0x444698 FDUP	Z31.D, #112

0x44469c STP	X25, X26, [SP, #64]

0x4446a0 ADRP	X26,

0x4446a4 ADD	X26, X26, #2160

0x4446a8 STP	X27, X28, [SP, #80]

0x4446ac LDP	X28, X14, [X20]

0x4446b0 LDP	X30, X6, [X20, #144]

0x4446b4 LDP	X12, X11, [X20, #104]

0x4446b8 MADD	X9, X1, X6, X6

0x4446bc UBFM	X22, X6, #61, #60

0x4446c0 LDP	X18, X15, [X20, #88]

0x4446c4 UBFM	X23, X12, #61, #60

0x4446c8 STR	W17, [SP, #116]

0x4446cc LDR	X24, [X20, #120]

0x4446d0 LDR	W28, [X28]

0x4446d4 LDR	X3, [X20, #176]

0x4446d8 UBFM	X25, X24, #61, #60

0x4446dc LDR	W14, [X14]

0x4446e0 ORR	X0, XZR, X25

0x4446e4 SUB	X25, X25, #8

0x4446e8 LDR	X8, [X20, #168]

0x4446ec STR	X0, [SP, #120]

0x4446f0 SBFM	X0, X28, #0, #31

0x4446f4 LDR	X16, [X20, #40]

0x4446f8 ADD	X17, X0, X3

0x4446fc ADD	X4, X0, X30

0x444700 ADD	X5, X0, X11

0x444704 MADD	X7, X1, X6, X0

0x444708 CMP	W28, W14

0x44470c LDR	X27, [X20, #56]

0x444710 MADD	X6, X1, X24, X0

0x444714 ADD	X18, X0, X18

0x444718 STP	W14, W28, [SP, #108]

0x44471c MADD	X10, X1, X8, X8

0x444720 UBFM	X21, X8, #61, #60

0x444724 LDP	X3, X30, [X20, #128]

0x444728 MADD	X11, X1, X12, X5

0x44472c ADD	W5, W14, #1

0x444730 MADD	X8, X1, X8, X17

0x444734 CSINC	W14, W28, W14, #12

0x444738 ADD	X9, X9, X0

0x44473c ADD	X10, X10, X17

0x444740 STR	W5, [SP, #140]

0x444744 SUB	W5, W5, W28

0x444748 WHILELO	P15.D, XZR, X5

0x44474c LDR	X12, [X20, #32]

0x444750 UBFM	X17, X30, #61, #60

0x444754 MADD	X4, X1, X30, X4

0x444758 ADD	X0, X0, X3

0x44475c ORR	X28, XZR, X17

0x444760 LDR	X17, [X20, #160]

0x444764 ADD	X1, X1, X15

0x444768 ADD	X3, X3, #1

0x44476c STR	W14, [SP, #104]

0x444770 LDR	X15, [X20, #72]

0x444774 ADD	X6, X6, X3

0x444778 ADD	X3, X16, X1,LSL #3

0x44477c ADD	X12, X12, X18,LSL #3

0x444780 LDR	X16, [X20, #48]

0x444784 ADD	X6, X27, X6,LSL #3

0x444788 ADD	X14, X17, #1

0x44478c ORR	X18, XZR, X12

0x444790 LDR	X1, [X20, #64]

0x444794 ADD	X30, X12, #8

0x444798 ADD	X9, X9, X14

0x44479c ADD	X7, X7, X14

0x4447a0 ADD	X9, X15, X9,LSL #3

0x4447a4 LDR	X12, [X20, #80]

0x4447a8 ADD	X7, X15, X7,LSL #3

0x4447ac ADD	X11, X16, X11,LSL #3

0x4447b0 ADD	X4, X1, X4,LSL #3

0x4447b4 ADD	X10, X12, X10,LSL #3

0x4447b8 ADD	X8, X12, X8,LSL #3

0x4447bc LDR	W12, [SP, #136]

0x4447c0 STR	X20, [SP, #128]

(740) 0x4447c4 LDP	W15, W17, [SP, #108]

(740) 0x4447c8 ADD	W20, W2, #1

(740) 0x4447cc CMP	W17, W15

(740) 0x4447d0 B.GT	4449f4

(740) 0x4447d4 SUB	W12, W2, #1

(740) 0x4447d8 MOVZ	X1, #0

(740) 0x4447dc ORR	P6.B, P15/Z, P15.B, P15.B

(740) 0x4447e0 SBFM	X2, X12, #0, #31

(740) 0x4447e4 SUB	X17, X7, #8

(740) 0x4447e8 LD1RD	{Z30.D}, P7/Z, [X26]

(740) 0x4447ec SUB	X16, X9, #8

(740) 0x4447f0 ADD	X15, X10, #8

(740) 0x4447f4 MADD	X2, X2, X24, X0

(740) 0x4447f8 ADD	X14, X8, #8

(740) 0x4447fc SUB	X13, X6, #16

(740) 0x444800 ADD	X12, X25, X6

(740) 0x444804 ADD	X2, X27, X2,LSL #3

  (742) 0x444808 LD1D	{Z24.D}, P6/Z, [X10, X1,LSL #3]

  (742) 0x44480c LD1D	{Z5.D}, P6/Z, [X15, X1,LSL #3]

  (742) 0x444810 LD1D	{Z3.D}, P6/Z, [X14, X1,LSL #3]

  (742) 0x444814 LD1D	{Z29.D}, P6/Z, [X7, X1,LSL #3]

  (742) 0x444818 LD1D	{Z28.D}, P6/Z, [X9, X1,LSL #3]

  (742) 0x44481c LD1D	{Z4.D}, P6/Z, [X16, X1,LSL #3]

  (742) 0x444820 LD1D	{Z2.D}, P6/Z, [X17, X1,LSL #3]

  (742) 0x444824 LD1D	{Z21.D}, P6/Z, [X8, X1,LSL #3]

  (742) 0x444828 FADD	Z22.D, Z5.D, Z24.D

  (742) 0x44482c FADD	Z7.D, Z3.D, Z5.D

  (742) 0x444830 FADD	Z6.D, Z28.D, Z29.D

  (742) 0x444834 FADD	Z0.D, Z4.D, Z28.D

  (742) 0x444838 FADD	Z16.D, Z4.D, Z2.D

  (742) 0x44483c FADD	Z17.D, Z2.D, Z29.D

  (742) 0x444840 FADD	Z23.D, Z21.D, Z24.D

  (742) 0x444844 FSUB	Z18.D, Z0.D, Z17.D

  (742) 0x444848 LD1D	{Z28.D}, P6/Z, [X18, X1,LSL #3]

  (742) 0x44484c LD1RD	{Z29.D}, P7/Z, [X3]

  (742) 0x444850 LD1D	{Z5.D}, P6/Z, [X2, X1,LSL #3]

  (742) 0x444854 LD1D	{Z1.D}, P6/Z, [X6, X1,LSL #3]

  (742) 0x444858 FSUB	Z20.D, Z6.D, Z16.D

  (742) 0x44485c FADD	Z19.D, Z3.D, Z21.D

  (742) 0x444860 FSUB	Z26.D, Z7.D, Z23.D

  (742) 0x444864 FSUB	Z25.D, Z22.D, Z19.D

  (742) 0x444868 LD1D	{Z3.D}, P6/Z, [X12, X1,LSL #3]

  (742) 0x44486c LD1D	{Z7.D}, P6/Z, [X30, X1,LSL #3]

  (742) 0x444870 LD1D	{Z2.D}, P6/Z, [X13, X1,LSL #3]

  (742) 0x444874 FMUL	Z16.D, Z29.D, Z25.D

  (742) 0x444878 LD1RD	{Z24.D}, P7/Z, [X3, #1]

  (742) 0x44487c FMLA	Z16.D, P7/M, Z28.D, Z20.D

  (742) 0x444880 FADD	Z22.D, Z24.D, Z29.D

  (742) 0x444884 FSUB	Z6.D, Z3.D, Z5.D

  (742) 0x444888 FCMGE	P5.D, P7/Z, Z16.D, #0.0000000

  (742) 0x44488c FDIVR	Z22.D, P7/M, Z22.D, Z6.D

  (742) 0x444890 MOVPRFX	Z27, Z31

  (742) 0x444894 FDIV	Z27.D, P7/M, Z27.D, Z28.D

  (742) 0x444898 MOVPRFX	Z4, Z31

  (742) 0x44489c FDIV	Z4.D, P7/M, Z4.D, Z29.D

  (742) 0x4448a0 FMUL	Z27.D, P7/M, Z27.D, #0.0000000

  (742) 0x4448a4 FMUL	Z4.D, P7/M, Z4.D, #0.0000000

  (742) 0x4448a8 FMUL	Z0.D, Z26.D, Z27.D

  (742) 0x4448ac FADD	Z17.D, Z7.D, Z28.D

  (742) 0x4448b0 FMLA	Z0.D, P7/M, Z4.D, Z18.D

  (742) 0x4448b4 FSUB	Z1.D, Z1.D, Z2.D

  (742) 0x4448b8 FMUL	Z18.D, Z22.D, Z22.D

  (742) 0x4448bc FDIVR	Z17.D, P7/M, Z17.D, Z1.D

  (742) 0x4448c0 FMUL	Z23.D, Z22.D, Z17.D

  (742) 0x4448c4 FABS	Z22.D, P7/M, Z22.D

  (742) 0x4448c8 FMAXNM	Z22.D, P7/M, Z22.D, Z30.D

  (742) 0x4448cc FMUL	Z21.D, Z18.D, Z25.D

  (742) 0x4448d0 FCMLT	P3.D, P7/Z, Z17.D, #0.0000000

  (742) 0x4448d4 FMUL	Z19.D, Z21.D, Z4.D

  (742) 0x4448d8 FMUL	Z25.D, Z17.D, Z17.D

  (742) 0x4448dc FCMGE	P4.D, P7/Z, Z17.D, #0.0000000

  (742) 0x4448e0 FMUL	Z20.D, Z25.D, Z20.D

  (742) 0x4448e4 FADD	Z26.D, Z18.D, Z25.D

  (742) 0x4448e8 FMLA	Z19.D, P7/M, Z20.D, Z27.D

  (742) 0x4448ec FMAXNM	Z26.D, P7/M, Z26.D, Z30.D

  (742) 0x4448f0 FMAD	Z23.D, P7/M, Z0.D, Z19.D

  (742) 0x4448f4 MOVPRFX	Z27, Z17

  (742) 0x4448f8 FABS	Z27.D, P7/M, Z17.D

  (742) 0x4448fc FDIVR	Z26.D, P7/M, Z26.D, Z23.D

  (742) 0x444900 FMAXNM	Z27.D, P7/M, Z27.D, Z30.D

  (742) 0x444904 FCMGT	P14.D, P7/Z, Z26.D, #0.0000000

  (742) 0x444908 FCMGT	P1.D, P3/Z, Z27.D, #0.0000000

  (742) 0x44490c NOR	P0.B, P7/Z, P5.B, P14.B

  (742) 0x444910 AND	P2.B, P4/Z, P0.B, P6.B

  (742) 0x444914 AND	P8.B, P1/Z, P0.B, P6.B

  (742) 0x444918 EOR	P5.B, P7/Z, P2.B, P7.B

  (742) 0x44491c AND	P0.B, P0/Z, P6.B, P6.B

  (742) 0x444920 FNEG	Z27.D, P5/M, Z27.D

  (742) 0x444924 LD1D	{Z0.D}, P0/Z, [X11, X1,LSL #3]

  (742) 0x444928 MOVPRFX	Z4, Z31

  (742) 0x44492c FCPY	Z4.D, P8/M, #-1.0000000

  (742) 0x444930 FADD	Z3.D, Z0.D, Z0.D

  (742) 0x444934 FMUL	Z16.D, Z22.D, Z4.D

  (742) 0x444938 FMUL	Z24.D, Z16.D, Z16.D

  (742) 0x44493c FMLA	Z24.D, P7/M, Z27.D, Z27.D

  (742) 0x444940 FSQRT	Z24.D, P7/M, Z24.D

  (742) 0x444944 FMUL	Z29.D, Z24.D, Z29.D

  (742) 0x444948 FMUL	Z28.D, Z24.D, Z28.D

  (742) 0x44494c FDIV	Z29.D, P7/M, Z29.D, Z16.D

  (742) 0x444950 FDIV	Z28.D, P7/M, Z28.D, Z27.D

  (742) 0x444954 FABS	Z29.D, P7/M, Z29.D

  (742) 0x444958 FABS	Z28.D, P7/M, Z28.D

  (742) 0x44495c FMINNM	Z28.D, P7/M, Z28.D, Z29.D

  (742) 0x444960 FMUL	Z22.D, Z28.D, Z26.D

  (742) 0x444964 FMUL	Z5.D, Z22.D, Z22.D

  (742) 0x444968 MOVPRFX	Z5.D, P0/Z, Z5.D

  (742) 0x44496c FMUL	Z5.D, P0/M, Z5.D, Z3.D

  (742) 0x444970 ST1D	{Z5.D}, P6, [X4, X1,LSL #3]

  (742) 0x444974 ADD	X1, X1, X19

  (742) 0x444978 WHILELO	P6.D, X1, X5

  (742) 0x44497c B.NE	444808

(740) 0x444980 LDR	X17, [SP, #120]

(740) 0x444984 ADD	X7, X7, X22

(740) 0x444988 ADD	X9, X9, X22

(740) 0x44498c ADD	X10, X10, X21

(740) 0x444990 ADD	X8, X8, X21

(740) 0x444994 LDR	W16, [SP, #116]

(740) 0x444998 ADD	X11, X11, X23

(740) 0x44499c ADD	X4, X4, X28

(740) 0x4449a0 ADD	X3, X3, #8

(740) 0x4449a4 MOVZ	W13, #1

(740) 0x4449a8 ADD	X6, X6, X17

(740) 0x4449ac CMP	W16, W20

(740) 0x4449b0 B.LE	4449c0

(740) 0x4449b4 LDR	W12, [SP, #104]

(740) 0x4449b8 ORR	W2, WZR, W20

(740) 0x4449bc B	4447c4

0x4449c0 LDR	X5, [SP, #128]

0x4449c4 LDR	W0, [SP, #104]

0x4449c8 STR	W0, [X5, #184]

0x4449cc LDP	X23, X24, [SP, #48]

0x4449d0 LDP	X25, X26, [SP, #64]

0x4449d4 LDP	X27, X28, [SP, #80]

0x4449d8 LDP	X19, X20, [SP, #16]

0x4449dc LDP	X21, X22, [SP, #32]

0x4449e0 LDP	X29, X30, [SP], #144

0x4449e4 RET

0x4449e8 ADD	W6, W6, #1

0x4449ec MOVZ	W7, #0

0x4449f0 B	44466c

(740) 0x4449f4 LDR	W2, [SP, #116]

(740) 0x4449f8 SUB	W14, W2, W20

(740) 0x4449fc ANDS	W16, W14, #0x3

(740) 0x444a00 B.EQ	444b74

(740) 0x444a04 LDR	W1, [SP, #104]

(740) 0x444a08 LDR	W15, [SP, #140]

(740) 0x444a0c CMP	W15, W1

(740) 0x444a10 B.EQ	444980

(740) 0x444a14 LDR	X2, [SP, #120]

(740) 0x444a18 ADD	X7, X7, X22

(740) 0x444a1c ADD	X9, X9, X22

(740) 0x444a20 ADD	X10, X10, X21

(740) 0x444a24 ADD	X8, X8, X21

(740) 0x444a28 LDR	W17, [SP, #116]

(740) 0x444a2c ADD	X11, X11, X23

(740) 0x444a30 ADD	X4, X4, X28

(740) 0x444a34 ADD	X3, X3, #8

(740) 0x444a38 ADD	X6, X6, X2

(740) 0x444a3c CMP	W17, W20

(740) 0x444a40 B.LE	444b2c

(740) 0x444a44 ADD	W20, W20, #1

(740) 0x444a48 CMP	W16, #1

(740) 0x444a4c B.EQ	444b60

(740) 0x444a50 CMP	W16, #2

(740) 0x444a54 B.EQ	444a7c

(740) 0x444a58 ADD	X7, X7, X22

(740) 0x444a5c ADD	X9, X9, X22

(740) 0x444a60 ADD	X10, X10, X21

(740) 0x444a64 ADD	X8, X8, X21

(740) 0x444a68 ADD	X6, X6, X2

(740) 0x444a6c ADD	X11, X11, X23

(740) 0x444a70 ADD	X4, X4, X28

(740) 0x444a74 ADD	X3, X3, #8

(740) 0x444a78 ADD	W20, W20, #1

(740) 0x444a7c LDR	W16, [SP, #104]

(740) 0x444a80 LDR	W14, [SP, #140]

(740) 0x444a84 CMP	W14, W16

(740) 0x444a88 B.EQ	444980

(740) 0x444a8c LDR	X1, [SP, #120]

(740) 0x444a90 ADD	X7, X7, X22

(740) 0x444a94 ADD	X9, X9, X22

(740) 0x444a98 ADD	X10, X10, X21

(740) 0x444a9c ADD	X8, X8, X21

(740) 0x444aa0 LDR	W15, [SP, #116]

(740) 0x444aa4 ADD	X11, X11, X23

(740) 0x444aa8 ADD	X4, X4, X28

(740) 0x444aac ADD	X3, X3, #8

(740) 0x444ab0 ADD	W20, W20, #1

(740) 0x444ab4 ADD	X6, X6, X1

(740) 0x444ab8 B	444aec

  (741) 0x444abc ADD	X6, X6, X1,LSL #1

  (741) 0x444ac0 ADD	X10, X17, X21

  (741) 0x444ac4 ADD	X7, X7, X22

  (741) 0x444ac8 ADD	X11, X11, X23,LSL #1

  (741) 0x444acc ADD	X9, X9, X22

  (741) 0x444ad0 ADD	X8, X2, X21

  (741) 0x444ad4 ADD	X17, X4, X28,LSL #1

  (741) 0x444ad8 ADD	X6, X6, X1

  (741) 0x444adc ADD	X3, X3, #24

  (741) 0x444ae0 ADD	X11, X11, X23

  (741) 0x444ae4 ADD	W20, W20, #4

  (741) 0x444ae8 ADD	X4, X17, X28

  (741) 0x444aec CMP	W14, W16

  (741) 0x444af0 B.EQ	444980

  (741) 0x444af4 ADD	X17, X7, X22

  (741) 0x444af8 ADD	X2, X9, X22

  (741) 0x444afc ADD	X10, X10, X21

  (741) 0x444b00 ADD	X8, X8, X21

  (741) 0x444b04 ADD	X7, X17, X22,LSL #1

  (741) 0x444b08 ADD	X9, X2, X22,LSL #1

  (741) 0x444b0c ADD	X6, X6, X1

  (741) 0x444b10 ADD	X11, X11, X23

  (741) 0x444b14 ADD	X17, X10, X21,LSL #1

  (741) 0x444b18 ADD	X4, X4, X28

  (741) 0x444b1c ADD	X3, X3, #8

  (741) 0x444b20 ADD	X2, X8, X21,LSL #1

  (741) 0x444b24 CMP	W15, W20

  (741) 0x444b28 B.GT	444abc

0x444b2c STR	W12, [SP, #136]

0x444b30 LDR	X5, [SP, #128]

0x444b34 CBNZ	W13, 444b54

0x444b38 LDP	X23, X24, [SP, #48]

0x444b3c LDP	X25, X26, [SP, #64]

0x444b40 LDP	X27, X28, [SP, #80]

0x444b44 LDP	X19, X20, [SP, #16]

0x444b48 LDP	X21, X22, [SP, #32]

0x444b4c LDP	X29, X30, [SP], #144

0x444b50 RET

0x444b54 LDR	W13, [SP, #136]

0x444b58 STR	W13, [SP, #104]

0x444b5c B	4449c4

(740) 0x444b60 LDR	W16, [SP, #104]

(740) 0x444b64 ORR	X1, XZR, X2

(740) 0x444b68 LDR	W15, [SP, #116]

(740) 0x444b6c LDR	W14, [SP, #140]

(740) 0x444b70 B	444aec

(740) 0x444b74 LDR	X1, [SP, #120]

(740) 0x444b78 LDR	W16, [SP, #104]

(740) 0x444b7c LDR	W15, [SP, #116]

(740) 0x444b80 LDR	W14, [SP, #140]

(740) 0x444b84 B	444aec

Coverage (%)	Name	Source Location	Module
►98.38+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.62+	GOMP_parallel		libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	viscosity_kernel.f90:50-89
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:50-89.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.17 to 12.50 cycles (1.45x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 18.17 to 12.50 cycles (1.45x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 21 bytes. The binary function is storing 18 bytes.

General properties

nb instructions	131
nb uops	131
loop length	524
used w registers	17
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	1
nb stack references	31

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.38 cycles
front end	16.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	17.50	17.50	17.50	17.50	0.50	0.50	0.00	0.00	18.17	17.83	18.00	7.50	7.50
cycles	4.50	4.50	17.50	17.50	17.50	17.50	0.50	0.50	0.00	0.00	18.17	17.83	18.00	7.50	7.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	16.38
Dispatch	18.17
DIV/SQRT	5.00-12.50
Overall L1	18.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	27%
load	34%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	21%
other	24%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	27%
load	34%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	21%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.17 cycles. At this rate:

1% of peak load performance is reached (1.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (0.99 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 444620

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 410110 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410130 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W3, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W4, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W5, W4, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W6, W5, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W7, W6, W19, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4449e8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W8, W6, W2, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W6, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4449d8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W2, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W17, W21, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X1, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
CNTD X19, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FDUP Z31.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X26, <4646a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X26, X26, #2160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X14, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X30, X6, [X20, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X11, [X20, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MADD X9, X1, X6, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X22, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X18, X15, [X20, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
UBFM X23, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W17, [SP, #116]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X24, [X20, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W28, [X28]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X20, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X25, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W14, [X14]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X25, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X20, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SBFM X0, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X20, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X17, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X0, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X7, X1, X6, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W28, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LDR X27, [X20, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X6, X1, X24, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP W14, W28, [SP, #108]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X10, X1, X8, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X21, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X3, X30, [X20, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MADD X11, X1, X12, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W5, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X8, X1, X8, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CSINC W14, W28, W14, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W5, [SP, #140]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB W5, W5, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P15.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LDR X12, [X20, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X17, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X4, X1, X30, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X0, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X20, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W14, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X15, [X20, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X16, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X12, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X20, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X27, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X18, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [X20, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X7, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X15, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [X20, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X7, X15, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X16, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X1, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X12, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X12, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W12, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X20, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W0, [SP, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W0, [X5, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #144	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 44466c <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W12, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ W13, 444b54 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #144	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W13, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W13, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 4449c4 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	viscosity_kernel.f90:50-89
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 21 bytes. The binary function is storing 18 bytes.

General properties

nb instructions	131
nb uops	131
loop length	524
used w registers	17
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	1
nb stack references	31

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.38 cycles
front end	16.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	17.50	17.50	17.50	17.50	0.50	0.50	0.00	0.00	18.17	17.83	18.00	7.50	7.50
cycles	4.50	4.50	17.50	17.50	17.50	17.50	0.50	0.50	0.00	0.00	18.17	17.83	18.00	7.50	7.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	16.38
Dispatch	18.17
DIV/SQRT	5.00-12.50
Overall L1	18.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	27%
load	34%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	21%
other	24%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	27%
load	34%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	21%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.17 cycles. At this rate:

1% of peak load performance is reached (1.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (0.99 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 444620

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 410110 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410130 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W3, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W4, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W5, W4, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W6, W5, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W7, W6, W19, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4449e8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W8, W6, W2, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W6, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4449d8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W2, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W17, W21, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X1, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
CNTD X19, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FDUP Z31.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X26, <4646a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X26, X26, #2160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X14, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X30, X6, [X20, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X11, [X20, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MADD X9, X1, X6, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X22, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X18, X15, [X20, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
UBFM X23, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W17, [SP, #116]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X24, [X20, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W28, [X28]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X20, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X25, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W14, [X14]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X25, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X20, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SBFM X0, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X20, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X17, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X0, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X7, X1, X6, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W28, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LDR X27, [X20, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X6, X1, X24, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X18, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP W14, W28, [SP, #108]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MADD X10, X1, X8, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X21, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X3, X30, [X20, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MADD X11, X1, X12, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W5, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MADD X8, X1, X8, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CSINC W14, W28, W14, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W5, [SP, #140]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB W5, W5, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P15.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LDR X12, [X20, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X17, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X4, X1, X30, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X0, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X20, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W14, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X15, [X20, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X16, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X12, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X20, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X27, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X18, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [X20, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X7, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X15, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [X20, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X7, X15, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X16, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X1, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X12, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X12, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W12, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X20, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W0, [SP, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W0, [X5, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #144	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 44466c <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W12, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ W13, 444b54 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #144	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W13, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W13, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 4449c4 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0–	2.49	3.26
▼Loop 740 - viscosity_kernel.f90:52-89 - exec–	0.00	0.02
○Loop 742 - viscosity_kernel.f90:56-89 - exec	2.48	3.23
○Loop 741 - viscosity_kernel.f90:52-52 - exec	0.00	0.00

Report Configuration

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

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Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code