OV - exec - Function __generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp

	Function: __generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0	Module: exec	Source: generate_chunk_kernel.f90:85-161	Coverage (incl. loops): 0.03% \| (excl. loops): 0.03%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 85 - 161

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85:     !$OMP PARALLEL SHARED(x_cent,y_cent)

86:     !$OMP DO

87:     DO k=y_min-2,y_max+2

88:     !$OMP SIMD

89:       DO j=x_min-2,x_max+2

90:         energy0(j,k)=state_energy(1)

91:       ENDDO

92:     ENDDO

93:     !$OMP END DO

94:     !$OMP DO

95:     DO k=y_min-2,y_max+2

96:     !$OMP SIMD

97:       DO j=x_min-2,x_max+2

98:         density0(j,k)=state_density(1)

99:       ENDDO

100:     ENDDO

101:     !$OMP END DO

102:     !$OMP DO

103:     DO k=y_min-2,y_max+2

104:     !$OMP SIMD

105:       DO j=x_min-2,x_max+2

106:         xvel0(j,k)=state_xvel(1)

107:       ENDDO

108:     ENDDO

109:     !$OMP END DO

110:     !$OMP DO

111:     DO k=y_min-2,y_max+2

112:     !$OMP SIMD

113:       DO j=x_min-2,x_max+2

114:         yvel0(j,k)=state_yvel(1)

115:       ENDDO

116:     ENDDO

117:     !$OMP END DO

118:

119:     DO state=2,number_of_states

120:

121:       ! Could the velocity setting be thread unsafe?

122:       x_cent=state_xmin(state)

123:       y_cent=state_ymin(state)

124:

125:       !$OMP DO PRIVATE(radius,jt,kt)

126:       DO k=y_min-2,y_max+2

127:       !$OMP SIMD

128:         DO j=x_min-2,x_max+2

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

138:                   ENDDO

139:                 ENDDO

140:               ENDIF

141:             ENDIF

142:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

145:               energy0(j,k)=state_energy(state)

146:               density0(j,k)=state_density(state)

147:               DO kt=k,k+1

148:                 DO jt=j,j+1

149:                   xvel0(jt,kt)=state_xvel(state)

150:                   yvel0(jt,kt)=state_yvel(state)

151:                 ENDDO

152:               ENDDO

153:             ENDIF

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

156:               energy0(j,k)=state_energy(state)

157:               density0(j,k)=state_density(state)

158:               DO kt=k,k+1

159:                 DO jt=j,j+1

160:                   xvel0(jt,kt)=state_xvel(state)

161:                   yvel0(jt,kt)=state_yvel(state)

0x424ba0 STP	X29, X30, [SP, #656]!

0x424ba4 ADD	X29, SP, #0

0x424ba8 STP	X25, X26, [SP, #64]

0x424bac ORR	X25, XZR, X0

0x424bb0 STP	X19, X20, [SP, #16]

0x424bb4 STP	X21, X22, [SP, #32]

0x424bb8 STP	X23, X24, [SP, #48]

0x424bbc STP	X27, X28, [SP, #80]

0x424bc0 LDR	X0, [X0, #16]

0x424bc4 LDP	X20, X21, [X25, #208]

0x424bc8 LDR	X1, [X25, #224]

0x424bcc LDR	X2, [X25, #232]

0x424bd0 LDR	X3, [X25, #240]

0x424bd4 STR	X1, [SP, #128]

0x424bd8 LDR	X4, [X25, #248]

0x424bdc STR	X2, [SP, #336]

0x424be0 LDR	X5, [X25, #264]

0x424be4 STR	X3, [SP, #120]

0x424be8 LDR	X6, [X25, #280]

0x424bec STR	X4, [SP, #328]

0x424bf0 LDR	X7, [X25, #296]

0x424bf4 STR	X5, [SP, #320]

0x424bf8 LDR	W26, [X0]

0x424bfc STR	X6, [SP, #312]

0x424c00 LDR	X19, [X25, #256]

0x424c04 STR	X7, [SP, #304]

0x424c08 BL	410110

0x424c0c STR	W0, [SP, #108]

0x424c10 SUB	W26, W26, #2

0x424c14 BL	410130

0x424c18 LDR	X8, [X25, #24]

0x424c1c ORR	W27, WZR, W0

0x424c20 LDR	W1, [SP, #108]

0x424c24 LDR	X24, [X25, #272]

0x424c28 LDR	W9, [X8]

0x424c2c LDR	X28, [X25, #288]

0x424c30 ADD	W10, W9, #3

0x424c34 SUB	W11, W10, W26

0x424c38 SDIV	W12, W11, W1

0x424c3c MSUB	W13, W12, W1, W11

0x424c40 CMP	W0, W13

0x424c44 B.LT	4258d4

0x424c48 MADD	W14, W12, W27, W13

0x424c4c ADD	W15, W12, W14

0x424c50 CMP	W14, W15

0x424c54 B.GE	424cd0

0x424c58 LDP	X17, X18, [X25]

0x424c5c ADD	W6, W26, W14

0x424c60 ADD	W7, W26, W15

0x424c64 SBFM	X16, X6, #0, #31

0x424c68 MOVZ	W9, #0

0x424c6c LDR	X2, [SP, #120]

0x424c70 LDR	W12, [X18]

0x424c74 LDR	X0, [SP, #328]

0x424c78 UBFM	X11, X2, #61, #60

0x424c7c LDR	W26, [X17]

0x424c80 ADD	X3, X0, W26,SXTW

0x424c84 MADD	X4, X16, X2, X3

0x424c88 ADD	W13, W12, #5

0x424c8c LDR	X30, [X25, #72]

0x424c90 UBFM	X5, X4, #61, #60

0x424c94 ADD	W4, W12, #3

0x424c98 LDR	X2, [X25, #112]

0x424c9c SUB	X8, X5, #16

0x424ca0 SUB	W17, W26, #2

0x424ca4 CMP	W17, W4

0x424ca8 ADD	X15, X30, X8

0x424cac CSEL	W8, W17, W4, #10

(189) 0x424cb0 CMP	W17, W4

(189) 0x424cb4 B.LT	4257f0

(189) 0x424cb8 ADD	W6, W6, #1

(189) 0x424cbc ADD	X15, X15, X11

(189) 0x424cc0 B.LE	4259d0

(189) 0x424cc4 CMP	W7, W6

(189) 0x424cc8 B.GT	424cb0

0x424ccc CBNZ	W9, 4256fc

0x424cd0 STR	W1, [SP, #108]

0x424cd4 BL	4100d0

0x424cd8 LDP	X9, X10, [X25, #16]

0x424cdc LDR	W1, [SP, #108]

0x424ce0 LDR	W11, [X9]

0x424ce4 LDR	W26, [X10]

0x424ce8 SUB	W18, W11, #2

0x424cec ADD	W2, W26, #3

0x424cf0 SUB	W0, W2, W18

0x424cf4 SDIV	W3, W0, W1

0x424cf8 MSUB	W4, W3, W1, W0

0x424cfc CMP	W27, W4

0x424d00 B.LT	4258b0

0x424d04 MADD	W16, W3, W27, W4

0x424d08 ADD	W17, W3, W16

0x424d0c CMP	W16, W17

0x424d10 B.GE	424d8c

0x424d14 LDR	X8, [SP, #128]

0x424d18 ADD	W6, W18, W16

0x424d1c ADD	W7, W18, W17

0x424d20 LDP	X5, X12, [X25]

0x424d24 SBFM	X30, X6, #0, #31

0x424d28 MOVZ	W10, #0

0x424d2c LDR	X13, [X25, #64]

0x424d30 UBFM	X11, X8, #61, #60

0x424d34 LDR	X15, [SP, #336]

0x424d38 LDR	W14, [X5]

0x424d3c ADD	X18, X15, W14,SXTW

0x424d40 MADD	X26, X30, X8, X18

0x424d44 LDR	W4, [X12]

0x424d48 UBFM	X2, X26, #61, #60

0x424d4c SUB	X0, X2, #16

0x424d50 ADD	X30, X13, X0

0x424d54 LDR	X13, [X25, #104]

0x424d58 SUB	W9, W14, #2

0x424d5c ADD	W3, W4, #5

0x424d60 ADD	W8, W4, #3

0x424d64 CMP	W9, W8

0x424d68 CSEL	W16, W9, W8, #10

(186) 0x424d6c CMP	W9, W8

(186) 0x424d70 B.LT	425850

(186) 0x424d74 ADD	W6, W6, #1

(186) 0x424d78 ADD	X30, X30, X11

(186) 0x424d7c B.LE	4259a8

(186) 0x424d80 CMP	W7, W6

(186) 0x424d84 B.GT	424d6c

0x424d88 CBNZ	W10, 42570c

0x424d8c STR	W1, [SP, #108]

0x424d90 BL	4100d0

0x424d94 LDP	X1, X10, [X25, #16]

0x424d98 LDR	W22, [SP, #108]

0x424d9c LDR	W14, [X1]

0x424da0 LDR	W18, [X10]

0x424da4 SUB	W15, W14, #2

0x424da8 ADD	W26, W18, #3

0x424dac SUB	W0, W26, W15

0x424db0 SDIV	W2, W0, W22

0x424db4 MSUB	W4, W2, W22, W0

0x424db8 CMP	W27, W4

0x424dbc B.LT	4258c8

0x424dc0 MADD	W3, W2, W27, W4

0x424dc4 ADD	W16, W2, W3

0x424dc8 CMP	W3, W16

0x424dcc B.GE	424e44

0x424dd0 LDP	X30, X12, [X25]

0x424dd4 ADD	W6, W15, W3

0x424dd8 ADD	W7, W15, W16

0x424ddc SBFM	X17, X6, #0, #31

0x424de0 MOVZ	W10, #0

0x424de4 UBFM	X11, X24, #61, #60

0x424de8 LDR	X13, [X25, #80]

0x424dec LDR	X1, [SP, #312]

0x424df0 LDR	W8, [X12]

0x424df4 LDR	W5, [X30]

0x424df8 ADD	X14, X1, W5,SXTW

0x424dfc MADD	X15, X17, X24, X14

0x424e00 LDR	X4, [X25, #120]

0x424e04 UBFM	X18, X15, #61, #60

0x424e08 ADD	W0, W8, #5

0x424e0c SUB	X26, X18, #16

0x424e10 ADD	W12, W8, #3

0x424e14 ADD	X2, X13, X26

0x424e18 SUB	W9, W5, #2

0x424e1c CMP	W12, W9

0x424e20 CSEL	W16, W12, W9, #10

(183) 0x424e24 CMP	W12, W9

(183) 0x424e28 B.GT	425790

(183) 0x424e2c ADD	W6, W6, #1

(183) 0x424e30 ADD	X2, X2, X11

(183) 0x424e34 B.GE	4259bc

(183) 0x424e38 CMP	W7, W6

(183) 0x424e3c B.GT	424e24

0x424e40 CBNZ	W10, 425718

0x424e44 STR	W22, [SP, #108]

0x424e48 BL	4100d0

0x424e4c LDP	X13, X8, [X25, #16]

0x424e50 LDR	W22, [SP, #108]

0x424e54 LDR	W5, [X13]

0x424e58 LDR	W14, [X8]

0x424e5c SUB	W1, W5, #2

0x424e60 ADD	W15, W14, #3

0x424e64 SUB	W18, W15, W1

0x424e68 SDIV	W26, W18, W22

0x424e6c MSUB	W0, W26, W22, W18

0x424e70 CMP	W27, W0

0x424e74 B.LT	4258bc

0x424e78 MADD	W16, W26, W27, W0

0x424e7c ADD	W17, W26, W16

0x424e80 CMP	W16, W17

0x424e84 B.GE	424efc

0x424e88 LDP	X30, X4, [X25]

0x424e8c ADD	W6, W1, W16

0x424e90 ADD	W7, W1, W17

0x424e94 SBFM	X3, X6, #0, #31

0x424e98 MOVZ	W10, #0

0x424e9c UBFM	X11, X28, #61, #60

0x424ea0 LDR	X2, [X25, #88]

0x424ea4 LDR	X8, [SP, #304]

0x424ea8 LDR	W13, [X30]

0x424eac ADD	X5, X8, W13,SXTW

0x424eb0 MADD	X1, X3, X28, X5

0x424eb4 LDR	W12, [X4]

0x424eb8 UBFM	X14, X1, #61, #60

0x424ebc LDR	X30, [X25, #128]

0x424ec0 SUB	X15, X14, #16

0x424ec4 ADD	X16, X2, X15

0x424ec8 SUB	W9, W13, #2

0x424ecc ADD	W18, W12, #5

0x424ed0 ADD	W4, W12, #3

0x424ed4 CMP	W4, W9

0x424ed8 CSEL	W26, W4, W9, #10

(180) 0x424edc CMP	W4, W9

(180) 0x424ee0 B.GT	425730

(180) 0x424ee4 ADD	W6, W6, #1

(180) 0x424ee8 ADD	X16, X16, X11

(180) 0x424eec B.GE	425994

(180) 0x424ef0 CMP	W7, W6

(180) 0x424ef4 B.GT	424edc

0x424ef8 CBNZ	W10, 425728

0x424efc STR	W22, [SP, #108]

0x424f00 BL	4100d0

0x424f04 LDR	X23, [X25, #96]

0x424f08 LDR	W10, [X23]

0x424f0c CMP	W10, #1

0x424f10 B.LE	425300

0x424f14 LDR	X2, [SP, #304]

0x424f18 UBFM	X21, X21, #61, #60

0x424f1c UBFM	X1, X19, #61, #60

0x424f20 STR	W27, [SP, #288]

0x424f24 ORR	X27, XZR, X24

0x424f28 ORR	W22, WZR, W10

0x424f2c LDR	X8, [SP, #320]

0x424f30 MOVZ	X26, #1

0x424f34 STR	X22, [SP, #280]

0x424f38 LDR	W24, [SP, #108]

0x424f3c SUB	X12, XZR, X2,LSL #3

0x424f40 SUB	X13, X2, #1

0x424f44 STR	X1, [SP, #360]

0x424f48 SUB	X5, X21, X8,LSL #3

0x424f4c STR	X13, [SP, #256]

0x424f50 ADD	X20, X12, X20,LSL #3

0x424f54 ADD	X19, X12, X19,LSL #3

0x424f58 STR	W24, [SP, #292]

0x424f5c STR	X5, [SP, #352]

0x424f60 STP	X20, X19, [SP, #240]

0x424f64 B	424f7c

(171) 0x424f68 BL	4100d0

(171) 0x424f6c LDR	X13, [SP, #280]

(171) 0x424f70 ADD	X26, X26, #1

(171) 0x424f74 CMP	X26, X13

(171) 0x424f78 B.EQ	425300

(171) 0x424f7c LDP	X14, X15, [X25, #16]

(171) 0x424f80 LDR	W30, [SP, #292]

(171) 0x424f84 LDR	W18, [X15]

(171) 0x424f88 LDR	W6, [X14]

(171) 0x424f8c LDR	X10, [X25, #136]

(171) 0x424f90 ADD	W0, W18, #3

(171) 0x424f94 LDR	X3, [X25, #152]

(171) 0x424f98 SUB	W16, W6, #2

(171) 0x424f9c SUB	W17, W0, W16

(171) 0x424fa0 LDR	D27, [X10, X26,LSL #3]

(171) 0x424fa4 SDIV	W9, W17, W30

(171) 0x424fa8 LDR	D26, [X3, X26,LSL #3]

(171) 0x424fac STP	D26, D27, [X25, #304]

(171) 0x424fb0 LDR	W7, [SP, #288]

(171) 0x424fb4 STR	X3, [SP, #264]

(171) 0x424fb8 MSUB	W4, W9, W30, W17

(171) 0x424fbc CMP	W7, W4

(171) 0x424fc0 B.LT	425618

(171) 0x424fc4 LDR	W11, [SP, #288]

(171) 0x424fc8 MADD	W23, W9, W11, W4

(171) 0x424fcc ADD	W21, W9, W23

(171) 0x424fd0 CMP	W23, W21

(171) 0x424fd4 B.GE	424f68

(171) 0x424fd8 ADD	W1, W16, W21

(171) 0x424fdc ADD	W24, W16, W23

(171) 0x424fe0 LDR	X16, [X25, #8]

(171) 0x424fe4 LDP	X8, X5, [SP, #320]

(171) 0x424fe8 SBFM	X13, X24, #0, #31

(171) 0x424fec MOVZ	W0, #0

(171) 0x424ff0 UBFM	X19, X26, #61, #31

(171) 0x424ff4 STR	W1, [SP, #172]

(171) 0x424ff8 LDR	X22, [X25]

(171) 0x424ffc ADD	X15, X8, X13

(171) 0x425000 LDR	X14, [SP, #120]

(171) 0x425004 LDR	W3, [X16]

(171) 0x425008 LDR	X6, [SP, #128]

(171) 0x42500c MADD	X8, X13, X14, X5

(171) 0x425010 LDR	X20, [SP, #336]

(171) 0x425014 ADD	W4, W3, #4

(171) 0x425018 ADD	W9, W3, #3

(171) 0x42501c LDR	W2, [X22]

(171) 0x425020 LDP	X7, X22, [SP, #304]

(171) 0x425024 MADD	X23, X6, X13, X20

(171) 0x425028 LDR	X18, [X25, #32]

(171) 0x42502c SUB	W12, W2, #2

(171) 0x425030 MADD	X11, X27, X13, X22

(171) 0x425034 SBFM	X17, X12, #0, #31

(171) 0x425038 LDR	X5, [SP, #360]

(171) 0x42503c MADD	X21, X28, X13, X7

(171) 0x425040 SUB	W13, W4, W2

(171) 0x425044 ADD	X6, X22, X17

(171) 0x425048 ADD	X1, X13, W2,SXTW

(171) 0x42504c ADD	X7, X17, X7

(171) 0x425050 LDR	X20, [X25, #56]

(171) 0x425054 SUB	W2, W2, #1

(171) 0x425058 STR	X18, [SP, #200]

(171) 0x42505c LDR	X4, [SP, #352]

(171) 0x425060 ADD	X16, X18, X5

(171) 0x425064 STR	X1, [SP, #232]

(171) 0x425068 LDR	X14, [X25, #48]

(171) 0x42506c STR	X6, [SP, #216]

(171) 0x425070 LDR	X3, [X25, #144]

(171) 0x425074 ADD	X1, X20, X4

(171) 0x425078 STR	X7, [SP, #224]

(171) 0x42507c LDR	X18, [X25, #176]

(171) 0x425080 STR	X1, [SP, #160]

(171) 0x425084 LDR	X22, [X25, #184]

(171) 0x425088 STR	X14, [SP, #208]

(171) 0x42508c LDR	X13, [X25, #192]

(171) 0x425090 STR	X18, [SP, #176]

(171) 0x425094 STR	X3, [SP, #272]

(171) 0x425098 STR	X22, [SP, #184]

(171) 0x42509c STR	W2, [SP, #296]

(171) 0x4250a0 LDR	X30, [X25, #168]

(171) 0x4250a4 STR	X13, [SP, #192]

(171) 0x4250a8 LDR	X20, [X25, #200]

(171) 0x4250ac STR	W9, [SP, #108]

  (177) 0x4250b0 LDR	W9, [SP, #108]

  (177) 0x4250b4 ADD	W24, W24, #1

  (177) 0x4250b8 CMP	W12, W9

  (177) 0x4250bc B.GE	4252b4

  (172) 0x4250c0 LDR	X0, [SP, #176]

  (172) 0x4250c4 LDR	X18, [SP, #184]

  (172) 0x4250c8 LDR	W6, [X0, X26,LSL #2]

  (172) 0x4250cc LDR	W22, [X18]

  (172) 0x4250d0 CMP	W6, W22

  (172) 0x4250d4 B.EQ	4253cc

  (174) 0x4250d8 LDR	X14, [SP, #216]

  (174) 0x4250dc SBFM	X7, X24, #0, #31

  (174) 0x4250e0 ADD	X3, X17, X8

  (174) 0x4250e4 ADD	X2, X17, X23

  (174) 0x4250e8 ADD	X5, X11, X17

  (174) 0x4250ec STR	X8, [SP, #152]

  (174) 0x4250f0 LDR	X9, [SP, #248]

  (174) 0x4250f4 MUL	X18, X28, X7

  (174) 0x4250f8 ADD	X4, X21, X17

  (174) 0x4250fc STR	W24, [SP, #168]

  (174) 0x425100 LDR	X0, [SP, #256]

  (174) 0x425104 MADD	X1, X27, X7, X14

  (174) 0x425108 LDR	X22, [SP, #192]

  (174) 0x42510c SUB	X7, X9, X18,LSL #3

  (174) 0x425110 LDR	X9, [SP, #224]

  (174) 0x425114 ADD	X14, X0, X18

  (174) 0x425118 LDR	X13, [SP, #240]

  (174) 0x42511c LDR	W22, [X22]

  (174) 0x425120 ADD	X0, X9, X18

  (174) 0x425124 STP	X28, X27, [SP, #136]

  (174) 0x425128 SUB	X18, X13, X18,LSL #3

  (174) 0x42512c LDR	X9, [SP, #200]

  (174) 0x425130 LDR	X27, [SP, #208]

  (174) 0x425134 LDR	X13, [SP, #232]

  (174) 0x425138 ADD	X7, X9, X7

  (174) 0x42513c ADD	X8, X27, X18

  (174) 0x425140 STR	X7, [SP, #112]

  (174) 0x425144 ADD	X14, X13, X14

  (174) 0x425148 B	425188

    (175) 0x42514c LDR	W28, [X20]

    (175) 0x425150 CMP	W6, W28

    (175) 0x425154 B.EQ	42531c

    (175) 0x425158 ADD	X18, X5, #1

    (175) 0x42515c ADD	X13, X4, #1

    (175) 0x425160 ADD	X9, X1, #1

    (175) 0x425164 ADD	X7, X0, #1

    (175) 0x425168 ADD	X3, X3, #1

    (175) 0x42516c ADD	X2, X2, #1

    (175) 0x425170 ORR	X5, XZR, X18

    (175) 0x425174 ORR	X4, XZR, X13

    (175) 0x425178 ORR	X1, XZR, X9

    (175) 0x42517c ORR	X0, XZR, X7

    (175) 0x425180 CMP	X14, X7

    (175) 0x425184 B.EQ	425260

    (175) 0x425188 CMP	W6, W22

    (175) 0x42518c B.NE	42514c

    (175) 0x425190 LDR	X13, [SP, #160]

    (175) 0x425194 LDR	D31, [X8, X0,LSL #3]

    (175) 0x425198 LDR	D30, [X30, X26,LSL #3]

    (175) 0x42519c LDR	D29, [X13, X15,LSL #3]

    (175) 0x4251a0 FSUB	D28, D31, S27

    (175) 0x4251a4 FSUB	D6, D29, S26

    (175) 0x4251a8 FMUL	D7, D6, D6

    (175) 0x4251ac FMADD	D5, D28, D28, D7

    (175) 0x4251b0 FSQRT	D4, D5

    (175) 0x4251b4 FCMPE	D4, D30

    (175) 0x4251b8 B.GT	425158

    (175) 0x4251bc LDP	X27, X7, [X25, #104]

    (175) 0x4251c0 ADD	X18, X5, #1

    (175) 0x4251c4 ADD	X13, X4, #1

    (175) 0x4251c8 ADD	X9, X1, #1

    (175) 0x4251cc LDR	X24, [X25, #72]

    (175) 0x4251d0 LDR	D3, [X7, X26,LSL #3]

    (175) 0x4251d4 ADD	X7, X0, #1

    (175) 0x4251d8 LDR	X28, [X25, #120]

    (175) 0x4251dc STR	D3, [X24, X3,LSL #3]

    (175) 0x4251e0 ADD	X3, X3, #1

    (175) 0x4251e4 LDR	D2, [X27, X26,LSL #3]

    (175) 0x4251e8 LDR	X24, [X25, #64]

    (175) 0x4251ec LDR	X27, [X25, #80]

    (175) 0x4251f0 STR	D2, [X24, X2,LSL #3]

    (175) 0x4251f4 ADD	X2, X2, #1

    (175) 0x4251f8 LDR	D1, [X28, X19]

    (175) 0x4251fc LDR	X24, [X25, #128]

    (175) 0x425200 STR	D1, [X27, X5,LSL #3]

    (175) 0x425204 LDR	D0, [X24, X19]

    (175) 0x425208 LDR	X5, [X25, #88]

    (175) 0x42520c STR	D0, [X5, X4,LSL #3]

    (175) 0x425210 ORR	X4, XZR, X13

    (175) 0x425214 LDR	D16, [X28, X19]

    (175) 0x425218 STR	D16, [X27, X18,LSL #3]

    (175) 0x42521c LDR	D17, [X24, X19]

    (175) 0x425220 STR	D17, [X5, X13,LSL #3]

    (175) 0x425224 LDR	D18, [X28, X19]

    (175) 0x425228 STR	D18, [X27, X1,LSL #3]

    (175) 0x42522c ORR	X1, XZR, X9

    (175) 0x425230 LDR	D19, [X24, X19]

    (175) 0x425234 STR	D19, [X5, X0,LSL #3]

    (175) 0x425238 ORR	X0, XZR, X7

    (175) 0x42523c LDR	D20, [X28, X19]

    (175) 0x425240 STR	D20, [X27, X9,LSL #3]

    (175) 0x425244 LDR	D21, [X24, X19]

    (175) 0x425248 STR	D21, [X5, X7,LSL #3]

    (175) 0x42524c ORR	X5, XZR, X18

    (175) 0x425250 CMP	X14, X7

    (175) 0x425254 B.NE	425188

  (174) 0x425258 HINT	#0

  (174) 0x42525c HINT	#0

  (174) 0x425260 LDR	X8, [SP, #152]

  (174) 0x425264 LDP	X28, X27, [SP, #136]

  (174) 0x425268 LDR	W24, [SP, #168]

  (174) 0x42526c ADD	X18, X15, #1

  (172) 0x425270 LDR	X6, [SP, #120]

  (172) 0x425274 ORR	X15, XZR, X18

  (172) 0x425278 ADD	X11, X11, X27

  (172) 0x42527c ADD	X21, X21, X28

  (172) 0x425280 LDR	X22, [SP, #128]

  (172) 0x425284 LDR	W14, [SP, #172]

  (172) 0x425288 ADD	X8, X8, X6

  (172) 0x42528c ADD	X23, X23, X22

  (172) 0x425290 CMP	W14, W24

  (172) 0x425294 B.LE	425624

  (172) 0x425298 LDR	W9, [SP, #108]

  (172) 0x42529c MOVZ	W0, #1

  (172) 0x4252a0 ADD	W24, W24, #1

  (172) 0x4252a4 STR	W9, [SP, #300]

  (172) 0x4252a8 LDR	W9, [SP, #108]

  (172) 0x4252ac CMP	W12, W9

  (172) 0x4252b0 B.LT	4250c0

  (176) 0x4252b4 B.EQ	42526c

  (177) 0x4252b8 LDR	X5, [SP, #120]

  (177) 0x4252bc ADD	X15, X15, #1

  (177) 0x4252c0 ADD	X11, X11, X27

  (177) 0x4252c4 ADD	X21, X21, X28

  (177) 0x4252c8 LDR	X2, [SP, #128]

  (177) 0x4252cc LDR	W14, [SP, #172]

  (177) 0x4252d0 ADD	X8, X8, X5

  (177) 0x4252d4 ADD	X23, X23, X2

  (177) 0x4252d8 CMP	W14, W24

  (177) 0x4252dc B.GT	4250b0

(171) 0x4252e0 CBZ	W0, 424f68

(171) 0x4252e4 LDR	W18, [SP, #300]

(171) 0x4252e8 STR	W18, [X25, #320]

(171) 0x4252ec BL	4100d0

(171) 0x4252f0 LDR	X13, [SP, #280]

(171) 0x4252f4 ADD	X26, X26, #1

(171) 0x4252f8 CMP	X26, X13

(171) 0x4252fc B.NE	424f7c

0x425300 LDP	X19, X20, [SP, #16]

0x425304 LDP	X21, X22, [SP, #32]

0x425308 LDP	X23, X24, [SP, #48]

0x42530c LDP	X25, X26, [SP, #64]

0x425310 LDP	X27, X28, [SP, #80]

0x425314 LDP	X29, X30, [SP], #368

0x425318 RET

    (175) 0x42531c LDR	X24, [SP, #112]

    (175) 0x425320 LDR	D1, [X24, X0,LSL #3]

    (175) 0x425324 FCMP	D27, D1

    (175) 0x425328 B.NE	425158

    (175) 0x42532c LDR	X18, [X25, #40]

    (175) 0x425330 LDR	D0, [X18, X15,LSL #3]

    (175) 0x425334 FCMP	D26, D0

    (175) 0x425338 B.NE	425158

    (175) 0x42533c LDP	X28, X7, [X25, #104]

    (175) 0x425340 UBFM	X24, X26, #61, #31

    (175) 0x425344 ADD	X18, X5, #1

    (175) 0x425348 ADD	X13, X4, #1

    (175) 0x42534c ADD	X9, X1, #1

    (175) 0x425350 LDR	X27, [X25, #72]

    (175) 0x425354 LDR	D16, [X7, X26,LSL #3]

    (175) 0x425358 ADD	X7, X0, #1

    (175) 0x42535c STR	D16, [X27, X3,LSL #3]

    (175) 0x425360 LDR	D17, [X28, X26,LSL #3]

    (175) 0x425364 LDR	X27, [X25, #64]

    (175) 0x425368 LDR	X28, [X25, #120]

    (175) 0x42536c STR	D17, [X27, X2,LSL #3]

    (175) 0x425370 LDR	X27, [X25, #128]

    (175) 0x425374 LDR	D18, [X28, X24]

    (175) 0x425378 STR	X27, [SP, #344]

    (175) 0x42537c LDR	X27, [X25, #80]

    (175) 0x425380 STR	D18, [X27, X5,LSL #3]

    (175) 0x425384 LDR	X27, [SP, #344]

    (175) 0x425388 LDR	X5, [X25, #88]

    (175) 0x42538c LDR	D19, [X27, X24]

    (175) 0x425390 STR	D19, [X5, X4,LSL #3]

    (175) 0x425394 LDR	D20, [X28, X24]

    (175) 0x425398 LDR	X4, [X25, #80]

    (175) 0x42539c STR	D20, [X4, X18,LSL #3]

    (175) 0x4253a0 LDR	D21, [X27, X24]

    (175) 0x4253a4 STR	D21, [X5, X13,LSL #3]

    (175) 0x4253a8 LDR	D22, [X28, X24]

    (175) 0x4253ac STR	D22, [X4, X1,LSL #3]

    (175) 0x4253b0 LDR	D23, [X27, X24]

    (175) 0x4253b4 STR	D23, [X5, X0,LSL #3]

    (175) 0x4253b8 LDR	D24, [X28, X24]

    (175) 0x4253bc STR	D24, [X4, X9,LSL #3]

    (175) 0x4253c0 LDR	D25, [X27, X24]

    (175) 0x4253c4 STR	D25, [X5, X7,LSL #3]

    (175) 0x4253c8 B	425168

  (172) 0x4253cc LDR	W3, [SP, #296]

  (172) 0x4253d0 ORN	W7, WZR, W12

  (172) 0x4253d4 SBFM	X0, X12, #0, #31

  (172) 0x4253d8 ADD	X18, X15, #1

  (172) 0x4253dc LDR	D6, [X10, X26,LSL #3]

  (172) 0x4253e0 LDR	W13, [SP, #108]

  (172) 0x4253e4 SBFM	X1, X3, #0, #31

  (172) 0x4253e8 LDR	D7, [X16, W3,SXTW #3]

  (172) 0x4253ec ADD	W4, W13, W7

  (172) 0x4253f0 AND	W2, W4, #0x1

  (172) 0x4253f4 FCMPE	D7, D6

  (172) 0x4253f8 B.MI	425428

  (172) 0x4253fc LDR	X9, [SP, #272]

  (172) 0x425400 LDR	D5, [X16, W12,SXTW #3]

  (172) 0x425404 LDR	D4, [X9, X26,LSL #3]

  (172) 0x425408 FCMPE	D5, D4

  (172) 0x42540c B.GE	425428

  (172) 0x425410 LDR	X5, [X25, #40]

  (172) 0x425414 LDR	X14, [SP, #264]

  (172) 0x425418 LDR	D3, [X5, X18,LSL #3]

  (172) 0x42541c LDR	D2, [X14, X26,LSL #3]

  (172) 0x425420 FCMPE	D3, D2

  (172) 0x425424 B.GE	425630

  (172) 0x425428 LDR	W6, [SP, #108]

  (172) 0x42542c ADD	X0, X0, #1

  (172) 0x425430 ADD	X1, X1, #1

  (172) 0x425434 CMP	W6, W0

  (172) 0x425438 B.LE	425270

  (172) 0x42543c CBZ	W2, 4254a4

  (172) 0x425440 LDR	D31, [X16, X1,LSL #3]

  (172) 0x425444 LDR	D30, [X10, X26,LSL #3]

  (172) 0x425448 FCMPE	D31, D30

  (172) 0x42544c B.MI	425490

  (172) 0x425450 LDR	X2, [SP, #272]

  (172) 0x425454 LDR	D28, [X16, X0,LSL #3]

  (172) 0x425458 LDR	D29, [X2, X26,LSL #3]

  (172) 0x42545c FCMPE	D28, D29

  (172) 0x425460 B.GE	425490

  (172) 0x425464 LDR	X9, [X25, #40]

  (172) 0x425468 LDR	X13, [SP, #264]

  (172) 0x42546c LDR	D6, [X9, X18,LSL #3]

  (172) 0x425470 LDR	D7, [X13, X26,LSL #3]

  (172) 0x425474 FCMPE	D6, D7

  (172) 0x425478 B.MI	425490

  (172) 0x42547c LDR	X22, [X25, #160]

  (172) 0x425480 LDR	D5, [X9, X15,LSL #3]

  (172) 0x425484 LDR	D4, [X22, X26,LSL #3]

  (172) 0x425488 FCMPE	D5, D4

  (172) 0x42548c B.MI	4259e4

  (172) 0x425490 LDR	W2, [SP, #108]

  (172) 0x425494 ADD	X0, X0, #1

  (172) 0x425498 ADD	X1, X1, #1

  (172) 0x42549c CMP	W2, W0

  (172) 0x4254a0 B.LE	425270

  (172) 0x4254a4 LDR	W2, [SP, #108]

  (172) 0x4254a8 B	425514

    (173) 0x4254ac ADD	X1, X1, #1

    (173) 0x4254b0 LDR	D18, [X10, X26,LSL #3]

    (173) 0x4254b4 ADD	X0, X0, #1

    (173) 0x4254b8 LDR	D19, [X16, X1,LSL #3]

    (173) 0x4254bc FCMPE	D19, D18

    (173) 0x4254c0 B.MI	425504

    (173) 0x4254c4 LDR	X7, [SP, #272]

    (173) 0x4254c8 LDR	D20, [X16, X0,LSL #3]

    (173) 0x4254cc LDR	D21, [X7, X26,LSL #3]

    (173) 0x4254d0 FCMPE	D20, D21

    (173) 0x4254d4 B.GE	425504

    (173) 0x4254d8 LDR	X5, [X25, #40]

    (173) 0x4254dc LDR	X22, [SP, #264]

    (173) 0x4254e0 LDR	D22, [X5, X18,LSL #3]

    (173) 0x4254e4 LDR	D23, [X22, X26,LSL #3]

    (173) 0x4254e8 FCMPE	D22, D23

    (173) 0x4254ec B.MI	425504

    (173) 0x4254f0 LDR	X13, [X25, #160]

    (173) 0x4254f4 LDR	D24, [X5, X15,LSL #3]

    (173) 0x4254f8 LDR	D25, [X13, X26,LSL #3]

    (173) 0x4254fc FCMPE	D24, D25

    (173) 0x425500 B.MI	4258e0

    (173) 0x425504 ADD	X0, X0, #1

    (173) 0x425508 ADD	X1, X1, #1

    (173) 0x42550c CMP	W2, W0

    (173) 0x425510 B.LE	425270

    (173) 0x425514 LDR	D22, [X16, X1,LSL #3]

    (173) 0x425518 LDR	D23, [X10, X26,LSL #3]

    (173) 0x42551c FCMPE	D22, D23

    (173) 0x425520 B.MI	4254ac

    (173) 0x425524 LDR	X6, [SP, #272]

    (173) 0x425528 LDR	D24, [X16, X0,LSL #3]

    (173) 0x42552c LDR	D25, [X6, X26,LSL #3]

    (173) 0x425530 FCMPE	D24, D25

    (173) 0x425534 B.GE	4254ac

    (173) 0x425538 LDR	X14, [X25, #40]

    (173) 0x42553c LDR	X4, [SP, #264]

    (173) 0x425540 LDR	D31, [X14, X18,LSL #3]

    (173) 0x425544 LDR	D30, [X4, X26,LSL #3]

    (173) 0x425548 FCMPE	D31, D30

    (173) 0x42554c B.MI	4254ac

    (173) 0x425550 LDR	X22, [X25, #160]

    (173) 0x425554 LDR	D28, [X14, X15,LSL #3]

    (173) 0x425558 LDR	D29, [X22, X26,LSL #3]

    (173) 0x42555c FCMPE	D28, D29

    (173) 0x425560 B.GE	4254ac

    (173) 0x425564 LDP	X14, X6, [X25, #104]

    (173) 0x425568 ADD	X13, X0, X8

    (173) 0x42556c ADD	X5, X23, X0

    (173) 0x425570 SBFM	X4, X24, #0, #31

    (173) 0x425574 UBFM	X3, X26, #61, #31

    (173) 0x425578 ADD	X9, X21, X0

    (173) 0x42557c LDR	X7, [X25, #72]

    (173) 0x425580 LDR	D6, [X6, X26,LSL #3]

    (173) 0x425584 LDR	X22, [X25, #64]

    (173) 0x425588 STR	D6, [X7, X13,LSL #3]

    (173) 0x42558c LDR	D7, [X14, X26,LSL #3]

    (173) 0x425590 LDR	X7, [X25, #120]

    (173) 0x425594 STR	D7, [X22, X5,LSL #3]

    (173) 0x425598 LDP	X13, X14, [SP, #304]

    (173) 0x42559c LDR	D5, [X7, X3]

    (173) 0x4255a0 MADD	X6, X4, X27, X14

    (173) 0x4255a4 MADD	X4, X4, X28, X13

    (173) 0x4255a8 LDR	X5, [X25, #128]

    (173) 0x4255ac ADD	X22, X6, X0

    (173) 0x4255b0 ADD	X13, X6, X1

    (173) 0x4255b4 LDR	X6, [X25, #80]

    (173) 0x4255b8 ADD	X14, X0, X4

    (173) 0x4255bc ADD	X4, X1, X4

    (173) 0x4255c0 STR	X4, [SP, #112]

    (173) 0x4255c4 ADD	X4, X11, X0

    (173) 0x4255c8 STR	D5, [X6, X4,LSL #3]

    (173) 0x4255cc LDR	D4, [X5, X3]

    (173) 0x4255d0 LDR	X4, [X25, #88]

    (173) 0x4255d4 STR	D4, [X4, X9,LSL #3]

    (173) 0x4255d8 ADD	X9, X11, X1

    (173) 0x4255dc LDR	D3, [X7, X3]

    (173) 0x4255e0 STR	D3, [X6, X9,LSL #3]

    (173) 0x4255e4 ADD	X9, X1, X21

    (173) 0x4255e8 LDR	D2, [X5, X3]

    (173) 0x4255ec STR	D2, [X4, X9,LSL #3]

    (173) 0x4255f0 LDR	D1, [X7, X3]

    (173) 0x4255f4 STR	D1, [X6, X22,LSL #3]

    (173) 0x4255f8 LDR	D0, [X5, X3]

    (173) 0x4255fc STR	D0, [X4, X14,LSL #3]

    (173) 0x425600 LDR	D16, [X7, X3]

    (173) 0x425604 STR	D16, [X6, X13,LSL #3]

    (173) 0x425608 LDR	D17, [X5, X3]

    (173) 0x42560c LDR	X3, [SP, #112]

    (173) 0x425610 STR	D17, [X4, X3,LSL #3]

    (173) 0x425614 B	4254ac

(171) 0x425618 ADD	W9, W9, #1

(171) 0x42561c MOVZ	W4, #0

(171) 0x425620 B	424fc4

(171) 0x425624 LDR	W18, [SP, #108]

(171) 0x425628 STR	W18, [X25, #320]

(171) 0x42562c B	4252ec

  (172) 0x425630 LDR	X6, [X25, #160]

  (172) 0x425634 LDR	D1, [X5, X15,LSL #3]

  (172) 0x425638 LDR	D0, [X6, X26,LSL #3]

  (172) 0x42563c FCMPE	D1, D0

  (172) 0x425640 B.GE	425428

  (172) 0x425644 LDP	X22, X4, [X25, #104]

  (172) 0x425648 ADD	X13, X0, X8

  (172) 0x42564c SBFM	X7, X24, #0, #31

  (172) 0x425650 UBFM	X3, X26, #61, #31

  (172) 0x425654 ADD	X5, X23, X0

  (172) 0x425658 ADD	X14, X11, X0

  (172) 0x42565c LDR	X9, [X25, #72]

  (172) 0x425660 LDR	D16, [X4, X26,LSL #3]

  (172) 0x425664 LDR	X6, [X25, #120]

  (172) 0x425668 STR	D16, [X9, X13,LSL #3]

  (172) 0x42566c LDP	X13, X9, [SP, #304]

  (172) 0x425670 LDR	D17, [X22, X26,LSL #3]

  (172) 0x425674 MADD	X4, X7, X27, X9

  (172) 0x425678 LDR	X22, [X25, #64]

  (172) 0x42567c MADD	X7, X7, X28, X13

  (172) 0x425680 ADD	X9, X4, X0

  (172) 0x425684 ADD	X13, X4, X1

  (172) 0x425688 LDR	X4, [X25, #128]

  (172) 0x42568c STR	D17, [X22, X5,LSL #3]

  (172) 0x425690 ADD	X22, X0, X7

  (172) 0x425694 ADD	X7, X1, X7

  (172) 0x425698 LDR	D18, [X6, X3]

  (172) 0x42569c STR	X7, [SP, #112]

  (172) 0x4256a0 ADD	X7, X21, X0

  (172) 0x4256a4 LDR	X5, [X25, #80]

  (172) 0x4256a8 STR	D18, [X5, X14,LSL #3]

  (172) 0x4256ac LDR	D19, [X4, X3]

  (172) 0x4256b0 LDR	X14, [X25, #88]

  (172) 0x4256b4 STR	D19, [X14, X7,LSL #3]

  (172) 0x4256b8 ADD	X7, X11, X1

  (172) 0x4256bc LDR	D20, [X6, X3]

  (172) 0x4256c0 STR	D20, [X5, X7,LSL #3]

  (172) 0x4256c4 ADD	X7, X1, X21

  (172) 0x4256c8 LDR	D21, [X4, X3]

  (172) 0x4256cc STR	D21, [X14, X7,LSL #3]

  (172) 0x4256d0 LDR	D22, [X6, X3]

  (172) 0x4256d4 STR	D22, [X5, X9,LSL #3]

  (172) 0x4256d8 LDR	D23, [X4, X3]

  (172) 0x4256dc STR	D23, [X14, X22,LSL #3]

  (172) 0x4256e0 LDR	D24, [X6, X3]

  (172) 0x4256e4 STR	D24, [X5, X13,LSL #3]

  (172) 0x4256e8 LDR	D25, [X4, X3]

  (172) 0x4256ec LDR	X3, [SP, #112]

  (172) 0x4256f0 STR	D25, [X14, X3,LSL #3]

  (172) 0x4256f4 B	425428

0x4256f8 STR	W8, [SP, #168]

0x4256fc LDR	W7, [SP, #168]

0x425700 STR	W7, [X25, #320]

0x425704 B	424cd0

0x425708 ORR	W22, WZR, W16

0x42570c STR	W22, [X25, #320]

0x425710 B	424d8c

0x425714 STR	W16, [SP, #112]

0x425718 LDR	W10, [SP, #112]

0x42571c STR	W10, [X25, #320]

0x425720 B	424e44

0x425724 ORR	W23, WZR, W26

0x425728 STR	W23, [X25, #320]

0x42572c B	424efc

0x425730 CNTD	X3, ALL

0x425734 SUB	W17, W18, W13

0x425738 PTRUE	P5.B, ALL

0x42573c WHILELO	P8.D, XZR, X17

(179) 0x425740 MOVZ	X0, #0

(179) 0x425744 ORR	P4.B, P8/Z, P8.B, P8.B

  (178) 0x425748 LD1RD	{Z28.D}, P5/Z, [X30]

  (178) 0x42574c ST1D	{Z28.D}, P4, [X16, X0,LSL #3]

  (178) 0x425750 ADD	X0, X0, X3

  (178) 0x425754 WHILELO	P4.D, X0, X17

  (178) 0x425758 B.NE	425748

(179) 0x42575c ADD	W6, W6, #1

(179) 0x425760 ADD	X16, X16, X11

(179) 0x425764 CMP	W4, W9

(179) 0x425768 B.GE	42577c

(179) 0x42576c CMP	W7, W6

(179) 0x425770 B.GT	425740

0x425774 CBZ	W10, 424efc

0x425778 B	425728

(179) 0x42577c CMP	W7, W6

(179) 0x425780 B.LE	425724

(179) 0x425784 ORR	W23, WZR, W26

(179) 0x425788 MOVZ	W10, #1

(179) 0x42578c B	425740

0x425790 CNTD	X30, ALL

0x425794 SUB	W3, W0, W5

0x425798 PTRUE	P2.B, ALL

0x42579c WHILELO	P3.D, XZR, X3

(182) 0x4257a0 MOVZ	X17, #0

(182) 0x4257a4 ORR	P1.B, P3/Z, P3.B, P3.B

  (181) 0x4257a8 LD1RD	{Z29.D}, P2/Z, [X4]

  (181) 0x4257ac ST1D	{Z29.D}, P1, [X2, X17,LSL #3]

  (181) 0x4257b0 ADD	X17, X17, X30

  (181) 0x4257b4 WHILELO	P1.D, X17, X3

  (181) 0x4257b8 B.NE	4257a8

(182) 0x4257bc ADD	W6, W6, #1

(182) 0x4257c0 ADD	X2, X2, X11

(182) 0x4257c4 CMP	W12, W9

(182) 0x4257c8 B.GE	4257dc

(182) 0x4257cc CMP	W7, W6

(182) 0x4257d0 B.GT	4257a0

0x4257d4 CBZ	W10, 424e44

0x4257d8 B	425718

(182) 0x4257dc CMP	W7, W6

(182) 0x4257e0 B.LE	425714

(182) 0x4257e4 MOVZ	W10, #1

(182) 0x4257e8 STR	W16, [SP, #112]

(182) 0x4257ec B	4257a0

0x4257f0 CNTD	X5, ALL

0x4257f4 SUB	W3, W13, W26

0x4257f8 PTRUE	P0.B, ALL

0x4257fc WHILELO	P9.D, XZR, X3

(188) 0x425800 MOVZ	X14, #0

(188) 0x425804 ORR	P7.B, P9/Z, P9.B, P9.B

  (187) 0x425808 LD1RD	{Z31.D}, P0/Z, [X2]

  (187) 0x42580c ST1D	{Z31.D}, P7, [X15, X14,LSL #3]

  (187) 0x425810 ADD	X14, X14, X5

  (187) 0x425814 WHILELO	P7.D, X14, X3

  (187) 0x425818 B.NE	425808

(188) 0x42581c ADD	W6, W6, #1

(188) 0x425820 ADD	X15, X15, X11

(188) 0x425824 CMP	W17, W4

(188) 0x425828 B.LE	42583c

(188) 0x42582c CMP	W7, W6

(188) 0x425830 B.GT	425800

0x425834 CBZ	W9, 424cd0

0x425838 B	4256fc

(188) 0x42583c CMP	W7, W6

(188) 0x425840 B.LE	4256f8

(188) 0x425844 MOVZ	W9, #1

(188) 0x425848 STR	W8, [SP, #168]

(188) 0x42584c B	425800

0x425850 CNTD	X5, ALL

0x425854 SUB	W12, W3, W14

0x425858 PTRUE	P6.B, ALL

0x42585c WHILELO	P15.D, XZR, X12

(185) 0x425860 MOVZ	X17, #0

(185) 0x425864 ORR	P0.B, P15/Z, P15.B, P15.B

  (184) 0x425868 LD1RD	{Z30.D}, P6/Z, [X13]

  (184) 0x42586c ST1D	{Z30.D}, P0, [X30, X17,LSL #3]

  (184) 0x425870 ADD	X17, X17, X5

  (184) 0x425874 WHILELO	P0.D, X17, X12

  (184) 0x425878 B.NE	425868

(185) 0x42587c ADD	W6, W6, #1

(185) 0x425880 ADD	X30, X30, X11

(185) 0x425884 CMP	W9, W8

(185) 0x425888 B.LE	42589c

(185) 0x42588c CMP	W7, W6

(185) 0x425890 B.GT	425860

0x425894 CBZ	W10, 424d8c

0x425898 B	42570c

(185) 0x42589c CMP	W7, W6

(185) 0x4258a0 B.LE	425708

(185) 0x4258a4 ORR	W22, WZR, W16

(185) 0x4258a8 MOVZ	W10, #1

(185) 0x4258ac B	425860

0x4258b0 ADD	W3, W3, #1

0x4258b4 MOVZ	W4, #0

0x4258b8 B	424d04

0x4258bc ADD	W26, W26, #1

0x4258c0 MOVZ	W0, #0

0x4258c4 B	424e78

0x4258c8 ADD	W2, W2, #1

0x4258cc MOVZ	W4, #0

0x4258d0 B	424dc0

0x4258d4 ADD	W12, W12, #1

0x4258d8 MOVZ	W13, #0

0x4258dc B	424c48

    (173) 0x4258e0 LDP	X22, X6, [X25, #104]

    (173) 0x4258e4 ADD	X7, X0, X8

    (173) 0x4258e8 ADD	X5, X23, X0

    (173) 0x4258ec SBFM	X4, X24, #0, #31

    (173) 0x4258f0 UBFM	X3, X26, #61, #31

    (173) 0x4258f4 ADD	X9, X21, X0

    (173) 0x4258f8 LDR	X14, [X25, #72]

    (173) 0x4258fc LDR	D31, [X6, X26,LSL #3]

    (173) 0x425900 LDR	X13, [X25, #64]

    (173) 0x425904 STR	D31, [X14, X7,LSL #3]

    (173) 0x425908 LDR	D30, [X22, X26,LSL #3]

    (173) 0x42590c LDR	X7, [X25, #120]

    (173) 0x425910 STR	D30, [X13, X5,LSL #3]

    (173) 0x425914 LDP	X14, X22, [SP, #304]

    (173) 0x425918 LDR	D28, [X7, X3]

    (173) 0x42591c MADD	X6, X4, X27, X22

    (173) 0x425920 MADD	X4, X4, X28, X14

    (173) 0x425924 LDR	X5, [X25, #128]

    (173) 0x425928 ADD	X22, X6, X0

    (173) 0x42592c ADD	X13, X6, X1

    (173) 0x425930 LDR	X6, [X25, #80]

    (173) 0x425934 ADD	X14, X0, X4

    (173) 0x425938 ADD	X4, X1, X4

    (173) 0x42593c STR	X4, [SP, #112]

    (173) 0x425940 ADD	X4, X11, X0

    (173) 0x425944 STR	D28, [X6, X4,LSL #3]

    (173) 0x425948 LDR	D29, [X5, X3]

    (173) 0x42594c LDR	X4, [X25, #88]

    (173) 0x425950 STR	D29, [X4, X9,LSL #3]

    (173) 0x425954 ADD	X9, X11, X1

    (173) 0x425958 LDR	D6, [X7, X3]

    (173) 0x42595c STR	D6, [X6, X9,LSL #3]

    (173) 0x425960 ADD	X9, X1, X21

    (173) 0x425964 LDR	D7, [X5, X3]

    (173) 0x425968 STR	D7, [X4, X9,LSL #3]

    (173) 0x42596c LDR	D5, [X7, X3]

    (173) 0x425970 STR	D5, [X6, X22,LSL #3]

    (173) 0x425974 LDR	D4, [X5, X3]

    (173) 0x425978 STR	D4, [X4, X14,LSL #3]

    (173) 0x42597c LDR	D3, [X7, X3]

    (173) 0x425980 STR	D3, [X6, X13,LSL #3]

    (173) 0x425984 LDR	D2, [X5, X3]

    (173) 0x425988 LDR	X3, [SP, #112]

    (173) 0x42598c STR	D2, [X4, X3,LSL #3]

    (173) 0x425990 B	425504

(180) 0x425994 CMP	W7, W6

(180) 0x425998 B.LE	425724

(180) 0x42599c ORR	W23, WZR, W26

(180) 0x4259a0 MOVZ	W10, #1

(180) 0x4259a4 B	424edc

(186) 0x4259a8 CMP	W7, W6

(186) 0x4259ac B.LE	425708

(186) 0x4259b0 ORR	W22, WZR, W16

(186) 0x4259b4 MOVZ	W10, #1

(186) 0x4259b8 B	424d6c

(183) 0x4259bc CMP	W7, W6

(183) 0x4259c0 B.LE	425714

(183) 0x4259c4 MOVZ	W10, #1

(183) 0x4259c8 STR	W16, [SP, #112]

(183) 0x4259cc B	424e24

(189) 0x4259d0 CMP	W7, W6

(189) 0x4259d4 B.LE	4256f8

(189) 0x4259d8 MOVZ	W9, #1

(189) 0x4259dc STR	W8, [SP, #168]

(189) 0x4259e0 B	424cb0

  (172) 0x4259e4 LDP	X9, X5, [X25, #104]

  (172) 0x4259e8 ADD	X6, X0, X8

  (172) 0x4259ec ADD	X4, X23, X0

  (172) 0x4259f0 UBFM	X2, X26, #61, #31

  (172) 0x4259f4 SBFM	X3, X24, #0, #31

  (172) 0x4259f8 ADD	X7, X21, X0

  (172) 0x4259fc LDR	X14, [X25, #72]

  (172) 0x425a00 LDR	D3, [X5, X26,LSL #3]

  (172) 0x425a04 LDR	X13, [X25, #64]

  (172) 0x425a08 LDR	X5, [X25, #80]

  (172) 0x425a0c STR	D3, [X14, X6,LSL #3]

  (172) 0x425a10 LDR	D2, [X9, X26,LSL #3]

  (172) 0x425a14 LDR	X6, [X25, #120]

  (172) 0x425a18 STR	D2, [X13, X4,LSL #3]

  (172) 0x425a1c LDP	X22, X14, [SP, #304]

  (172) 0x425a20 LDR	D1, [X6, X2]

  (172) 0x425a24 MADD	X9, X3, X27, X14

  (172) 0x425a28 LDR	X4, [X25, #128]

  (172) 0x425a2c MADD	X3, X3, X28, X22

  (172) 0x425a30 ADD	X14, X9, X0

  (172) 0x425a34 ADD	X22, X9, X1

  (172) 0x425a38 ADD	X13, X1, X3

  (172) 0x425a3c ADD	X9, X0, X3

  (172) 0x425a40 ADD	X3, X11, X0

  (172) 0x425a44 STR	D1, [X5, X3,LSL #3]

  (172) 0x425a48 LDR	D0, [X4, X2]

  (172) 0x425a4c LDR	X3, [X25, #88]

  (172) 0x425a50 STR	D0, [X3, X7,LSL #3]

  (172) 0x425a54 ADD	X7, X11, X1

  (172) 0x425a58 LDR	D16, [X6, X2]

  (172) 0x425a5c STR	D16, [X5, X7,LSL #3]

  (172) 0x425a60 ADD	X7, X1, X21

  (172) 0x425a64 LDR	D17, [X4, X2]

  (172) 0x425a68 STR	D17, [X3, X7,LSL #3]

  (172) 0x425a6c LDR	D18, [X6, X2]

  (172) 0x425a70 STR	D18, [X5, X14,LSL #3]

  (172) 0x425a74 LDR	D19, [X4, X2]

  (172) 0x425a78 STR	D19, [X3, X9,LSL #3]

  (172) 0x425a7c LDR	D20, [X6, X2]

  (172) 0x425a80 STR	D20, [X5, X22,LSL #3]

  (172) 0x425a84 LDR	D21, [X4, X2]

  (172) 0x425a88 STR	D21, [X3, X13,LSL #3]

  (172) 0x425a8c B	425490

Coverage (%)	Name	Source Location	Module
►98.13+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.88+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run gcc_5

Source file and lines	generate_chunk_kernel.f90:85-161
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:85-161.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 50.00 to 12.50 cycles (4.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 50.00 to 21.87 cycles (2.29x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.00 to 34.75 cycles (1.44x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:85
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:88
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:96
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:104
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:112

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 39 bytes.

General properties

nb instructions	271
nb uops	271
loop length	1084
used w registers	25
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	48

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.88 cycles
front end	33.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	18.50	18.50	35.75	35.75	35.75	35.75	0.00	0.00	0.00	0.00	32.83	32.50	32.67	15.50	15.50
cycles	18.50	18.50	35.75	35.75	35.75	35.75	0.00	0.00	0.00	0.00	32.83	32.50	32.67	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

20.00-50.00

Cycles summary

Front-end	33.88
Dispatch	35.75
DIV/SQRT	20.00-50.00
Overall L1	35.75-50.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	23%
load	23%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	16%
div/sqrt	12%
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 50.00 cycles. At this rate:

1% of peak load performance is reached (1.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 424ba0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X20, X21, [X25, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X1, [X25, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X25, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X25, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X25, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X25, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X25, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X4, [SP, #328]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X25, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W26, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X6, [SP, #312]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X25, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X7, [SP, #304]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410110 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
STR W0, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB W26, W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410130 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W27, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W1, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X25, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X25, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W10, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB W11, W10, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W12, W11, W1	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W13, W12, W1, W11	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4258d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W14, W12, W27, W13	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W15, W12, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W14, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 424cd0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X18, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W6, W26, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W7, W26, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X16, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
MOVZ W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X2, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W12, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #328]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X11, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W26, [X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD X3, X0, W26,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MADD X4, X16, X2, X3	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD W13, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X30, [X25, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W4, W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X2, [X25, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X8, X5, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB W17, W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W17, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
ADD X15, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL W8, W17, W4, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CBNZ W9, 4256fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W1, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X10, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W1, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W11, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W26, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W18, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W2, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W2, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SDIV W3, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W4, W3, W1, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W27, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4258b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W16, W3, W27, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W17, W3, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W16, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 424d8c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W6, W18, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W7, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X5, X12, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SBFM X30, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X25, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X11, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X15, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W14, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD X18, X15, W14,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
MADD X26, X30, X8, X18	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR W4, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X0, X2, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X30, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X25, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W9, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W3, W4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W8, W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W16, W9, W8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CBNZ W10, 42570c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W1, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X10, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W22, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W14, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W15, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W26, W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W26, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SDIV W2, W0, W22	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W4, W2, W22, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W27, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4258c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W2, W27, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W16, W2, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W3, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 424e44 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X30, X12, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W6, W15, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W7, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X17, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X11, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X13, [X25, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W5, [X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X1, W5,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MADD X15, X17, X24, X14	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X4, [X25, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X18, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W0, W8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X26, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W12, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X2, X13, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W9, W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W16, W12, W9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CBNZ W10, 425718 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W22, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X8, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W22, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W5, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W1, W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W15, W14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W18, W15, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SDIV W26, W18, W22	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W0, W26, W22, W18	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W27, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4258bc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W16, W26, W27, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W17, W26, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W16, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 424efc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X30, X4, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W6, W1, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W7, W1, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X3, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X11, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X2, [X25, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #304]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X8, W13,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
MADD X1, X3, X28, X5	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR W12, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X14, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X30, [X25, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X15, X14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W9, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W18, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W4, W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W4, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W26, W4, W9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CBNZ W10, 425728 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W22, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X25, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W10, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 425300 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x760>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #304]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X21, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X1, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W27, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ORR X27, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W22, WZR, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X22, [SP, #280]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W24, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB X12, XZR, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X13, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #360]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X5, X21, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X20, X12, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X12, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR W24, [SP, #292]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X5, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 424f7c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W8, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W7, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W7, [X25, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 424cd0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR W22, [X25, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 424d8c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W16, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W10, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W10, [X25, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 424e44 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W23, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W23, [X25, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 424efc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X3, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W17, W18, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
PTRUE P5.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P8.D, XZR, X17	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
CBZ W10, 424efc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 425728 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X30, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SUB W3, W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P3.D, XZR, X3	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
CBZ W10, 424e44 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 425718 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SUB W3, W13, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P9.D, XZR, X3	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
CBZ W9, 424cd0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4256fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SUB W12, W3, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P15.D, XZR, X12	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
CBZ W10, 424d8c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42570c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 424d04 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 424e78 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 424dc0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 424c48 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run gcc_5

Source file and lines	generate_chunk_kernel.f90:85-161
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.00 to 34.75 cycles (1.44x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:85
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:86
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:88
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:96
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:104
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:112

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 39 bytes.

General properties

nb instructions	271
nb uops	271
loop length	1084
used w registers	25
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	48

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.88 cycles
front end	33.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	18.50	18.50	35.75	35.75	35.75	35.75	0.00	0.00	0.00	0.00	32.83	32.50	32.67	15.50	15.50
cycles	18.50	18.50	35.75	35.75	35.75	35.75	0.00	0.00	0.00	0.00	32.83	32.50	32.67	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

20.00-50.00

Cycles summary

Front-end	33.88
Dispatch	35.75
DIV/SQRT	20.00-50.00
Overall L1	35.75-50.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	23%
load	23%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	16%
div/sqrt	12%
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 50.00 cycles. At this rate:

1% of peak load performance is reached (1.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 424ba0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X20, X21, [X25, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X1, [X25, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X25, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X25, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X25, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X25, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X25, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X4, [SP, #328]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X25, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W26, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X6, [SP, #312]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X25, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X7, [SP, #304]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410110 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
STR W0, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
SUB W26, W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410130 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W27, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W1, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X25, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X25, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W10, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB W11, W10, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W12, W11, W1	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W13, W12, W1, W11	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4258d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W14, W12, W27, W13	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W15, W12, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W14, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 424cd0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X18, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W6, W26, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W7, W26, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X16, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
MOVZ W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X2, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W12, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #328]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X11, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W26, [X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD X3, X0, W26,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MADD X4, X16, X2, X3	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD W13, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X30, [X25, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W4, W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X2, [X25, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X8, X5, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB W17, W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W17, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
ADD X15, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL W8, W17, W4, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CBNZ W9, 4256fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W1, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X10, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W1, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W11, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W26, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W18, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W2, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W2, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SDIV W3, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W4, W3, W1, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W27, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4258b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W16, W3, W27, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W17, W3, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W16, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 424d8c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W6, W18, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W7, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X5, X12, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SBFM X30, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X25, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X11, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X15, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W14, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD X18, X15, W14,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
MADD X26, X30, X8, X18	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR W4, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X0, X2, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X30, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X25, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W9, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W3, W4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W8, W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W9, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W16, W9, W8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CBNZ W10, 42570c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W1, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X10, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W22, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W14, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W18, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W15, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W26, W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W26, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SDIV W2, W0, W22	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W4, W2, W22, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W27, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4258c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W2, W27, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W16, W2, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W3, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 424e44 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X30, X12, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W6, W15, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W7, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X17, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X11, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X13, [X25, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W5, [X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X1, W5,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MADD X15, X17, X24, X14	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X4, [X25, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X18, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W0, W8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X26, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W12, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X2, X13, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W9, W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W12, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W16, W12, W9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CBNZ W10, 425718 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W22, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X8, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W22, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W5, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W1, W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W15, W14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W18, W15, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SDIV W26, W18, W22	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W0, W26, W22, W18	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W27, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 4258bc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W16, W26, W27, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W17, W26, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W16, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 424efc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X30, X4, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W6, W1, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W7, W1, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X3, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X11, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X2, [X25, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #304]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W13, [X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X8, W13,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
MADD X1, X3, X28, X5	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR W12, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X14, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X30, [X25, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X15, X14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W9, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W18, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W4, W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W4, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W26, W4, W9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CBNZ W10, 425728 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W22, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X25, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W10, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 425300 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x760>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #304]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X21, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X1, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W27, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ORR X27, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W22, WZR, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [SP, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X22, [SP, #280]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W24, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB X12, XZR, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X13, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #360]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X5, X21, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X20, X12, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X12, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR W24, [SP, #292]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X5, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 424f7c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W8, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W7, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W7, [X25, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 424cd0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W22, WZR, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR W22, [X25, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 424d8c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR W16, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W10, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W10, [X25, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 424e44 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W23, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W23, [X25, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B 424efc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X3, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
SUB W17, W18, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
PTRUE P5.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P8.D, XZR, X17	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
CBZ W10, 424efc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 425728 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X30, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SUB W3, W0, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P2.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P3.D, XZR, X3	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
CBZ W10, 424e44 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 425718 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SUB W3, W13, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P9.D, XZR, X3	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
CBZ W9, 424cd0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4256fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
SUB W12, W3, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P15.D, XZR, X12	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
CBZ W10, 424d8c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42570c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 424d04 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 424e78 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 424dc0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 424c48 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0–	0.03	0.04
○Loop 183 - generate_chunk_kernel.f90:98-106 - exec	0.00	0.00
▼Loop 185 - generate_chunk_kernel.f90:98-98 - exec–	0.00	0.00
○Loop 184 - generate_chunk_kernel.f90:98-98 - exec	0.00	0.00
▼Loop 179 - generate_chunk_kernel.f90:114-114 - exec–	0.00	0.00
○Loop 178 - generate_chunk_kernel.f90:114-114 - exec	0.00	0.00
○Loop 180 - generate_chunk_kernel.f90:112-137 - exec	0.00	0.00
▼Loop 188 - generate_chunk_kernel.f90:90-90 - exec–	0.00	0.00
○Loop 187 - generate_chunk_kernel.f90:90-90 - exec	0.00	0.00
▼Loop 182 - generate_chunk_kernel.f90:106-106 - exec–	0.00	0.00
○Loop 181 - generate_chunk_kernel.f90:106-106 - exec	0.00	0.00
○Loop 186 - generate_chunk_kernel.f90:96-114 - exec	0.00	0.00
○Loop 189 - generate_chunk_kernel.f90:88-106 - exec	0.00	0.00
▼Loop 171 - generate_chunk_kernel.f90:119-161 - exec–	0.00	0.00
○Loop 177 - generate_chunk_kernel.f90:130-154 - exec	0.00	0.00
○Loop 176 - generate_chunk_kernel.f90:130-130 - exec	0.00	0.00
▼Loop 174 - generate_chunk_kernel.f90:129-161 - exec–	0.00	0.00
○Loop 175 - generate_chunk_kernel.f90:142-161 - exec	0.00	0.00
▼Loop 172 - generate_chunk_kernel.f90:129-150 - exec–	0.00	0.00
○Loop 173 - generate_chunk_kernel.f90:130-137 - exec	0.00	0.01

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Code clean check

Workaround

Vectorization

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Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code