OV - exec - Function __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp

	Function: __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0	Module: exec	Source: ideal_gas_kernel.f90:45-55	Coverage (incl. loops): 4.38% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90: 45 - 55

--------------------------------------------------------------------------------

45:     !$OMP PARALLEL

46:     !$OMP DO PRIVATE(v,pressurebyenergy,pressurebyvolume,sound_speed_squared)

47:     DO k=y_min,y_max

48:     !$OMP SIMD

49:       DO j=x_min,x_max

50:         v=1.0_8/density(j,k)

51:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

52:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

53:         pressurebyvolume=-density(j,k)*pressure(j,k)

54:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

55:         soundspeed(j,k)=SQRT(sound_speed_squared)

0x4264a0 STP	X29, X30, [SP, #976]!

0x4264a4 ADD	X29, SP, #0

0x4264a8 STP	X19, X20, [SP, #16]

0x4264ac ORR	X20, XZR, X0

0x4264b0 STP	X21, X22, [SP, #32]

0x4264b4 LDR	X0, [X0, #16]

0x4264b8 LDR	W22, [X0]

0x4264bc BL	410110

0x4264c0 ORR	W21, WZR, W0

0x4264c4 BL	410130

0x4264c8 LDR	X1, [X20, #24]

0x4264cc ORR	W8, WZR, W0

0x4264d0 LDR	W2, [X1]

0x4264d4 ADD	W3, W2, #1

0x4264d8 SUB	W4, W3, W22

0x4264dc SDIV	W5, W4, W21

0x4264e0 MSUB	W6, W5, W21, W4

0x4264e4 CMP	W0, W6

0x4264e8 B.LT	426638

0x4264ec MADD	W7, W5, W8, W6

0x4264f0 ADD	W9, W5, W7

0x4264f4 CMP	W7, W9

0x4264f8 B.GE	426628

0x4264fc LDP	X18, X30, [X20]

0x426500 ADD	W8, W22, W7

0x426504 ADD	W0, W22, W9

0x426508 SBFM	X17, X8, #0, #31

0x42650c LDP	X11, X22, [X20, #64]

0x426510 LDP	X16, X15, [X20, #32]

0x426514 LDP	X10, X21, [X20, #80]

0x426518 LDP	X12, X1, [X20, #96]

0x42651c LDP	X13, X5, [X20, #112]

0x426520 LDR	W7, [X18]

0x426524 LDR	W30, [X30]

0x426528 LDR	X14, [X20, #48]

0x42652c SBFM	X2, X7, #0, #31

0x426530 ADD	X3, X2, X22

0x426534 ADD	X6, X2, X21

0x426538 ADD	X4, X2, X1

0x42653c ADD	X9, X2, X5

0x426540 MADD	X18, X17, X11, X3

0x426544 CMP	W7, W30

0x426548 UBFM	X11, X11, #61, #60

0x42654c MADD	X22, X17, X10, X6

0x426550 UBFM	X10, X10, #61, #60

0x426554 MADD	X21, X17, X12, X4

0x426558 UBFM	X12, X12, #61, #60

0x42655c ADD	X3, X16, X18,LSL #3

0x426560 LDR	X16, [X20, #56]

0x426564 MADD	X17, X17, X13, X9

0x426568 UBFM	X13, X13, #61, #60

0x42656c CSINC	W9, W7, W30, #12

0x426570 ADD	X6, X15, X22,LSL #3

0x426574 ADD	W15, W30, #1

0x426578 ADD	X4, X14, X21,LSL #3

0x42657c ADD	X2, X16, X17,LSL #3

0x426580 B.GT	426644

0x426584 CNTD	X22, ALL

0x426588 ADRP	X19,

0x42658c PTRUE	P7.B, ALL

0x426590 ADRP	X1,

0x426594 SUB	W5, W15, W7

0x426598 FDUP	Z31.D, #112

0x42659c ADD	X7, X19, #2144

0x4265a0 ADD	X18, X1, #2152

0x4265a4 WHILELO	P15.D, XZR, X5

0x4265a8 LD1RD	{Z30.D}, P7/Z, [X7]

0x4265ac LD1RD	{Z29.D}, P7/Z, [X18]

(203) 0x4265b0 MOVZ	X21, #0

(203) 0x4265b4 ORR	P6.B, P15/Z, P15.B, P15.B

(203) 0x4265b8 HINT	#0

(203) 0x4265bc HINT	#0

  (202) 0x4265c0 LD1D	{Z0.D}, P6/Z, [X3, X21,LSL #3]

  (202) 0x4265c4 LD1D	{Z26.D}, P6/Z, [X6, X21,LSL #3]

  (202) 0x4265c8 MOVPRFX	Z27, Z31

  (202) 0x4265cc FDIV	Z27.D, P7/M, Z27.D, Z0.D

  (202) 0x4265d0 FMUL	Z1.D, Z26.D, Z0.D

  (202) 0x4265d4 FMUL	Z2.D, Z27.D, Z27.D

  (202) 0x4265d8 FMUL	Z3.D, Z1.D, Z30.D

  (202) 0x4265dc ST1D	{Z3.D}, P6, [X4, X21,LSL #3]

  (202) 0x4265e0 LD1D	{Z28.D}, P6/Z, [X3, X21,LSL #3]

  (202) 0x4265e4 FMUL	Z4.D, Z28.D, Z29.D

  (202) 0x4265e8 FMUL	Z5.D, Z4.D, Z3.D

  (202) 0x4265ec FMUL	Z6.D, Z5.D, Z2.D

  (202) 0x4265f0 FSQRT	Z6.D, P7/M, Z6.D

  (202) 0x4265f4 ST1D	{Z6.D}, P6, [X2, X21,LSL #3]

  (202) 0x4265f8 ADD	X21, X21, X22

  (202) 0x4265fc WHILELO	P6.D, X21, X5

  (202) 0x426600 B.NE	4265c0

(203) 0x426604 ADD	W8, W8, #1

(203) 0x426608 ADD	X3, X3, X11

(203) 0x42660c ADD	X6, X6, X10

(203) 0x426610 ADD	X4, X4, X12

(203) 0x426614 ADD	X2, X2, X13

(203) 0x426618 CMP	W0, W8

(203) 0x42661c B.GT	4265b0

0x426620 ORR	W19, WZR, W9

0x426624 STR	W19, [X20, #128]

0x426628 LDP	X19, X20, [SP, #16]

0x42662c LDP	X21, X22, [SP, #32]

0x426630 LDP	X29, X30, [SP], #48

0x426634 RET

0x426638 ADD	W5, W5, #1

0x42663c MOVZ	W6, #0

0x426640 B	4264ec

0x426644 MOVZ	W14, #0

(201) 0x426648 ADD	W8, W8, #1

(201) 0x42664c CMP	W15, W9

(201) 0x426650 B.EQ	426670

(201) 0x426654 CMP	W0, W8

(201) 0x426658 B.GT	426648

0x42665c CBNZ	W14, 426624

0x426660 LDP	X19, X20, [SP, #16]

0x426664 LDP	X21, X22, [SP, #32]

0x426668 LDP	X29, X30, [SP], #48

0x42666c RET

(201) 0x426670 CMP	W0, W8

(201) 0x426674 B.LE	426620

(201) 0x426678 ORR	W19, WZR, W15

(201) 0x42667c MOVZ	W14, #1

(201) 0x426680 B	426648

Coverage (%)	Name	Module
►98.44+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	83
nb uops	83
loop length	332
used w registers	16
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	3
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.38 cycles
front end	10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	12.50	12.50	12.50	12.50	0.50	0.50	0.00	0.00	8.67	8.67	8.67	2.00	2.00
cycles	4.50	4.50	12.50	12.50	12.50	12.50	0.50	0.50	0.00	0.00	8.67	8.67	8.67	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	10.38
Dispatch	12.50
DIV/SQRT	5.00-12.50
Overall L1	12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	28%
load	34%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	21%
other	31%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	28%
load	34%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	21%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (0.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4264a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W22, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 410110 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410130 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W3, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W5, W4, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W6, W5, W21, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 426638 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W7, W5, W8, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W9, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 426628 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X18, X30, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W8, W22, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W22, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X17, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDP X11, X22, [X20, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X16, X15, [X20, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X21, [X20, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X1, [X20, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X5, [X20, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W7, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W30, [X30]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X20, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X2, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X3, X2, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X2, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X2, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X18, X17, X11, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
CMP W7, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X22, X17, X10, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X21, X17, X12, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X12, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X16, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X20, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X17, X17, X13, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X13, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W9, W7, W30, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X6, X15, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W15, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X4, X14, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X16, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GT 426644 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X22, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X19, <464588>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADRP X1, <464590>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W5, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z31.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
ADD X7, X19, #2144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X1, #2152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P15.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LD1RD {Z30.D}, P7/Z, [X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z29.D}, P7/Z, [X18]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
ORR W19, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W19, [X20, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 4264ec <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CBNZ W14, 426624 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
- /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	83
nb uops	83
loop length	332
used w registers	16
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	3
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.38 cycles
front end	10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	12.50	12.50	12.50	12.50	0.50	0.50	0.00	0.00	8.67	8.67	8.67	2.00	2.00
cycles	4.50	4.50	12.50	12.50	12.50	12.50	0.50	0.50	0.00	0.00	8.67	8.67	8.67	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	10.38
Dispatch	12.50
DIV/SQRT	5.00-12.50
Overall L1	12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	28%
load	34%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	21%
other	31%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	28%
load	34%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	21%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (0.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4264a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W22, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
BL 410110 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410130 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W4, W3, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV W5, W4, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W6, W5, W21, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 426638 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W7, W5, W8, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W9, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W7, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 426628 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X18, X30, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W8, W22, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W22, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X17, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDP X11, X22, [X20, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X16, X15, [X20, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X21, [X20, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X1, [X20, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X5, [X20, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR W7, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W30, [X30]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X20, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X2, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD X3, X2, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X2, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X2, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X18, X17, X11, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
CMP W7, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X22, X17, X10, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X21, X17, X12, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X12, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X16, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X20, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X17, X17, X13, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM X13, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W9, W7, W30, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X6, X15, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W15, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X4, X14, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X16, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.GT 426644 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X22, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X19, <464588>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADRP X1, <464590>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB W5, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z31.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
ADD X7, X19, #2144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X1, #2152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P15.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LD1RD {Z30.D}, P7/Z, [X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z29.D}, P7/Z, [X18]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
ORR W19, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W19, [X20, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 4264ec <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CBNZ W14, 426624 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0–	4.38	5.73
▼Loop 203 - ideal_gas_kernel.f90:48-55 - exec–	0.00	0.02
○Loop 202 - ideal_gas_kernel.f90:50-55 - exec	4.38	5.69
○Loop 201 - ideal_gas_kernel.f90:45-48 - exec	0.00	0.00

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