OV - exec - Loop 55

	Loop Id: 55	Module: exec	Source: PdV_kernel.f90:114-135 [...]	Coverage: 8.15%

0x41c68c LD1D	{Z28.D}, P7/Z, [X20, X0,LSL #3]    [17]

0x41c690 LD1D	{Z27.D}, P7/Z, [X19, X0,LSL #3]    [26]

0x41c694 LD1D	{Z2.D}, P7/Z, [X18, X0,LSL #3]    [25]

0x41c698 FADD	Z3.D, Z27.D, Z28.D

0x41c69c LD1D	{Z23.D}, P7/Z, [X30, X0,LSL #3]    [21]

0x41c6a0 LD1D	{Z1.D}, P7/Z, [X7, X0,LSL #3]    [14]

0x41c6a4 LD1D	{Z18.D}, P7/Z, [X15, X0,LSL #3]    [9]

0x41c6a8 LD1D	{Z17.D}, P7/Z, [X14, X0,LSL #3]    [22]

0x41c6ac LD1D	{Z16.D}, P7/Z, [X11, X0,LSL #3]    [5]

0x41c6b0 LD1D	{Z22.D}, P7/Z, [X10, X0,LSL #3]    [3]

0x41c6b4 LD1D	{Z19.D}, P7/Z, [X22, X0,LSL #3]    [28]

0x41c6b8 LD1D	{Z25.D}, P7/Z, [X17, X0,LSL #3]    [24]

0x41c6bc LD1D	{Z29.D}, P7/Z, [X28, X0,LSL #3]    [4]

0x41c6c0 LD1D	{Z21.D}, P7/Z, [X13, X0,LSL #3]    [8]

0x41c6c4 LD1D	{Z28.D}, P7/Z, [X12, X0,LSL #3]    [7]

0x41c6c8 LD1D	{Z27.D}, P7/Z, [X9, X0,LSL #3]    [16]

0x41c6cc FADD	Z24.D, Z1.D, Z23.D

0x41c6d0 FADD	Z4.D, Z17.D, Z18.D

0x41c6d4 FADD	Z5.D, Z22.D, Z16.D

0x41c6d8 FADD	Z7.D, Z25.D, Z2.D

0x41c6dc FADD	Z6.D, Z5.D, Z4.D

0x41c6e0 FADD	Z20.D, Z7.D, Z3.D

0x41c6e4 FADD	Z2.D, Z28.D, Z21.D

0x41c6e8 LD1D	{Z3.D}, P7/Z, [X8, X0,LSL #3]    [15]

0x41c6ec FMUL	Z26.D, Z6.D, Z19.D

0x41c6f0 FMLA	Z26.D, P6/M, Z20.D, Z29.D

0x41c6f4 LD1D	{Z25.D}, P7/Z, [X5, X0,LSL #3]    [13]

0x41c6f8 LD1D	{Z0.D}, P7/Z, [X16, X0,LSL #3]    [23]

0x41c6fc LD1D	{Z23.D}, P7/Z, [X21, X0,LSL #3]    [27]

0x41c700 LD1D	{Z18.D}, P7/Z, [X6, X0,LSL #3]    [6]

0x41c704 LD1D	{Z7.D}, P7/Z, [X26, X0,LSL #3]    [2]

0x41c708 LD1D	{Z20.D}, P7/Z, [X24, X0,LSL #3]    [19]

0x41c70c LD1D	{Z21.D}, P7/Z, [X3, X0,LSL #3]    [12]

0x41c710 LD1D	{Z28.D}, P7/Z, [X25, X0,LSL #3]    [1]

0x41c714 FADD	Z1.D, Z3.D, Z27.D

0x41c718 LD1RD	{Z22.D}, P6/Z, [X27]    [20]

0x41c71c FADD	Z17.D, Z1.D, Z2.D

0x41c720 FADD	Z0.D, Z18.D, Z0.D

0x41c724 FMUL	Z16.D, Z17.D, Z23.D

0x41c728 FADD	Z4.D, Z0.D, Z24.D

0x41c72c FMUL	Z19.D, Z22.D, Z31.D

0x41c730 LD1D	{Z24.D}, P7/Z, [X23, X0,LSL #3]    [18]

0x41c734 FADD	Z29.D, Z20.D, Z7.D

0x41c738 FMLA	Z16.D, P6/M, Z4.D, Z24.D

0x41c73c FDIVR	Z21.D, P6/M, Z21.D, Z29.D

0x41c740 FSUB	Z5.D, Z16.D, Z26.D

0x41c744 FMUL	Z6.D, Z19.D, Z5.D

0x41c748 FADD	Z26.D, Z25.D, Z6.D

0x41c74c FDIVR	Z26.D, P6/M, Z26.D, Z25.D

0x41c750 FDIVR	Z25.D, P6/M, Z25.D, Z30.D

0x41c754 FMUL	Z27.D, Z21.D, Z25.D

0x41c758 FMLS	Z28.D, P6/M, Z27.D, Z6.D

0x41c75c ST1D	{Z28.D}, P7, [X1, X0,LSL #3]    [10]

0x41c760 LD1D	{Z2.D}, P7/Z, [X3, X0,LSL #3]    [12]

0x41c764 FMUL	Z3.D, Z26.D, Z2.D

0x41c768 ST1D	{Z3.D}, P7, [X2, X0,LSL #3]    [11]

0x41c76c INCD	X0, ALL

0x41c770 WHILELO	P7.D, X0, X4

0x41c774 B.NE	41c68c

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90: 114 - 135

--------------------------------------------------------------------------------

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

129:           recip_volume=1.0/volume(j,k)

130:

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

Coverage (%)	Name	Source Location	Module
►98.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	GOMP_parallel		libgomp.so.1.0.0
○	pdv_kernel	PdV_kernel.f90:145	exec
○	pdv	PdV.f90:58	exec
○	hydro	hydro.f90:60	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45 - 2.91
Bottlenecks	P6, P8,
Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:114-123,PdV_kernel.f90:129-135
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.98 - 42.25
CQA cycles if no scalar integer	20.98 - 42.25
CQA cycles if FP arith vectorized	20.98 - 42.25
CQA cycles if fully vectorized	20.98 - 42.25
Front-end cycles	7.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	13.50
P7 cycles	13.50
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	14.50
P11 cycles	14.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	20.98 - 42.25
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.72 - 2.84
Nb FLOP add-sub	60.00
Nb FLOP mul	24.00
Nb FLOP fma	12.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.21 - 42.71
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	98.21
Vectorization ratio load	96.30
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	98.66
Vector-efficiency ratio load	97.22
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45 - 2.91
Bottlenecks	P6, P8,
Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:114-123,PdV_kernel.f90:129-135
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.98 - 42.25
CQA cycles if no scalar integer	20.98 - 42.25
CQA cycles if FP arith vectorized	20.98 - 42.25
CQA cycles if fully vectorized	20.98 - 42.25
Front-end cycles	7.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	13.50
P7 cycles	13.50
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	14.50
P11 cycles	14.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	20.98 - 42.25
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.72 - 2.84
Nb FLOP add-sub	60.00
Nb FLOP mul	24.00
Nb FLOP fma	12.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.21 - 42.71
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	98.21
Vectorization ratio load	96.30
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	98.66
Vector-efficiency ratio load	97.22
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:114-123,129-135.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU loads are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 42.25 to 14.50 cycles (2.91x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
36: multiply (12 inside FMA instructions)
12: divide

The binary loop is loading 832 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	59
nb uops	59
loop length	236
used w registers	0
used x registers	30
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	2.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.38 cycles
front end	7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	13.50	13.50	1.00	1.00	14.50	14.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	13.50	13.50	12.00	12.00	14.50	14.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	20.98-42.25
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.38
Dispatch	14.50
DIV/SQRT	20.98-42.25
Data deps.	2.00
Overall L1	20.98-42.25

Vectorization ratios

INT

all	96%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	97%
load	97%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 42.25 cycles. At this rate:

20% of peak load performance is reached (19.69 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.51 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41c68c

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z28.D}, P7/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P7/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z3.D, Z27.D, Z28.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P7/Z, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P7/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z29.D}, P7/Z, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P7/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z24.D, Z1.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z4.D, Z17.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z5.D, Z22.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z7.D, Z25.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, Z5.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z20.D, Z7.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z2.D, Z28.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z26.D, Z6.D, Z19.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z26.D, P6/M, Z20.D, Z29.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P7/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P7/Z, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z1.D, Z3.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z22.D}, P6/Z, [X27]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FADD Z17.D, Z1.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z0.D, Z18.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z16.D, Z17.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z4.D, Z0.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z19.D, Z22.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z29.D, Z20.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z16.D, P6/M, Z4.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIVR Z21.D, P6/M, Z21.D, Z29.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FSUB Z5.D, Z16.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z6.D, Z19.D, Z5.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z26.D, Z25.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z26.D, P6/M, Z26.D, Z25.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z25.D, P6/M, Z25.D, Z30.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z27.D, Z21.D, Z25.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLS Z28.D, P6/M, Z27.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z28.D}, P7, [X1, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z3.D, Z26.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z3.D}, P7, [X2, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
INCD X0, ALL	1	0	0	1	0	0	0	0	0	0	2	1	N/A
WHILELO P7.D, X0, X4	1	0	0	1	0	0	0	0	0	0	3	2	N/A
B.NE 41c68c <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x7ec>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU loads are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 42.25 to 14.50 cycles (2.91x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
36: multiply (12 inside FMA instructions)
12: divide

The binary loop is loading 832 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	59
nb uops	59
loop length	236
used w registers	0
used x registers	30
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	2.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.38 cycles
front end	7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	13.50	13.50	1.00	1.00	14.50	14.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	13.50	13.50	12.00	12.00	14.50	14.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	20.98-42.25
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.38
Dispatch	14.50
DIV/SQRT	20.98-42.25
Data deps.	2.00
Overall L1	20.98-42.25

Vectorization ratios

INT

all	96%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	97%
load	97%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	97%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 42.25 cycles. At this rate:

20% of peak load performance is reached (19.69 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.51 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41c68c

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z28.D}, P7/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P7/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z3.D, Z27.D, Z28.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P7/Z, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P7/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z29.D}, P7/Z, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P7/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z24.D, Z1.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z4.D, Z17.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z5.D, Z22.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z7.D, Z25.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, Z5.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z20.D, Z7.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z2.D, Z28.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z26.D, Z6.D, Z19.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z26.D, P6/M, Z20.D, Z29.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z23.D}, P7/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P7/Z, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z1.D, Z3.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z22.D}, P6/Z, [X27]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FADD Z17.D, Z1.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z0.D, Z18.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z16.D, Z17.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z4.D, Z0.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z19.D, Z22.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z29.D, Z20.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z16.D, P6/M, Z4.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIVR Z21.D, P6/M, Z21.D, Z29.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FSUB Z5.D, Z16.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z6.D, Z19.D, Z5.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z26.D, Z25.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z26.D, P6/M, Z26.D, Z25.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z25.D, P6/M, Z25.D, Z30.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z27.D, Z21.D, Z25.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLS Z28.D, P6/M, Z27.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z28.D}, P7, [X1, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z3.D, Z26.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z3.D}, P7, [X2, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
INCD X0, ALL	1	0	0	1	0	0	0	0	0	0	2	1	N/A
WHILELO P7.D, X0, X4	1	0	0	1	0	0	0	0	0	0	3	2	N/A
B.NE 41c68c <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x7ec>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code