OV - exec - Loop 742

	Loop Id: 742	Module: exec	Source: viscosity_kernel.f90:56-89	Coverage: 2.48%

0x444808 LD1D	{Z24.D}, P6/Z, [X10, X1,LSL #3]    [5]

0x44480c LD1D	{Z5.D}, P6/Z, [X15, X1,LSL #3]    [11]

0x444810 LD1D	{Z3.D}, P6/Z, [X14, X1,LSL #3]    [10]

0x444814 LD1D	{Z29.D}, P6/Z, [X7, X1,LSL #3]    [2]

0x444818 LD1D	{Z28.D}, P6/Z, [X9, X1,LSL #3]    [4]

0x44481c LD1D	{Z4.D}, P6/Z, [X16, X1,LSL #3]    [12]

0x444820 LD1D	{Z2.D}, P6/Z, [X17, X1,LSL #3]    [13]

0x444824 LD1D	{Z21.D}, P6/Z, [X8, X1,LSL #3]    [3]

0x444828 FADD	Z22.D, Z5.D, Z24.D

0x44482c FADD	Z7.D, Z3.D, Z5.D

0x444830 FADD	Z6.D, Z28.D, Z29.D

0x444834 FADD	Z0.D, Z4.D, Z28.D

0x444838 FADD	Z16.D, Z4.D, Z2.D

0x44483c FADD	Z17.D, Z2.D, Z29.D

0x444840 FADD	Z23.D, Z21.D, Z24.D

0x444844 FSUB	Z18.D, Z0.D, Z17.D

0x444848 LD1D	{Z28.D}, P6/Z, [X18, X1,LSL #3]    [15]

0x44484c LD1RD	{Z29.D}, P7/Z, [X3]    [16]

0x444850 LD1D	{Z5.D}, P6/Z, [X2, X1,LSL #3]    [14]

0x444854 LD1D	{Z1.D}, P6/Z, [X6, X1,LSL #3]    [1]

0x444858 FSUB	Z20.D, Z6.D, Z16.D

0x44485c FADD	Z19.D, Z3.D, Z21.D

0x444860 FSUB	Z26.D, Z7.D, Z23.D

0x444864 FSUB	Z25.D, Z22.D, Z19.D

0x444868 LD1D	{Z3.D}, P6/Z, [X12, X1,LSL #3]    [8]

0x44486c LD1D	{Z7.D}, P6/Z, [X30, X1,LSL #3]    [6]

0x444870 LD1D	{Z2.D}, P6/Z, [X13, X1,LSL #3]    [9]

0x444874 FMUL	Z16.D, Z29.D, Z25.D

0x444878 LD1RD	{Z24.D}, P7/Z, [X3, #1]    [16]

0x44487c FMLA	Z16.D, P7/M, Z28.D, Z20.D

0x444880 FADD	Z22.D, Z24.D, Z29.D

0x444884 FSUB	Z6.D, Z3.D, Z5.D

0x444888 FCMGE	P5.D, P7/Z, Z16.D, #0.0000000

0x44488c FDIVR	Z22.D, P7/M, Z22.D, Z6.D

0x444890 MOVPRFX	Z27, Z31

0x444894 FDIV	Z27.D, P7/M, Z27.D, Z28.D

0x444898 MOVPRFX	Z4, Z31

0x44489c FDIV	Z4.D, P7/M, Z4.D, Z29.D

0x4448a0 FMUL	Z27.D, P7/M, Z27.D, #0.0000000

0x4448a4 FMUL	Z4.D, P7/M, Z4.D, #0.0000000

0x4448a8 FMUL	Z0.D, Z26.D, Z27.D

0x4448ac FADD	Z17.D, Z7.D, Z28.D

0x4448b0 FMLA	Z0.D, P7/M, Z4.D, Z18.D

0x4448b4 FSUB	Z1.D, Z1.D, Z2.D

0x4448b8 FMUL	Z18.D, Z22.D, Z22.D

0x4448bc FDIVR	Z17.D, P7/M, Z17.D, Z1.D

0x4448c0 FMUL	Z23.D, Z22.D, Z17.D

0x4448c4 FABS	Z22.D, P7/M, Z22.D

0x4448c8 FMAXNM	Z22.D, P7/M, Z22.D, Z30.D

0x4448cc FMUL	Z21.D, Z18.D, Z25.D

0x4448d0 FCMLT	P3.D, P7/Z, Z17.D, #0.0000000

0x4448d4 FMUL	Z19.D, Z21.D, Z4.D

0x4448d8 FMUL	Z25.D, Z17.D, Z17.D

0x4448dc FCMGE	P4.D, P7/Z, Z17.D, #0.0000000

0x4448e0 FMUL	Z20.D, Z25.D, Z20.D

0x4448e4 FADD	Z26.D, Z18.D, Z25.D

0x4448e8 FMLA	Z19.D, P7/M, Z20.D, Z27.D

0x4448ec FMAXNM	Z26.D, P7/M, Z26.D, Z30.D

0x4448f0 FMAD	Z23.D, P7/M, Z0.D, Z19.D

0x4448f4 MOVPRFX	Z27, Z17

0x4448f8 FABS	Z27.D, P7/M, Z17.D

0x4448fc FDIVR	Z26.D, P7/M, Z26.D, Z23.D

0x444900 FMAXNM	Z27.D, P7/M, Z27.D, Z30.D

0x444904 FCMGT	P14.D, P7/Z, Z26.D, #0.0000000

0x444908 FCMGT	P1.D, P3/Z, Z27.D, #0.0000000

0x44490c NOR	P0.B, P7/Z, P5.B, P14.B

0x444910 AND	P2.B, P4/Z, P0.B, P6.B

0x444914 AND	P8.B, P1/Z, P0.B, P6.B

0x444918 EOR	P5.B, P7/Z, P2.B, P7.B

0x44491c AND	P0.B, P0/Z, P6.B, P6.B

0x444920 FNEG	Z27.D, P5/M, Z27.D

0x444924 LD1D	{Z0.D}, P0/Z, [X11, X1,LSL #3]    [7]

0x444928 MOVPRFX	Z4, Z31

0x44492c FCPY	Z4.D, P8/M, #-1.0000000

0x444930 FADD	Z3.D, Z0.D, Z0.D

0x444934 FMUL	Z16.D, Z22.D, Z4.D

0x444938 FMUL	Z24.D, Z16.D, Z16.D

0x44493c FMLA	Z24.D, P7/M, Z27.D, Z27.D

0x444940 FSQRT	Z24.D, P7/M, Z24.D

0x444944 FMUL	Z29.D, Z24.D, Z29.D

0x444948 FMUL	Z28.D, Z24.D, Z28.D

0x44494c FDIV	Z29.D, P7/M, Z29.D, Z16.D

0x444950 FDIV	Z28.D, P7/M, Z28.D, Z27.D

0x444954 FABS	Z29.D, P7/M, Z29.D

0x444958 FABS	Z28.D, P7/M, Z28.D

0x44495c FMINNM	Z28.D, P7/M, Z28.D, Z29.D

0x444960 FMUL	Z22.D, Z28.D, Z26.D

0x444964 FMUL	Z5.D, Z22.D, Z22.D

0x444968 MOVPRFX	Z5.D, P0/Z, Z5.D

0x44496c FMUL	Z5.D, P0/M, Z5.D, Z3.D

0x444970 ST1D	{Z5.D}, P6, [X4, X1,LSL #3]    [17]

0x444974 ADD	X1, X1, X19

0x444978 WHILELO	P6.D, X1, X5

0x44497c B.NE	444808

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 56 - 89

--------------------------------------------------------------------------------

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Coverage (%)	Name	Source Location	Module
►98.38+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.62+	GOMP_parallel		libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.65 - 3.31
Bottlenecks	P6, P8,
Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:56-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	55.94 - 112.68
CQA cycles if no scalar integer	55.94 - 112.68
CQA cycles if FP arith vectorized	55.94 - 112.68
CQA cycles if fully vectorized	55.94 - 112.68
Front-end cycles	11.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	6.00
P5 cycles	0.25
P6 cycles	34.00
P7 cycles	34.00
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	9.00
P11 cycles	9.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	55.94 - 112.68
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	94.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.79 - 1.88
Nb FLOP add-sub	72.00
Nb FLOP mul	68.00
Nb FLOP fma	20.00
Nb FLOP div	28.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.54 - 9.15
Bytes prefetched	0.00
Bytes loaded	480.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	0.00
Vectorization ratio all	92.31
Vectorization ratio load	88.24
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	80.00
Vector-efficiency ratio all	93.44
Vector-efficiency ratio load	91.18
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	82.13

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.65 - 3.31
Bottlenecks	P6, P8,
Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:56-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	55.94 - 112.68
CQA cycles if no scalar integer	55.94 - 112.68
CQA cycles if FP arith vectorized	55.94 - 112.68
CQA cycles if fully vectorized	55.94 - 112.68
Front-end cycles	11.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	6.00
P5 cycles	0.25
P6 cycles	34.00
P7 cycles	34.00
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	9.00
P11 cycles	9.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	55.94 - 112.68
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	94.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.79 - 1.88
Nb FLOP add-sub	72.00
Nb FLOP mul	68.00
Nb FLOP fma	20.00
Nb FLOP div	28.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.54 - 9.15
Bytes prefetched	0.00
Bytes loaded	480.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	0.00
Vectorization ratio all	92.31
Vectorization ratio load	88.24
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	80.00
Vector-efficiency ratio all	93.44
Vector-efficiency ratio load	91.18
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	82.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:56-89
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56-89.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU loads are used in vector version.
80% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 112.68 to 30.00 cycles (3.76x speedup).

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 212 FP arithmetical operations:

92: addition or subtraction (20 inside FMA instructions)
88: multiply (20 inside FMA instructions)
28: divide
4: square root

The binary loop is loading 480 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.41 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	94
loop length	376
used w registers	0
used x registers	20
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	1.06

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	6.00	0.25	34.00	34.00	0.50	0.50	9.00	9.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	6.00	0.25	34.00	34.00	20.00	20.00	9.00	9.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	55.94-112.68
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	11.75
Dispatch	34.00
DIV/SQRT	55.94-112.68
Data deps.	0.00
Overall L1	55.94-112.68

Vectorization ratios

INT

all	78%
load	88%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

INT+FP

all	92%
load	88%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	80%

Vector efficiency ratios

INT

all	82%
load	91%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	65%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

INT+FP

all	93%
load	91%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	82%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 112.68 cycles. At this rate:

4% of peak load performance is reached (4.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 444808

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z24.D}, P6/Z, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P6/Z, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P6/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z29.D}, P6/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P6/Z, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P6/Z, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P6/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z22.D, Z5.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z7.D, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z0.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z16.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z17.D, Z2.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z23.D, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z18.D, Z0.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1RD {Z29.D}, P7/Z, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1D {Z5.D}, P6/Z, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P6/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z20.D, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z19.D, Z3.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z26.D, Z7.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z25.D, Z22.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P6/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P6/Z, [X30, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P6/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z16.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1RD {Z24.D}, P7/Z, [X3, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FMLA Z16.D, P7/M, Z28.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z22.D, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z6.D, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGE P5.D, P7/Z, Z16.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIVR Z22.D, P7/M, Z22.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z27, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z27.D, P7/M, Z27.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z4, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z4.D, P7/M, Z4.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z27.D, P7/M, Z27.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z4.D, P7/M, Z4.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z0.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z17.D, Z7.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z0.D, P7/M, Z4.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FSUB Z1.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z17.D, P7/M, Z17.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z23.D, Z22.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FABS Z22.D, P7/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z22.D, P7/M, Z22.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z21.D, Z18.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FCMLT P3.D, P7/Z, Z17.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z19.D, Z21.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z25.D, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FCMGE P4.D, P7/Z, Z17.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z20.D, Z25.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z26.D, Z18.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z19.D, P7/M, Z20.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAXNM Z26.D, P7/M, Z26.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z23.D, P7/M, Z0.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z27, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z27.D, P7/M, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z26.D, P7/M, Z26.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMAXNM Z27.D, P7/M, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P14.D, P7/Z, Z26.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P1.D, P3/Z, Z27.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
NOR P0.B, P7/Z, P5.B, P14.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
AND P2.B, P4/Z, P0.B, P6.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P8.B, P1/Z, P0.B, P6.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
EOR P5.B, P7/Z, P2.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P0.B, P0/Z, P6.B, P6.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FNEG Z27.D, P5/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z0.D}, P0/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z4, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCPY Z4.D, P8/M, #-1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
FADD Z3.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z16.D, Z22.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z24.D, P7/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z24.D, P7/M, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z29.D, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z28.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z29.D, P7/M, Z29.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z28.D, P7/M, Z28.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FABS Z29.D, P7/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FABS Z28.D, P7/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z28.D, P7/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z22.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z5.D, P0/Z, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, P0/M, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z5.D}, P6, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X1, X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P6.D, X1, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 444808 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:56-89
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU loads are used in vector version.
80% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 112.68 to 30.00 cycles (3.76x speedup).

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 212 FP arithmetical operations:

92: addition or subtraction (20 inside FMA instructions)
88: multiply (20 inside FMA instructions)
28: divide
4: square root

The binary loop is loading 480 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.41 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	94
loop length	376
used w registers	0
used x registers	20
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	1.06

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	6.00	0.25	34.00	34.00	0.50	0.50	9.00	9.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	6.00	0.25	34.00	34.00	20.00	20.00	9.00	9.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	55.94-112.68
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	11.75
Dispatch	34.00
DIV/SQRT	55.94-112.68
Data deps.	0.00
Overall L1	55.94-112.68

Vectorization ratios

INT

all	78%
load	88%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

INT+FP

all	92%
load	88%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	80%

Vector efficiency ratios

INT

all	82%
load	91%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	65%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

INT+FP

all	93%
load	91%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	82%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 112.68 cycles. At this rate:

4% of peak load performance is reached (4.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 444808

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z24.D}, P6/Z, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P6/Z, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P6/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z29.D}, P6/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z4.D}, P6/Z, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P6/Z, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P6/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z22.D, Z5.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z7.D, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z0.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z16.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z17.D, Z2.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z23.D, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z18.D, Z0.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1RD {Z29.D}, P7/Z, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
LD1D {Z5.D}, P6/Z, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P6/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z20.D, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z19.D, Z3.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z26.D, Z7.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z25.D, Z22.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z3.D}, P6/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P6/Z, [X30, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P6/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z16.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1RD {Z24.D}, P7/Z, [X3, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FMLA Z16.D, P7/M, Z28.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z22.D, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z6.D, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGE P5.D, P7/Z, Z16.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIVR Z22.D, P7/M, Z22.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z27, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z27.D, P7/M, Z27.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z4, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z4.D, P7/M, Z4.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z27.D, P7/M, Z27.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z4.D, P7/M, Z4.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z0.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z17.D, Z7.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z0.D, P7/M, Z4.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FSUB Z1.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z17.D, P7/M, Z17.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z23.D, Z22.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FABS Z22.D, P7/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z22.D, P7/M, Z22.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z21.D, Z18.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FCMLT P3.D, P7/Z, Z17.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z19.D, Z21.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z25.D, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FCMGE P4.D, P7/Z, Z17.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z20.D, Z25.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z26.D, Z18.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z19.D, P7/M, Z20.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAXNM Z26.D, P7/M, Z26.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z23.D, P7/M, Z0.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z27, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z27.D, P7/M, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z26.D, P7/M, Z26.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMAXNM Z27.D, P7/M, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P14.D, P7/Z, Z26.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P1.D, P3/Z, Z27.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
NOR P0.B, P7/Z, P5.B, P14.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
AND P2.B, P4/Z, P0.B, P6.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P8.B, P1/Z, P0.B, P6.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
EOR P5.B, P7/Z, P2.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P0.B, P0/Z, P6.B, P6.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FNEG Z27.D, P5/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z0.D}, P0/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z4, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCPY Z4.D, P8/M, #-1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
FADD Z3.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z16.D, Z22.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z24.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z24.D, P7/M, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z24.D, P7/M, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z29.D, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z28.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z29.D, P7/M, Z29.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z28.D, P7/M, Z28.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FABS Z29.D, P7/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FABS Z28.D, P7/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z28.D, P7/M, Z28.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z22.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z5.D, P0/Z, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, P0/M, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z5.D}, P6, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X1, X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P6.D, X1, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 444808 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code