OV - exec - Loop 173

	Loop Id: 173	Module: exec	Source: generate_chunk_kernel.f90:130-137	Coverage: 0.03%

0x4254ac ADD	X1, X1, #1

0x4254b0 LDR	D18, [X10, X26,LSL #3]    [24]

0x4254b4 ADD	X0, X0, #1

0x4254b8 LDR	D19, [X16, X1,LSL #3]    [11]

0x4254bc FCMPE	D19, D18

0x4254c0 B.MI	425504

0x4254c4 LDR	X7, [SP, #272]    [12]

0x4254c8 LDR	D20, [X16, X0,LSL #3]    [11]

0x4254cc LDR	D21, [X7, X26,LSL #3]    [9]

0x4254d0 FCMPE	D20, D21

0x4254d4 B.GE	425504

0x4254d8 LDR	X5, [X25, #40]    [25]

0x4254dc LDR	X22, [SP, #264]    [12]

0x4254e0 LDR	D22, [X5, X18,LSL #3]    [15]

0x4254e4 LDR	D23, [X22, X26,LSL #3]    [21]

0x4254e8 FCMPE	D22, D23

0x4254ec B.MI	425504

0x4254f0 LDR	X13, [X25, #160]    [25]

0x4254f4 LDR	D24, [X5, X15,LSL #3]    [15]

0x4254f8 LDR	D25, [X13, X26,LSL #3]    [18]

0x4254fc FCMPE	D24, D25

0x425500 B.MI	4258e0

0x425504 ADD	X0, X0, #1

0x425508 ADD	X1, X1, #1

0x42550c CMP	W2, W0

0x425510 B.LE	425270

0x425514 LDR	D22, [X16, X1,LSL #3]    [11]

0x425518 LDR	D23, [X10, X26,LSL #3]    [24]

0x42551c FCMPE	D22, D23

0x425520 B.MI	4254ac

0x425524 LDR	X6, [SP, #272]    [12]

0x425528 LDR	D24, [X16, X0,LSL #3]    [11]

0x42552c LDR	D25, [X6, X26,LSL #3]    [7]

0x425530 FCMPE	D24, D25

0x425534 B.GE	4254ac

0x425538 LDR	X14, [X25, #40]    [25]

0x42553c LDR	X4, [SP, #264]    [12]

0x425540 LDR	D31, [X14, X18,LSL #3]    [28]

0x425544 LDR	D30, [X4, X26,LSL #3]    [13]

0x425548 FCMPE	D31, D30

0x42554c B.MI	4254ac

0x425550 LDR	X22, [X25, #160]    [25]

0x425554 LDR	D28, [X14, X15,LSL #3]    [28]

0x425558 LDR	D29, [X22, X26,LSL #3]    [23]

0x42555c FCMPE	D28, D29

0x425560 B.GE	4254ac

0x425564 LDP	X14, X6, [X25, #104]    [25]

0x425568 ADD	X13, X0, X8

0x42556c ADD	X5, X23, X0

0x425570 SBFM	X4, X24, #0, #31

0x425574 UBFM	X3, X26, #61, #31

0x425578 ADD	X9, X21, X0

0x42557c LDR	X7, [X25, #72]    [25]

0x425580 LDR	D6, [X6, X26,LSL #3]    [6]

0x425584 LDR	X22, [X25, #64]    [25]

0x425588 STR	D6, [X7, X13,LSL #3]    [19]

0x42558c LDR	D7, [X14, X26,LSL #3]    [27]

0x425590 LDR	X7, [X25, #120]    [25]

0x425594 STR	D7, [X22, X5,LSL #3]    [22]

0x425598 LDP	X13, X14, [SP, #304]    [12]

0x42559c LDR	D5, [X7, X3]    [10]

0x4255a0 MADD	X6, X4, X27, X14

0x4255a4 MADD	X4, X4, X28, X13

0x4255a8 LDR	X5, [X25, #128]    [25]

0x4255ac ADD	X22, X6, X0

0x4255b0 ADD	X13, X6, X1

0x4255b4 LDR	X6, [X25, #80]    [25]

0x4255b8 ADD	X14, X0, X4

0x4255bc ADD	X4, X1, X4

0x4255c0 STR	X4, [SP, #112]    [12]

0x4255c4 ADD	X4, X11, X0

0x4255c8 STR	D5, [X6, X4,LSL #3]    [5]

0x4255cc LDR	D4, [X5, X3]    [16]

0x4255d0 LDR	X4, [X25, #88]    [25]

0x4255d4 STR	D4, [X4, X9,LSL #3]    [2]

0x4255d8 ADD	X9, X11, X1

0x4255dc LDR	D3, [X7, X3]    [10]

0x4255e0 STR	D3, [X6, X9,LSL #3]    [5]

0x4255e4 ADD	X9, X1, X21

0x4255e8 LDR	D2, [X5, X3]    [16]

0x4255ec STR	D2, [X4, X9,LSL #3]    [2]

0x4255f0 LDR	D1, [X7, X3]    [10]

0x4255f4 STR	D1, [X6, X22,LSL #3]    [5]

0x4255f8 LDR	D0, [X5, X3]    [16]

0x4255fc STR	D0, [X4, X14,LSL #3]    [2]

0x425600 LDR	D16, [X7, X3]    [10]

0x425604 STR	D16, [X6, X13,LSL #3]    [5]

0x425608 LDR	D17, [X5, X3]    [16]

0x42560c LDR	X3, [SP, #112]    [12]

0x425610 STR	D17, [X4, X3,LSL #3]    [2]

0x425614 B	4254ac

0x4258e0 LDP	X22, X6, [X25, #104]    [25]

0x4258e4 ADD	X7, X0, X8

0x4258e8 ADD	X5, X23, X0

0x4258ec SBFM	X4, X24, #0, #31

0x4258f0 UBFM	X3, X26, #61, #31

0x4258f4 ADD	X9, X21, X0

0x4258f8 LDR	X14, [X25, #72]    [25]

0x4258fc LDR	D31, [X6, X26,LSL #3]    [4]

0x425900 LDR	X13, [X25, #64]    [25]

0x425904 STR	D31, [X14, X7,LSL #3]    [26]

0x425908 LDR	D30, [X22, X26,LSL #3]    [20]

0x42590c LDR	X7, [X25, #120]    [25]

0x425910 STR	D30, [X13, X5,LSL #3]    [17]

0x425914 LDP	X14, X22, [SP, #304]    [12]

0x425918 LDR	D28, [X7, X3]    [8]

0x42591c MADD	X6, X4, X27, X22

0x425920 MADD	X4, X4, X28, X14

0x425924 LDR	X5, [X25, #128]    [25]

0x425928 ADD	X22, X6, X0

0x42592c ADD	X13, X6, X1

0x425930 LDR	X6, [X25, #80]    [25]

0x425934 ADD	X14, X0, X4

0x425938 ADD	X4, X1, X4

0x42593c STR	X4, [SP, #112]    [12]

0x425940 ADD	X4, X11, X0

0x425944 STR	D28, [X6, X4,LSL #3]    [3]

0x425948 LDR	D29, [X5, X3]    [14]

0x42594c LDR	X4, [X25, #88]    [25]

0x425950 STR	D29, [X4, X9,LSL #3]    [1]

0x425954 ADD	X9, X11, X1

0x425958 LDR	D6, [X7, X3]    [8]

0x42595c STR	D6, [X6, X9,LSL #3]    [3]

0x425960 ADD	X9, X1, X21

0x425964 LDR	D7, [X5, X3]    [14]

0x425968 STR	D7, [X4, X9,LSL #3]    [1]

0x42596c LDR	D5, [X7, X3]    [8]

0x425970 STR	D5, [X6, X22,LSL #3]    [3]

0x425974 LDR	D4, [X5, X3]    [14]

0x425978 STR	D4, [X4, X14,LSL #3]    [1]

0x42597c LDR	D3, [X7, X3]    [8]

0x425980 STR	D3, [X6, X13,LSL #3]    [3]

0x425984 LDR	D2, [X5, X3]    [14]

0x425988 LDR	X3, [SP, #112]    [12]

0x42598c STR	D2, [X4, X3,LSL #3]    [1]

0x425990 B	425504

/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 130 - 137

--------------------------------------------------------------------------------

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►62.96+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec
►37.04+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

Coverage (%)	Name	Source Location	Module
►56.47+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►43.53+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►74.07+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►25.93+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►84.38+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►15.63+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►86.54+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►13.46+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►82.35+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►17.65+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►87.88+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.12+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►91.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►8.57+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►91.18+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►8.82+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

Coverage (%)	Name	Source Location	Module
►83.33+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►16.67+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.f90:41	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.73
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.65
Bottlenecks	P10, P11, P12,
Function	__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0
Source	generate_chunk_kernel.f90:130-137
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	18.67
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	5.92
Front-end cycles	17.00
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.25
P5 cycles	8.25
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	28.00
P11 cycles	28.00
P12 cycles	28.00
P13 cycles	1.00
P14 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	136.00
Nb uops	136.00
Nb loads	NA
Nb stores	22.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.81
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.61

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.73
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.65
Bottlenecks	P10, P11, P12,
Function	__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0
Source	generate_chunk_kernel.f90:130-137
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	18.67
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	5.92
Front-end cycles	17.00
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.25
P5 cycles	8.25
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	28.00
P11 cycles	28.00
P12 cycles	28.00
P13 cycles	1.00
P14 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	136.00
Nb uops	136.00
Nb loads	NA
Nb stores	22.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.81
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.61

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0
Source file and lines	generate_chunk_kernel.f90:130-137
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:130-137.

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=25
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 25 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.00 to 18.67 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 28.00 to 5.92 cycles (4.73x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	136
nb uops	136
loop length	544
used w registers	2
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	22
used q registers	0
used v registers	0
used z registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	8.25	8.25	8.25	8.25	14.00	14.00	0.00	0.00	28.00	28.00	28.00	1.00	1.00
cycles	5.50	5.50	8.25	8.25	8.25	8.25	14.00	14.00	0.00	0.00	28.00	28.00	28.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.00
Dispatch	28.00
Overall L1	28.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	24%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	24%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 425514

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D19, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 425504 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D20, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D21, [X7, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D20, D21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 425504 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X25, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X5, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D23, [X22, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D22, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 425504 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X25, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D24, [X5, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D25, [X13, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D24, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4258e0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 425270 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D22, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D23, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D22, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4254ac <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #272]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D24, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D25, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D24, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 4254ac <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X25, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D31, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D30, [X4, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D31, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4254ac <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X25, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D28, [X14, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D29, [X22, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D28, D29	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 4254ac <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X6, [X25, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X13, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X23, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X24, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X3, X26, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X25, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D6, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X22, [X25, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D6, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D7, [X14, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X7, [X25, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D7, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X13, X14, [SP, #304]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D5, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
MADD X6, X4, X27, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X4, X4, X28, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X5, [X25, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X22, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X25, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR D5, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D4, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X4, [X25, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D4, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D3, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X1, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D2, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D1, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D1, [X6, X22,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D0, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D16, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D16, [X6, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D17, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D17, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 4254ac <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X22, X6, [X25, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X7, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X23, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X24, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X3, X26, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X25, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D31, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X13, [X25, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D31, [X14, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D30, [X22, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X7, [X25, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D30, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X14, X22, [SP, #304]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D28, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
MADD X6, X4, X27, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X4, X4, X28, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X5, [X25, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X22, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X25, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR D28, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D29, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X4, [X25, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D29, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D6, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X1, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D7, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D5, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D5, [X6, X22,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D4, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D4, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D3, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D3, [X6, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D2, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D2, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 425504 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0
Source file and lines	generate_chunk_kernel.f90:130-137
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=25
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	136
nb uops	136
loop length	544
used w registers	2
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	22
used q registers	0
used v registers	0
used z registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	8.25	8.25	8.25	8.25	14.00	14.00	0.00	0.00	28.00	28.00	28.00	1.00	1.00
cycles	5.50	5.50	8.25	8.25	8.25	8.25	14.00	14.00	0.00	0.00	28.00	28.00	28.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.00
Dispatch	28.00
Overall L1	28.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	24%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	24%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 425514

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D19, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 425504 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D20, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D21, [X7, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D20, D21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 425504 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X25, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X5, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D23, [X22, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D22, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 425504 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X25, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D24, [X5, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D25, [X13, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D24, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4258e0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 425270 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D22, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D23, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D22, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4254ac <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #272]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D24, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D25, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D24, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 4254ac <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X25, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D31, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D30, [X4, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D31, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 4254ac <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X25, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D28, [X14, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D29, [X22, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D28, D29	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 4254ac <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X6, [X25, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X13, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X23, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X24, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X3, X26, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X25, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D6, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X22, [X25, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D6, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D7, [X14, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X7, [X25, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D7, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X13, X14, [SP, #304]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D5, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
MADD X6, X4, X27, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X4, X4, X28, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X5, [X25, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X22, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X25, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR D5, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D4, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X4, [X25, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D4, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D3, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X1, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D2, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D1, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D1, [X6, X22,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D0, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D16, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D16, [X6, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D17, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D17, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 4254ac <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X22, X6, [X25, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X7, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X23, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X4, X24, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X3, X26, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X25, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D31, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X13, [X25, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D31, [X14, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D30, [X22, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X7, [X25, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D30, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP X14, X22, [SP, #304]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D28, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
MADD X6, X4, X27, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MADD X4, X4, X28, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR X5, [X25, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X22, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X25, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR D28, [X6, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D29, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X4, [X25, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D29, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D6, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X9, X1, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D7, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D5, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D5, [X6, X22,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D4, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D4, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D3, [X7, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D3, [X6, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D2, [X5, X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D2, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 425504 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/multicore/gcc_5/oneview_run_1782340583OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	1	0	0.94	0	0.98	0	1.23	0	1.53	0	2.35	0	2.43	0	2.29	0	2.37	0	4.47	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.40500000119209	0.028955752030015
1x2	2	1	1.99	2	0.25499999523163	0.028721772134304
1x4	4	0.94	3.78	4	0.18500000238419	0.029483074322343
1x8	8	0.98	7.86	8	0.10499999672174	0.024479312822223
1x16	11	1.23	19.74	16	0.054999995976686	0.01271871291101
1x24	11	1.53	36.83	24	0.035000003874302	0.0072243460454047
1x32	7	2.35	75.12	32	0.029999999329448	0.0038274356629699
1x40	8	2.43	97.2	40	0.025000000372529	0.0031162218656391
1x48	10	2.29	109.97	48	0.02000000141561	0.0028077871538699
1x56	11	2.37	132.48	56	0.02000000141561	0.0023402806837112
1x64	6	4.47	286.29	64	0.015000000596046	0.0010810513049364

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency