OV - exec - Function setTemperature.omp

	Function: setTemperature.omp_outlined	Module: exec	Source: initAtoms.c:151-162	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 151 - 162

--------------------------------------------------------------------------------

151:    #pragma omp parallel for

152:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox)

153:    {

154:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

155:       {

156:          int iType = s->atoms->iSpecies[iOff];

157:          real_t mass = s->species[iType].mass;

158:          real_t sigma = sqrt(kB_eV * temperature/mass);

159:          uint64_t seed = mkSeed(s->atoms->gid[iOff], 123);

160:          s->atoms->p[iOff][0] = mass * sigma * gasdev(&seed);

161:          s->atoms->p[iOff][1] = mass * sigma * gasdev(&seed);

162:          s->atoms->p[iOff][2] = mass * sigma * gasdev(&seed);

0x4156b0 SUB	SP, SP, #144

0x4156b4 STR	D10, [SP, #32]

0x4156b8 STP	D9, D8, [SP, #48]

0x4156bc STP	X29, X30, [SP, #64]

0x4156c0 STP	X26, X25, [SP, #80]

0x4156c4 STP	X24, X23, [SP, #96]

0x4156c8 STP	X22, X21, [SP, #112]

0x4156cc STP	X20, X19, [SP, #128]

0x4156d0 ADD	X29, SP, #64

0x4156d4 LDR	X8, [X2]

0x4156d8 LDR	X8, [X8, #24]

0x4156dc LDR	W8, [X8, #12]

0x4156e0 SUBS	W22, W8, #1

0x4156e4 B.LT	415758

0x4156e8 LDR	W21, [X0]

0x4156ec ORR	X19, XZR, X3

0x4156f0 ORR	X20, XZR, X2

0x4156f4 MOVZ	W8, #1

0x4156f8 ADRP	X0,

0x4156fc ADD	X0, X0, #2712

0x415700 ADD	X3, SP, #24

0x415704 ORR	W1, WZR, W21

0x415708 SUB	X4, X29, #20

0x41570c SUB	X5, X29, #24

0x415710 ADD	X6, SP, #28

0x415714 MOVZ	W2, #34

0x415718 MOVZ	W7, #1

0x41571c STP	W22, WZR, [X29, #488]

0x415720 STP	WZR, W8, [SP, #24]

0x415724 STR	W8, [SP]

0x415728 BL	410220

0x41572c LDUR	W8, [X29, #488]

0x415730 CMP	W8, W22

0x415734 CSEL	W9, W8, W22, #11

0x415738 LDURSW	X22, [X29, #492]

0x41573c STUR	W9, [X29, #488]

0x415740 CMP	W22, W9

0x415744 B.LE	41577c

0x415748 ADRP	X0,

0x41574c ADD	X0, X0, #2736

0x415750 ORR	W1, WZR, W21

0x415754 BL	4100d0

0x415758 LDP	D9, D8, [SP, #48]

0x41575c LDR	D10, [SP, #32]

0x415760 LDP	X20, X19, [SP, #128]

0x415764 LDP	X22, X21, [SP, #112]

0x415768 LDP	X24, X23, [SP, #96]

0x41576c LDP	X26, X25, [SP, #80]

0x415770 LDP	X29, X30, [SP, #64]

0x415774 ADD	SP, SP, #144

0x415778 RET

0x41577c ADRP	X10,

0x415780 LDR	X8, [X20]

0x415784 UBFM	W23, W22, #26, #25

0x415788 LDR	D8, [X10, #3152]

0x41578c B	4157b0

0x415790 HINT	#0

0x415794 HINT	#0

0x415798 HINT	#0

0x41579c HINT	#0

(81) 0x4157a0 CMP	X22, W9,SXTW

(81) 0x4157a4 ADD	X22, X22, #1

(81) 0x4157a8 ADD	W23, W23, #64

(81) 0x4157ac B.GE	415748

(81) 0x4157b0 LDR	X10, [X8, #24]

(81) 0x4157b4 LDR	X10, [X10, #120]

(81) 0x4157b8 LDR	W10, [X10, X22,LSL #2]

(81) 0x4157bc CMP	W10, #1

(81) 0x4157c0 B.LT	4157a0

(81) 0x4157c4 SBFM	X9, X23, #0, #31

(81) 0x4157c8 SBFM	X25, X23, #62, #31

(81) 0x4157cc ORR	W24, WZR, WZR

(81) 0x4157d0 ADD	X9, X9, W23,SXTW #1

(81) 0x4157d4 UBFM	X26, X9, #61, #60

(81) 0x4157d8 LDR	X9, [X8, #32]

(81) 0x4157dc HINT	#0

  (82) 0x4157e0 LDP	X9, X10, [X9, #8]

  (82) 0x4157e4 LDR	X8, [X8, #40]

  (82) 0x4157e8 MOVZ	W1, #123

  (82) 0x4157ec LDR	D0, [X19]

  (82) 0x4157f0 FMUL	D0, D0, D8

  (82) 0x4157f4 LDRSW	X10, [X10, X25]

  (82) 0x4157f8 LDR	W0, [X9, X25]

  (82) 0x4157fc ADD	X8, X8, X10,LSL #4

  (82) 0x415800 LDR	D9, [X8, #8]

  (82) 0x415804 FDIV	D0, D0, D9

  (82) 0x415808 FSQRT	D10, D0

  (82) 0x41580c BL	418f30

  (82) 0x415810 STR	X0, [SP, #16]

  (82) 0x415814 ADD	X0, SP, #16

  (82) 0x415818 FMUL	D9, D9, D10

  (82) 0x41581c BL	418e20

  (82) 0x415820 LDR	X8, [X20]

  (82) 0x415824 FMUL	D0, D9, D0

  (82) 0x415828 ADD	X0, SP, #16

  (82) 0x41582c LDR	X8, [X8, #32]

  (82) 0x415830 LDR	X8, [X8, #32]

  (82) 0x415834 STR	D0, [X8, X26]

  (82) 0x415838 BL	418e20

  (82) 0x41583c LDR	X8, [X20]

  (82) 0x415840 FMUL	D0, D9, D0

  (82) 0x415844 ADD	X0, SP, #16

  (82) 0x415848 LDR	X8, [X8, #32]

  (82) 0x41584c LDR	X8, [X8, #32]

  (82) 0x415850 ADD	X8, X8, X26

  (82) 0x415854 STR	D0, [X8, #8]

  (82) 0x415858 BL	418e20

  (82) 0x41585c LDR	X8, [X20]

  (82) 0x415860 FMUL	D0, D9, D0

  (82) 0x415864 ADD	W24, W24, #1

  (82) 0x415868 ADD	X25, X25, #4

  (82) 0x41586c LDP	X10, X9, [X8, #24]

  (82) 0x415870 LDR	X10, [X10, #120]

  (82) 0x415874 LDR	X11, [X9, #32]

  (82) 0x415878 LDR	W10, [X10, X22,LSL #2]

  (82) 0x41587c ADD	X11, X11, X26

  (82) 0x415880 ADD	X26, X26, #24

  (82) 0x415884 STR	D0, [X11, #16]

  (82) 0x415888 CMP	W24, W10

  (82) 0x41588c B.LT	4157e0

(81) 0x415890 LDUR	W9, [X29, #488]

(81) 0x415894 B	4157a0

0x415898 HINT	#0

0x41589c HINT	#0

Coverage (%)	Name	Module
►100.00+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	initAtoms.c:151-162
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:151-162.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.83 to 1.67 cycles (5.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 8.83 to 2.54 cycles (3.48x speedup).

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

12% of VPU loads are used in vector version.
9% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:151
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:151

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	62
nb uops	56
loop length	248
used w registers	9
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.50	6.50	6.50	6.50	1.00	1.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50
cycles	3.00	3.00	6.50	6.50	6.50	6.50	1.00	1.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.00
Dispatch	8.83
Overall L1	8.83

Vectorization ratios

all	6%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	34%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.83 cycles. At this rate:

1% of peak load performance is reached (1.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4156b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W22, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 415758 <setTemperature.omp_outlined+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <43f6f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2712	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X29, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP W22, WZR, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP WZR, W8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410220 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W9, W8, W22, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDURSW X22, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STUR W9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W22, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 41577c <setTemperature.omp_outlined+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <43f748>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2736	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X10, <42177c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM W23, W22, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D8, [X10, #3152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 4157b0 <setTemperature.omp_outlined+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	initAtoms.c:151-162
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:151-162.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.83 to 1.67 cycles (5.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

12% of VPU loads are used in vector version.
9% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:151
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:151

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	62
nb uops	56
loop length	248
used w registers	9
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.50	6.50	6.50	6.50	1.00	1.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50
cycles	3.00	3.00	6.50	6.50	6.50	6.50	1.00	1.00	0.00	0.00	8.83	8.50	8.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.00
Dispatch	8.83
Overall L1	8.83

Vectorization ratios

all	6%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	34%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.83 cycles. At this rate:

1% of peak load performance is reached (1.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4156b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W22, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 415758 <setTemperature.omp_outlined+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <43f6f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2712	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X4, X29, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP W22, WZR, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP WZR, W8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410220 <@plt_start@+0x200>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W9, W8, W22, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDURSW X22, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STUR W9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W22, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 41577c <setTemperature.omp_outlined+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <43f748>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2736	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4100d0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X10, <42177c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM W23, W22, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D8, [X10, #3152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 4157b0 <setTemperature.omp_outlined+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼setTemperature.omp_outlined–	0.01	0.00
▼Loop 81 - initAtoms.c:152-162 - exec–	0.00	0.00
○Loop 82 - initAtoms.c:154-162 - exec	0.01	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code