OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:209-385 [...]	Coverage (incl. loops): 0.34% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 209 - 385

--------------------------------------------------------------------------------

209:    if (iz == gridSize[2])

210:    {

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x4166c0 STP	X29, X30, [SP, #976]!

0x4166c4 STP	X22, X21, [SP, #16]

0x4166c8 STP	X20, X19, [SP, #32]

0x4166cc ADD	X29, SP, #0

0x4166d0 LDR	W12, [X0, #12]

0x4166d4 LDR	W8, [X0, #20]

0x4166d8 CMP	W12, W8

0x4166dc B.GE	416700

0x4166e0 LDR	X9, [X0, #120]

0x4166e4 SBFM	X8, X12, #0, #31

(95) 0x4166e8 STR	WZR, [X9, X8,LSL #2]

(95) 0x4166ec ADD	X8, X8, #1

(95) 0x4166f0 LDRSW	X10, [X0, #20]

(95) 0x4166f4 CMP	X8, X10

(95) 0x4166f8 B.LT	4166e8

0x4166fc LDR	W12, [X0, #12]

0x416700 CMP	W12, #1

0x416704 B.LT	416a68

0x416708 LDR	X14, [X0, #120]

0x41670c MOVZ	W9, #24

0x416710 ORR	X8, XZR, XZR

0x416714 B	41672c

0x416718 HINT	#0

0x41671c HINT	#0

    (92) 0x416720 ADD	X8, X8, #1

    (92) 0x416724 CMP	X8, W12,SXTW

    (92) 0x416728 B.GE	416a68

    (92) 0x41672c LDR	W10, [X14, X8,LSL #2]

    (92) 0x416730 CMP	W10, #1

    (92) 0x416734 B.LT	416720

  (94) 0x416738 UBFM	X11, X8, #58, #57

  (94) 0x41673c ORR	W10, WZR, WZR

  (94) 0x416740 ORR	W15, WZR, W12

  (94) 0x416744 ORR	W16, WZR, W12

  (94) 0x416748 ORR	W2, WZR, W12

  (94) 0x41674c B	416774

0x416750 HINT	#0

0x416754 HINT	#0

0x416758 HINT	#0

0x41675c HINT	#0

  (94) 0x416760 ADD	W10, W10, #1

  (94) 0x416764 LDR	X14, [X0, #120]

  (94) 0x416768 LDR	W13, [X14, X8,LSL #2]

  (94) 0x41676c CMP	W10, W13

  (94) 0x416770 B.GE	416720

  (94) 0x416774 LDR	X17, [X1, #24]

  (94) 0x416778 ADD	X13, X11, W10,SXTW

  (94) 0x41677c LDR	D1, [X0, #48]

  (94) 0x416780 MADD	X18, X13, X9, X17

  (94) 0x416784 LDR	D0, [X18]

  (94) 0x416788 FCMP	D0, D1

  (94) 0x41678c B.PL	4167c0

  (94) 0x416790 LDR	D1, [X0, #24]

  (94) 0x416794 LDR	W4, [X0]

  (94) 0x416798 SUB	W5, W4, #1

  (94) 0x41679c FSUB	D0, D0, S1

  (94) 0x4167a0 LDR	D1, [X0, #96]

  (94) 0x4167a4 FMUL	D0, D0, D1

  (94) 0x4167a8 FCVTMS	W3, D0

  (94) 0x4167ac CMP	W4, W3

  (94) 0x4167b0 CSEL	W3, W5, W3, #0

  (94) 0x4167b4 B	4167c8

0x4167b8 HINT	#0

0x4167bc HINT	#0

(93) 0x4167c0 LDR	W4, [X0]

(93) 0x4167c4 ORR	W3, WZR, W4

  (94) 0x4167c8 LDP	D0, D2, [X18, #8]

  (94) 0x4167cc LDP	D1, D3, [X0, #32]

  (94) 0x4167d0 LDP	D4, D5, [X0, #104]

  (94) 0x4167d4 FSUB	D3, D2, S3

  (94) 0x4167d8 FMUL	D3, D3, D5

  (94) 0x4167dc LDP	W5, W6, [X0, #4]

  (94) 0x4167e0 SUB	W21, W6, #1

  (94) 0x4167e4 SUB	W20, W5, #1

  (94) 0x4167e8 FCVTMS	W19, D3

  (94) 0x4167ec FSUB	D1, D0, S1

  (94) 0x4167f0 FMUL	D1, D1, D4

  (94) 0x4167f4 FCVTMS	W7, D1

  (94) 0x4167f8 LDP	D1, D3, [X0, #56]

  (94) 0x4167fc CMP	W5, W7

  (94) 0x416800 CSEL	W7, W20, W7, #0

  (94) 0x416804 FCMP	D0, D1

  (94) 0x416808 CSEL	W20, W5, W7, #5

  (94) 0x41680c CMP	W6, W19

  (94) 0x416810 CSEL	W19, W21, W19, #0

  (94) 0x416814 FCMP	D2, D3

  (94) 0x416818 B.MI	416840

  (94) 0x41681c UBFM	W15, W6, #31, #30

  (94) 0x416820 ADD	W2, W5, W20

  (94) 0x416824 ADD	W16, W4, #2

  (94) 0x416828 MADD	W15, W15, W5, W3

  (94) 0x41682c ADD	W2, W2, W6,LSL #1

  (94) 0x416830 ADD	W2, W2, #3

  (94) 0x416834 ADD	W15, W15, W12

  (94) 0x416838 MADD	W15, W16, W2, W15

  (94) 0x41683c B	4168dc

  (94) 0x416840 CMN	W19, #1

  (94) 0x416844 B.EQ	4168c0

  (94) 0x416848 MADD	W20, W19, W5, W7

  (94) 0x41684c CMN	W3, #1

  (94) 0x416850 MADD	W21, W4, W20, W3

  (94) 0x416854 ADD	W20, W20, W2

  (94) 0x416858 CSEL	W20, W21, W20, #1

  (94) 0x41685c ADD	W21, W19, W6

  (94) 0x416860 CMP	W3, W4

  (94) 0x416864 CSEL	W2, W2, W16, #1

  (94) 0x416868 ADD	W4, W4, #2

  (94) 0x41686c MADD	W22, W21, W5, W7

  (94) 0x416870 ADD	W22, W22, W16

  (94) 0x416874 CSEL	W20, W20, W22, #1

  (94) 0x416878 MUL	W22, W5, W6

  (94) 0x41687c MUL	W5, W6, W5

  (94) 0x416880 CMN	W7, #1

  (94) 0x416884 CSEL	W16, W16, W15, #1

  (94) 0x416888 CSEL	W2, W2, W15, #1

  (94) 0x41688c ADD	W22, W3, W22,LSL #1

  (94) 0x416890 ADD	W3, W3, W5,LSL #1

  (94) 0x416894 ADD	W22, W22, W15

  (94) 0x416898 ADD	W3, W3, W12

  (94) 0x41689c MADD	W19, W4, W19, W22

  (94) 0x4168a0 MADD	W3, W4, W21, W3

  (94) 0x4168a4 CSINC	W7, W20, W19, #1

  (94) 0x4168a8 FCMP	D0, D1

  (94) 0x4168ac CSEL	W15, W15, W12, #4

  (94) 0x4168b0 CSEL	W16, W16, W12, #4

  (94) 0x4168b4 CSEL	W2, W2, W12, #4

  (94) 0x4168b8 CSINC	W3, W7, W3, #4

  (94) 0x4168bc B	4168ec

  (94) 0x4168c0 UBFM	W15, W6, #31, #30

  (94) 0x4168c4 ADD	W16, W4, #2

  (94) 0x4168c8 ADD	W2, W20, W6,LSL #1

  (94) 0x4168cc MADD	W15, W15, W5, W3

  (94) 0x4168d0 MADD	W16, W16, W2, W16

  (94) 0x4168d4 ADD	W15, W15, W12

  (94) 0x4168d8 ADD	W15, W15, W16

  (94) 0x4168dc ADD	W3, W15, #1

  (94) 0x4168e0 ORR	W15, WZR, W12

  (94) 0x4168e4 ORR	W16, WZR, W12

  (94) 0x4168e8 ORR	W2, WZR, W12

  (94) 0x4168ec TBNZ	W3, #31, 416a78

  (94) 0x4168f0 LDR	W4, [X0, #20]

  (94) 0x4168f4 CMP	W3, W4

  (94) 0x4168f8 B.GE	416a98

  (94) 0x4168fc ORR	W4, WZR, W3

  (94) 0x416900 CMP	X8, X4

  (94) 0x416904 B.EQ	416760

  (94) 0x416908 LDR	W12, [X14, X4,LSL #2]

  (94) 0x41690c LDP	X14, X15, [X1, #8]

  (94) 0x416910 ADD	W12, W12, W3,LSL #6

  (94) 0x416914 LDR	W16, [X14, X13,LSL #2]

  (94) 0x416918 STR	W16, [X14, W12,SXTW #2]

  (94) 0x41691c SBFM	X14, X12, #0, #31

  (94) 0x416920 LDR	W16, [X15, X13,LSL #2]

  (94) 0x416924 ADD	X14, X14, W12,SXTW #1

  (94) 0x416928 STR	W16, [X15, W12,SXTW #2]

  (94) 0x41692c ADD	X15, X17, X14,LSL #3

  (94) 0x416930 ADD	X17, X13, X13,LSL #1

  (94) 0x416934 LDR	Q0, [X18]

  (94) 0x416938 LDR	X16, [X18, #16]

  (94) 0x41693c STR	X16, [X15, #16]

  (94) 0x416940 STR	Q0, [X15]

  (94) 0x416944 LDR	X15, [X1, #32]

  (94) 0x416948 ADD	X16, X15, X14,LSL #3

  (94) 0x41694c ADD	X15, X15, X17,LSL #3

  (94) 0x416950 LDR	Q0, [X15]

  (94) 0x416954 LDR	X15, [X15, #16]

  (94) 0x416958 STR	X15, [X16, #16]

  (94) 0x41695c STR	Q0, [X16]

  (94) 0x416960 LDR	X15, [X1, #40]

  (94) 0x416964 ADD	X14, X15, X14,LSL #3

  (94) 0x416968 ADD	X15, X15, X17,LSL #3

  (94) 0x41696c LDR	Q0, [X15]

  (94) 0x416970 LDR	X15, [X15, #16]

  (94) 0x416974 STR	X15, [X14, #16]

  (94) 0x416978 STR	Q0, [X14]

  (94) 0x41697c LDR	X14, [X1, #48]

  (94) 0x416980 LDR	X15, [X14, X13,LSL #3]

  (94) 0x416984 STR	X15, [X14, W12,SXTW #3]

  (94) 0x416988 LDR	X12, [X0, #120]

  (94) 0x41698c LDR	W14, [X12, X4,LSL #2]

  (94) 0x416990 ADD	W15, W14, #1

  (94) 0x416994 CMP	W14, #63

  (94) 0x416998 STR	W15, [X12, X4,LSL #2]

  (94) 0x41699c B.GE	416ab8

  (94) 0x4169a0 LDRSW	X14, [X12, X8,LSL #2]

  (94) 0x4169a4 SUB	X14, X14, #1

  (94) 0x4169a8 STR	W14, [X12, X8,LSL #2]

  (94) 0x4169ac CBZ	W14, 416a30

  (94) 0x4169b0 ADD	X12, X11, X14

  (94) 0x4169b4 LDP	X14, X15, [X1, #8]

  (94) 0x4169b8 ADD	X17, X12, X12,LSL #1

  (94) 0x4169bc LDR	W16, [X14, X12,LSL #2]

  (94) 0x4169c0 STR	W16, [X14, X13,LSL #2]

  (94) 0x4169c4 LDR	W14, [X15, X12,LSL #2]

  (94) 0x4169c8 STR	W14, [X15, X13,LSL #2]

  (94) 0x4169cc LDR	X14, [X1, #24]

  (94) 0x4169d0 ADD	X15, X13, X13,LSL #1

  (94) 0x4169d4 ADD	X16, X14, X15,LSL #3

  (94) 0x4169d8 ADD	X14, X14, X17,LSL #3

  (94) 0x4169dc LDR	Q0, [X14]

  (94) 0x4169e0 LDR	X14, [X14, #16]

  (94) 0x4169e4 STR	X14, [X16, #16]

  (94) 0x4169e8 STR	Q0, [X16]

  (94) 0x4169ec LDR	X14, [X1, #32]

  (94) 0x4169f0 ADD	X16, X14, X15,LSL #3

  (94) 0x4169f4 ADD	X14, X14, X17,LSL #3

  (94) 0x4169f8 LDR	Q0, [X14]

  (94) 0x4169fc LDR	X14, [X14, #16]

  (94) 0x416a00 STR	X14, [X16, #16]

  (94) 0x416a04 STR	Q0, [X16]

  (94) 0x416a08 LDR	X14, [X1, #40]

  (94) 0x416a0c ADD	X15, X14, X15,LSL #3

  (94) 0x416a10 ADD	X14, X14, X17,LSL #3

  (94) 0x416a14 LDR	Q0, [X14]

  (94) 0x416a18 LDR	X14, [X14, #16]

  (94) 0x416a1c STR	X14, [X15, #16]

  (94) 0x416a20 STR	Q0, [X15]

  (94) 0x416a24 LDR	X14, [X1, #48]

  (94) 0x416a28 LDR	X12, [X14, X12,LSL #3]

  (94) 0x416a2c STR	X12, [X14, X13,LSL #3]

  (94) 0x416a30 LDR	W12, [X0, #12]

  (94) 0x416a34 CMP	W3, W12

  (94) 0x416a38 B.LE	416a48

  (94) 0x416a3c LDR	W13, [X1]

  (94) 0x416a40 SUB	W13, W13, #1

  (94) 0x416a44 STR	W13, [X1]

  (94) 0x416a48 ORR	W15, WZR, W12

  (94) 0x416a4c ORR	W16, WZR, W12

  (94) 0x416a50 ORR	W2, WZR, W12

  (94) 0x416a54 LDR	X14, [X0, #120]

  (94) 0x416a58 LDR	W13, [X14, X8,LSL #2]

  (94) 0x416a5c CMP	W10, W13

  (94) 0x416a60 B.LT	416774

  (94) 0x416a64 B	416720

0x416a68 LDP	X20, X19, [SP, #32]

0x416a6c LDP	X22, X21, [SP, #16]

0x416a70 LDP	X29, X30, [SP], #48

0x416a74 RET

0x416a78 ADRP	X0,

0x416a7c ADD	X0, X0, #3732

0x416a80 ADRP	X1,

0x416a84 ADD	X1, X1, #3517

0x416a88 ADRP	X3,

0x416a8c ADD	X3, X3, #3742

0x416a90 MOVZ	W2, #246

0x416a94 BL	4101d0

0x416a98 ADRP	X0,

0x416a9c ADD	X0, X0, #3789

0x416aa0 ADRP	X1,

0x416aa4 ADD	X1, X1, #3517

0x416aa8 ADRP	X3,

0x416aac ADD	X3, X3, #3742

0x416ab0 MOVZ	W2, #247

0x416ab4 BL	4101d0

0x416ab8 ADRP	X0,

0x416abc ADD	X0, X0, #3815

0x416ac0 ADRP	X1,

0x416ac4 ADD	X1, X1, #3517

0x416ac8 ADRP	X3,

0x416acc ADD	X3, X3, #3846

0x416ad0 MOVZ	W2, #262

0x416ad4 BL	4101d0

0x416ad8 HINT	#0

0x416adc HINT	#0

Coverage (%)	Name	Source Location	Module
►99.05+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	eam.c:831	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:209-385
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:209-247,258-269,288-304,327-334,352-365,371,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.75 to 5.69 cycles (1.36x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes.

General properties

nb instructions	55
nb uops	45
loop length	220
used w registers	4
used x registers	14
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.63 cycles
front end	5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	3.50	3.50	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Dispatch	7.75
Overall L1	7.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	29%
load	29%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.75 cycles. At this rate:

1% of peak load performance is reached (1.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4166c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W12, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W12, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 416700 <updateLinkCells+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X8, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDR W12, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 416a68 <updateLinkCells+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W9, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 41672c <updateLinkCells+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <420a78>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3732	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X1, <420a80>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #3517	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X3, <420a88>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #3742	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #246	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101d0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <420a98>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3789	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X1, <420aa0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #3517	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X3, <420aa8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #3742	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #247	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101d0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <420ab8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3815	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X1, <420ac0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #3517	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X3, <420ac8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #3846	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #262	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101d0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:209-385
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes.

General properties

nb instructions	55
nb uops	45
loop length	220
used w registers	4
used x registers	14
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.63 cycles
front end	5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	3.50	3.50	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Dispatch	7.75
Overall L1	7.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	29%
load	29%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.75 cycles. At this rate:

1% of peak load performance is reached (1.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4166c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W12, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W12, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 416700 <updateLinkCells+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X8, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDR W12, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 416a68 <updateLinkCells+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W9, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 41672c <updateLinkCells+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <420a78>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3732	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X1, <420a80>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #3517	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X3, <420a88>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #3742	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #246	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101d0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <420a98>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3789	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X1, <420aa0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #3517	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X3, <420aa8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #3742	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #247	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101d0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <420ab8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3815	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X1, <420ac0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #3517	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X3, <420ac8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #3846	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #262	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101d0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.34	0.07
▼Loop 93 - linkCells.c:209-371 - exec–	0.00	0.00
▼Loop 94 - linkCells.c:209-371 - exec–	0.34	4.20
○Loop 92 - linkCells.c:291-295 - exec	0.00	0.02
○Loop 95 - linkCells.c:384-385 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code