OV - exec - Loop 104

0x417180 ADD	X18, X18, #1

0x417184 CMP	X18, X9

0x417188 B.EQ	417140

0x41718c LDR	W1, [X17, X18,LSL #2]

0x417190 TBNZ	W1, #31, 417380

0x417194 LDR	W2, [X12, X1,LSL #2]

0x417198 CMP	W2, #0

0x41719c B.LE	417180

0x4171a0 LDR	X3, [X11, #32]

0x4171a4 UBFM	W1, W1, #26, #25

0x4171a8 ORR	X6, XZR, X16

0x4171ac ADD	W2, W2, W1

0x4171b0 LDR	X4, [X3, #24]

0x4171b4 UMADDL	X5, W1, W15, X4

0x4171b8 ADD	X5, X5, #16

0x4171bc B	4171cc

  (105) 0x4171c0 ADD	X6, X6, #1

  (105) 0x4171c4 CMP	X6, X0

  (105) 0x4171c8 B.GE	417180

  (105) 0x4171cc MADD	X7, X6, X15, X4

  (105) 0x4171d0 ORR	W24, WZR, W1

  (105) 0x4171d4 ORR	X25, XZR, X5

  (105) 0x4171d8 B	4171f0

    (106) 0x4171e0 ADD	W24, W24, #1

    (106) 0x4171e4 ADD	X25, X25, #24

    (106) 0x4171e8 CMP	W2, W24

    (106) 0x4171ec B.LE	4171c0

    (106) 0x4171f0 LDR	Q16, [X7]

    (106) 0x4171f4 LDUR	Q17, [X25, #496]

    (106) 0x4171f8 LDR	D19, [X25]

    (106) 0x4171fc FSUB	V16.2D, V16.2D, V17.2D

    (106) 0x417200 FMADD	D18, D16, D16, D0

    (106) 0x417204 MOV	D17, V16.D[1]

    (106) 0x417208 FMLA	D18, D17, V16.D[1]

    (106) 0x41720c LDR	D17, [X7, #16]

    (106) 0x417210 FSUB	D17, D17, S19

    (106) 0x417214 LDR	D19, [X23]

    (106) 0x417218 FMADD	D18, D17, D17, D18

    (106) 0x41721c FCMP	D18, #0

    (106) 0x417220 FCCMP	D18, D19, #2, #12

    (106) 0x417224 B.HI	4171e0

    (106) 0x417228 FDIV	D18, D1, D18

    (106) 0x41722c LDR	D19, [X22]

    (106) 0x417230 LDR	D21, [X21]

    (106) 0x417234 LDP	X27, X26, [X3, #40]

    (106) 0x417238 FMUL	D20, D18, D18

    (106) 0x41723c FMUL	D20, D18, D20

    (106) 0x417240 FMUL	D19, D20, D19

    (106) 0x417244 FADD	D20, D19, D2

    (106) 0x417248 FNMSUB	D20, D19, D20, D21

    (106) 0x41724c LDR	D21, [X26, X6,LSL #3]

    (106) 0x417250 FMADD	D7, D20, D3, D7

    (106) 0x417254 FMADD	D21, D20, D3, D21

    (106) 0x417258 STR	D21, [X26, X6,LSL #3]

    (106) 0x41725c MADD	X26, X6, X15, X27

    (106) 0x417260 STR	D7, [SP, #16]

    (106) 0x417264 LDR	D20, [X10]

    (106) 0x417268 FMUL	D20, D20, D4

    (106) 0x41726c FMUL	D20, D19, D20

    (106) 0x417270 FMADD	D19, D19, D6, D5

    (106) 0x417274 FMUL	D18, D18, D20

    (106) 0x417278 FMUL	D18, D19, D18

    (106) 0x41727c LDR	Q19, [X26]

    (106) 0x417280 FMLS	V19.2D, V16.2D, V18.D[0]

    (106) 0x417284 LDR	D16, [X26, #16]

    (106) 0x417288 STR	Q19, [X26]

    (106) 0x41728c FMSUB	D16, D17, D18, D16

    (106) 0x417290 STR	D16, [X26, #16]

    (106) 0x417294 B	4171e0

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216

--------------------------------------------------------------------------------

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Module
►99.05+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	micro-operation queue, P0, P1, P2, P3, P4, P5,
Function	ljForce.omp_outlined.2
Source	ljForce.c:178-184,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.31
Front-end cycles	2.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	1.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.00
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	micro-operation queue, P0, P1, P2, P3, P4, P5,
Function	ljForce.omp_outlined.2
Source	ljForce.c:178-184,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.31
Front-end cycles	2.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	1.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.00
Bytes prefetched	0.00
Bytes loaded	6.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.omp_outlined.2
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.31 cycles (6.40x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 6 bytes.

General properties

nb instructions	16
nb uops	16
loop length	64
used w registers	3
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.00
Dispatch	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	18%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

3% of peak load performance is reached (3.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.33 cycles (1.50x speedup).

ASM code

In the binary file, the address of the loop is: 41718c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CMP X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 417140 <ljForce.omp_outlined.2+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X17, X18,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
TBNZ W1, #31, 417380 <ljForce.omp_outlined.2+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR W2, [X12, X1,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
CMP W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.LE 417180 <ljForce.omp_outlined.2+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X11, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
UBFM W1, W1, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ORR X6, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD W2, W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
LDR X4, [X3, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
UMADDL X5, W1, W15, X4	1	0	0	0	0	1	0	0	0	0	2	1	N/A
ADD X5, X5, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B 4171cc <ljForce.omp_outlined.2+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	ljForce.omp_outlined.2
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.31 cycles (6.40x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 6 bytes.

General properties

nb instructions	16
nb uops	16
loop length	64
used w registers	3
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.00
Dispatch	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	18%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

3% of peak load performance is reached (3.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.33 cycles (1.50x speedup).

ASM code

In the binary file, the address of the loop is: 41718c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CMP X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 417140 <ljForce.omp_outlined.2+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X17, X18,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
TBNZ W1, #31, 417380 <ljForce.omp_outlined.2+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR W2, [X12, X1,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
CMP W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.LE 417180 <ljForce.omp_outlined.2+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X11, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
UBFM W1, W1, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ORR X6, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD W2, W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
LDR X4, [X3, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
UMADDL X5, W1, W15, X4	1	0	0	0	0	1	0	0	0	0	2	1	N/A
ADD X5, X5, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B 4171cc <ljForce.omp_outlined.2+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code