OV - exec - Loop 113

	Loop Id: 113	Module: exec	Source: timestep.c:74-78	Coverage: 1.00%

0x41958c LDP	Q3, Q1, [X1, #16]    [2]

0x419590 LDR	Q2, [X1], #48    [2]

0x419594 SUBS	X2, X2, #2

0x419598 EXT	V4.16B, V2.16B, V1.16B, #8

0x41959c MOV	V2.D[1], V3.D[1]

0x4195a0 MOV	V3.D[1], V1.D[1]

0x4195a4 LDP	Q16, Q1, [X0, #16]    [1]

0x4195a8 LDR	Q5, [X0]    [1]

0x4195ac ORR	V7.16B, V16.16B, V16.16B

0x4195b0 MOV	V7.D[1], V1.D[1]

0x4195b4 FMLA	V7.2D, V3.2D, V0.D[0]

0x4195b8 EXT	V6.16B, V5.16B, V1.16B, #8

0x4195bc MOV	V5.D[1], V16.D[1]

0x4195c0 FMLA	V6.2D, V4.2D, V0.2D

0x4195c4 FMLA	V5.2D, V2.2D, V0.2D

0x4195c8 ST3	{V5.2D, V6.2D, V7.2D}, [X0], #48    [1]

0x4195cc B.NE	41958c

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 78

--------------------------------------------------------------------------------

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Source Location	Module
►97.85+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.15+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	timestep	timestep.c:39	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	eam.c:831	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.57
CQA speedup if fully vectorized	1.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P6, P7, P8, P9,
Function	advanceVelocity.omp_outlined
Source	timestep.c:74-78
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	1.75
CQA cycles if fully vectorized	2.00
Front-end cycles	2.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	1.83
P11 cycles	1.50
P12 cycles	1.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	4.36
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	6.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	73.33
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	42.86
Vector-efficiency ratio all	53.33
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	35.71

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.57
CQA speedup if fully vectorized	1.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P6, P7, P8, P9,
Function	advanceVelocity.omp_outlined
Source	timestep.c:74-78
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	1.75
CQA cycles if fully vectorized	2.00
Front-end cycles	2.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	1.83
P11 cycles	1.50
P12 cycles	1.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	4.36
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	6.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	73.33
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	42.86
Vector-efficiency ratio all	53.33
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	35.71

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity.omp_outlined
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 53% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.75 to 2.00 cycles (1.38x speedup).

Details

73% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	17
nb uops	17
loop length	68
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	5
used v registers	9
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.13 cycles
front end	2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	2.75	2.75	2.75	2.75	1.83	1.50	1.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	2.75	2.75	2.75	2.75	1.83	1.50	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.13
Dispatch	2.75
Data deps.	1.00
Overall L1	2.75

Vectorization ratios

INT

all	66%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	73%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

Vector efficiency ratios

INT

all	54%
load	75%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	53%
load	75%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41958c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDP Q3, Q1, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR Q2, [X1], #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
SUBS X2, X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
EXT V4.16B, V2.16B, V1.16B, #8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV V2.D[1], V3.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOV V3.D[1], V1.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDP Q16, Q1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR Q5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ORR V7.16B, V16.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV V7.D[1], V1.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMLA V7.2D, V3.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
EXT V6.16B, V5.16B, V1.16B, #8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV V5.D[1], V16.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMLA V6.2D, V4.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V5.2D, V2.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
ST3 {V5.2D, V6.2D, V7.2D}, [X0], #48	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	5	1.50	vect (100.0%)
B.NE 41958c <advanceVelocity.omp_outlined+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advanceVelocity.omp_outlined
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

73% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	17
nb uops	17
loop length	68
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	5
used v registers	9
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.13 cycles
front end	2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	2.75	2.75	2.75	2.75	1.83	1.50	1.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	2.75	2.75	2.75	2.75	1.83	1.50	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.13
Dispatch	2.75
Data deps.	1.00
Overall L1	2.75

Vectorization ratios

INT

all	66%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	73%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

Vector efficiency ratios

INT

all	54%
load	75%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	53%
load	75%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41958c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDP Q3, Q1, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR Q2, [X1], #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
SUBS X2, X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
EXT V4.16B, V2.16B, V1.16B, #8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV V2.D[1], V3.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOV V3.D[1], V1.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDP Q16, Q1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR Q5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ORR V7.16B, V16.16B, V16.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV V7.D[1], V1.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMLA V7.2D, V3.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
EXT V6.16B, V5.16B, V1.16B, #8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOV V5.D[1], V16.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMLA V6.2D, V4.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V5.2D, V2.2D, V0.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
ST3 {V5.2D, V6.2D, V7.2D}, [X0], #48	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	5	1.50	vect (100.0%)
B.NE 41958c <advanceVelocity.omp_outlined+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code