OV - exec - Function loadAtomsBuffer

	Function: loadAtomsBuffer	Module: exec	Source: haloExchange.c:365-394	Coverage (incl. loops): 0.08% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 365 - 394

--------------------------------------------------------------------------------

365:    AtomMsg* buf = (AtomMsg*) charBuf;

366:

367:    real_t* pbcFactor = parms->pbcFactor[face];

368:    real3 shift;

369:    shift[0] = pbcFactor[0] * s->domain->globalExtent[0];

370:    shift[1] = pbcFactor[1] * s->domain->globalExtent[1];

371:    shift[2] = pbcFactor[2] * s->domain->globalExtent[2];

372:

373:    int nCells = parms->nCells[face];

374:    int* cellList = parms->cellList[face];

375:    int nBuf = 0;

376:    for (int iCell=0; iCell<nCells; ++iCell)

377:    {

378:       int iBox = cellList[iCell];

379:       int iOff = iBox*MAXATOMS;

380:       for (int ii=iOff; ii<iOff+s->boxes->nAtoms[iBox]; ++ii)

381:       {

382:          buf[nBuf].gid  = s->atoms->gid[ii];

383:          buf[nBuf].type = s->atoms->iSpecies[ii];

384:          buf[nBuf].rx = s->atoms->r[ii][0] + shift[0];

385:          buf[nBuf].ry = s->atoms->r[ii][1] + shift[1];

386:          buf[nBuf].rz = s->atoms->r[ii][2] + shift[2];

387:          buf[nBuf].px = s->atoms->p[ii][0];

388:          buf[nBuf].py = s->atoms->p[ii][1];

389:          buf[nBuf].pz = s->atoms->p[ii][2];

390:          ++nBuf;

391:       }

392:    }

393:    return nBuf*sizeof(AtomMsg);

394: }

0x413860 ADD	X6, X0, W2,SXTW #3

0x413864 LDR	X4, [X1, #16]

0x413868 LDR	X5, [X6, #72]

0x41386c LDR	W15, [X0, W2,SXTW #2]

0x413870 LDP	D0, D4, [X4, #72]

0x413874 LDP	D1, D2, [X5]

0x413878 LDR	D3, [X5, #16]

0x41387c LDR	D7, [X4, #88]

0x413880 FMUL	D5, D1, D0

0x413884 FMUL	D6, D2, D4

0x413888 LDR	X16, [X6, #24]

0x41388c FMUL	D16, D3, D7

0x413890 CMP	W15, #0

0x413894 B.LE	413980

0x413898 LDR	X0, [X1, #24]

0x41389c MOVZ	X13, #0

0x4138a0 MOVZ	W11, #0

0x4138a4 MOVZ	W18, #56

0x4138a8 MOVZ	W17, #24

0x4138ac LDR	X14, [X0, #120]

(33) 0x4138b0 LDR	W8, [X16, X13,LSL #2]

(33) 0x4138b4 ADD	X9, X14, W8,SXTW #2

(33) 0x4138b8 LDR	W2, [X14, W8,SXTW #2]

(33) 0x4138bc UBFM	W8, W8, #26, #25

(33) 0x4138c0 CMP	W2, #0

(33) 0x4138c4 B.LE	413968

(33) 0x4138c8 LDR	X10, [X1, #32]

(33) 0x4138cc SMULL	X7, W8, W17

(33) 0x4138d0 ADD	W12, W11, #1

(33) 0x4138d4 SMADDL	X0, W11, W18, X3

(33) 0x4138d8 SBFM	X2, X8, #0, #31

(33) 0x4138dc LDP	X6, X4, [X10, #24]

(33) 0x4138e0 LDR	X11, [X10, #8]

(33) 0x4138e4 ADD	X5, X6, X7

(33) 0x4138e8 ADD	X4, X4, X7

(33) 0x4138ec LDR	X10, [X10, #16]

  (34) 0x4138f0 SUB	W7, W2, W8

  (34) 0x4138f4 ADD	X5, X5, #24

  (34) 0x4138f8 LDUR	D17, [X5, #488]

  (34) 0x4138fc ADD	W7, W12, W7

  (34) 0x413900 ADD	X4, X4, #24

  (34) 0x413904 ADD	X0, X0, #56

  (34) 0x413908 LDR	W6, [X11, X2,LSL #2]

  (34) 0x41390c FADD	D18, D17, D5

  (34) 0x413910 STUR	W6, [X0, #456]

  (34) 0x413914 LDR	W6, [X10, X2,LSL #2]

  (34) 0x413918 ADD	X2, X2, #1

  (34) 0x41391c STUR	D18, [X0, #464]

  (34) 0x413920 LDUR	D19, [X5, #496]

  (34) 0x413924 STUR	W6, [X0, #460]

  (34) 0x413928 LDR	W6, [X9]

  (34) 0x41392c FADD	D20, D19, D6

  (34) 0x413930 ADD	W6, W8, W6

  (34) 0x413934 STUR	D20, [X0, #472]

  (34) 0x413938 LDUR	D21, [X5, #504]

  (34) 0x41393c FADD	D22, D21, D16

  (34) 0x413940 STUR	D22, [X0, #480]

  (34) 0x413944 LDUR	D23, [X4, #488]

  (34) 0x413948 STUR	D23, [X0, #488]

  (34) 0x41394c LDUR	D24, [X4, #496]

  (34) 0x413950 STUR	D24, [X0, #496]

  (34) 0x413954 LDUR	D25, [X4, #504]

  (34) 0x413958 STUR	D25, [X0, #504]

  (34) 0x41395c CMP	W6, W2

  (34) 0x413960 B.GT	4138f0

(33) 0x413964 ORR	W11, WZR, W7

(33) 0x413968 ADD	X13, X13, #1

(33) 0x41396c CMP	W15, W13

(33) 0x413970 B.GT	4138b0

0x413974 MOVZ	W1, #56

0x413978 MUL	W0, W11, W1

0x41397c RET

0x413980 MOVZ	W0, #0

0x413984 RET

Coverage (%)	Name	Source Location	Module
►99.07+	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	haloExchange.c:365-394
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:365-394.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 1.67 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 3.33 to 0.83 cycles (4.00x speedup).

Details

15% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: multiply

The binary function is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 1.00 FP operations per loaded or stored byte.

General properties

nb instructions	25
nb uops	25
loop length	100
used w registers	7
used x registers	8
used b registers	0
used h registers	0
used s registers	0
used d registers	9
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.25	2.25	2.25	2.25	0.75	0.75	0.75	0.75	3.33	3.33	3.33	0.00	0.00
cycles	1.50	1.50	2.25	2.25	2.25	2.25	0.75	0.75	0.75	0.75	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.13
Dispatch	3.33
Overall L1	3.33

Vectorization ratios

INT

all	20%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.33 cycles. At this rate:

0% of peak load performance is reached (0.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 413860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD X6, X0, W2,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X4, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X5, [X6, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR W15, [X0, W2,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP D0, D4, [X4, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDP D1, D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR D3, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D7, [X4, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D5, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D6, D2, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR X16, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
FMUL D16, D3, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
CMP W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 413980 <loadAtomsBuffer+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MOVZ X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W18, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W17, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X14, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
MOVZ W1, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL W0, W11, W1	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	haloExchange.c:365-394
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:365-394.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 1.67 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

15% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: multiply

The binary function is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 1.00 FP operations per loaded or stored byte.

General properties

nb instructions	25
nb uops	25
loop length	100
used w registers	7
used x registers	8
used b registers	0
used h registers	0
used s registers	0
used d registers	9
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.25	2.25	2.25	2.25	0.75	0.75	0.75	0.75	3.33	3.33	3.33	0.00	0.00
cycles	1.50	1.50	2.25	2.25	2.25	2.25	0.75	0.75	0.75	0.75	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.13
Dispatch	3.33
Overall L1	3.33

Vectorization ratios

INT

all	20%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.33 cycles. At this rate:

0% of peak load performance is reached (0.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 413860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
ADD X6, X0, W2,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X4, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X5, [X6, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR W15, [X0, W2,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP D0, D4, [X4, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDP D1, D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR D3, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D7, [X4, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D5, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMUL D6, D2, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
LDR X16, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
FMUL D16, D3, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
CMP W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 413980 <loadAtomsBuffer+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MOVZ X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W18, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W17, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X14, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
MOVZ W1, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL W0, W11, W1	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼loadAtomsBuffer–	0.08	0.01
▼Loop 33 - haloExchange.c:376-390 - exec–	0.00	0.03
○Loop 34 - haloExchange.c:380-389 - exec	0.07	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code