OV - exec - Function getBoxFromTuple

	Function: getBoxFromTuple	Module: exec	Source: linkCells.c:204-250	Coverage (incl. loops): 0.01% \| (excl. loops): 0.01%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 204 - 250

--------------------------------------------------------------------------------

204: {

205:    int iBox = 0;

206:    const int* gridSize = boxes->gridSize; // alias

207:

208:    // Halo in Z+

209:    if (iz == gridSize[2])

210:    {

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

248:

249:    return iBox;

250: }

0x417150 STP	X29, X30, [SP, #1008]!

0x417154 ORR	X5, XZR, X0

0x417158 ADD	X29, SP, #0

0x41715c LDR	W0, [X0, #8]

0x417160 LDP	W6, W4, [X5]

0x417164 CMP	W0, W3

0x417168 B.EQ	4171e4

0x41716c CMN	W3, #1

0x417170 B.EQ	4171b8

0x417174 CMP	W2, W4

0x417178 B.EQ	417238

0x41717c CMN	W2, #1

0x417180 B.EQ	417218

0x417184 CMP	W1, W6

0x417188 B.EQ	41725c

0x41718c CMN	W1, #1

0x417190 B.EQ	417270

0x417194 MADD	W2, W2, W6, W1

0x417198 MUL	W1, W6, W4

0x41719c MADD	W0, W1, W3, W2

0x4171a0 TBNZ	W0, #31, 417280

0x4171a4 LDR	W1, [X5, #20]

0x4171a8 CMP	W1, W0

0x4171ac B.LE	4172a0

0x4171b0 LDP	X29, X30, [SP], #16

0x4171b4 RET

0x4171b8 LDR	W3, [X5, #12]

0x4171bc MUL	W8, W0, W4

0x4171c0 ADD	W7, W6, #2

0x4171c4 ADD	W1, W1, #1

0x4171c8 MUL	W9, W0, W7

0x4171cc MADD	W10, W2, W7, W7

0x4171d0 ADD	W11, W3, W8,LSL #1

0x4171d4 ADD	W12, W11, W9,LSL #1

0x4171d8 ADD	W13, W12, W10

0x4171dc ADD	W0, W13, W1

0x4171e0 B	4171a0

0x4171e4 ADD	W14, W6, #2

0x4171e8 LDR	W6, [X5, #12]

0x4171ec MUL	W15, W0, W4

0x4171f0 ADD	W16, W4, #2

0x4171f4 ADD	W17, W1, #1

0x4171f8 MUL	W18, W14, W0

0x4171fc MADD	W30, W2, W14, W14

0x417200 ADD	W4, W6, W15,LSL #1

0x417204 ADD	W0, W4, W18,LSL #1

0x417208 MADD	W2, W16, W14, W0

0x41720c ADD	W7, W2, W30

0x417210 ADD	W0, W7, W17

0x417214 B	4171a0

0x417218 LDR	W14, [X5, #12]

0x41721c MUL	W11, W0, W4

0x417220 ADD	W12, W6, #2

0x417224 ADD	W13, W1, #1

0x417228 ADD	W15, W14, W11,LSL #1

0x41722c MADD	W16, W12, W3, W15

0x417230 ADD	W0, W16, W13

0x417234 B	4171a0

0x417238 ADD	W18, W6, #2

0x41723c LDR	W6, [X5, #12]

0x417240 MUL	W17, W0, W2

0x417244 ADD	W30, W1, #1

0x417248 ADD	W4, W6, W17,LSL #1

0x41724c MADD	W0, W0, W18, W4

0x417250 MADD	W2, W18, W3, W0

0x417254 ADD	W0, W2, W30

0x417258 B	4171a0

0x41725c LDR	W8, [X5, #12]

0x417260 MADD	W9, W0, W4, W8

0x417264 MADD	W10, W3, W4, W9

0x417268 ADD	W0, W10, W2

0x41726c B	4171a0

0x417270 LDR	W7, [X5, #12]

0x417274 MADD	W3, W3, W4, W7

0x417278 ADD	W0, W3, W2

0x41727c B	4171a0

0x417280 ADRP	X5,

0x417284 ADRP	X8,

0x417288 ADRP	X9,

0x41728c ADD	X3, X5, #3240

0x417290 ADD	X1, X8, #2960

0x417294 ADD	X0, X9, #3056

0x417298 MOVZ	W2, #246

0x41729c BL	4101e0

0x4172a0 ADRP	X10,

0x4172a4 ADRP	X11,

0x4172a8 ADRP	X12,

0x4172ac ADD	X3, X10, #3240

0x4172b0 ADD	X1, X11, #2960

0x4172b4 ADD	X0, X12, #3072

0x4172b8 MOVZ	W2, #247

0x4172bc BL	4101e0

Coverage (%)	Name	Source Location	Module
►17.65+	putAtomInBox	linkCells.c:179	exec
○	unloadAtomsBuffer	haloExchange.c:424	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec
►17.65+	putAtomInBox	linkCells.c:179	exec
○	unloadAtomsBuffer	haloExchange.c:424	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec
►17.65+	unloadAtomsBuffer	haloExchange.c:421	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec
►11.76+	putAtomInBox	linkCells.c:179	exec
○	unloadAtomsBuffer	haloExchange.c:421	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec
►11.76+	unloadAtomsBuffer	haloExchange.c:424	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec
►5.88+	putAtomInBox	linkCells.c:179	exec
○	createFccLattice	initAtoms.c:96	exec
○	main	CoMD.c:199	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec
►5.88+	putAtomInBox	linkCells.c:179	exec
○	unloadAtomsBuffer	haloExchange.c:421	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec
►5.88+	unloadAtomsBuffer	haloExchange.c:424	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec
►5.88+	createFccLattice	initAtoms.c:100	exec
○	main	CoMD.c:199	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines	linkCells.c:204-250
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:204-250.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=21

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This function has 21 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 15% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 16.75 to 2.47 cycles (6.78x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes.

General properties

nb instructions	92
nb uops	92
loop length	368
used w registers	19
used x registers	12
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	16.75	16.75	16.75	16.75	0.00	0.00	0.00	0.00	3.83	3.50	3.67	0.50	0.50
cycles	8.50	8.50	16.75	16.75	16.75	16.75	0.00	0.00	0.00	0.00	3.83	3.50	3.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.50
Dispatch	16.75
Overall L1	16.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	15%
load	18%
store	50%
mul	12%
add-sub	17%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.75 cycles. At this rate:

1% of peak load performance is reached (1.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 417150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #1008]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X5, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W0, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W6, W4, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4171e4 <getBoxFromTuple+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4171b8 <getBoxFromTuple+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 417238 <getBoxFromTuple+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 417218 <getBoxFromTuple+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 41725c <getBoxFromTuple+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 417270 <getBoxFromTuple+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W2, W6, W1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
MUL W1, W6, W4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
MADD W0, W1, W3, W2	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
TBNZ W0, #31, 417280 <getBoxFromTuple+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X5, #20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4172a0 <getBoxFromTuple+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X29, X30, [SP], #16	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W3, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL W8, W0, W4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W7, W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W9, W0, W7	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
MADD W10, W2, W7, W7	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W11, W3, W8,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W12, W11, W9,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W13, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W6, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL W15, W0, W4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W16, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W17, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W18, W14, W0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
MADD W30, W2, W14, W14	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W4, W6, W15,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W4, W18,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD W2, W16, W14, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W7, W2, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W7, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W14, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL W11, W0, W4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W12, W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W13, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W15, W14, W11,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MADD W16, W12, W3, W15	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W16, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W18, W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W6, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL W17, W0, W2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W30, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W4, W6, W17,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MADD W0, W0, W18, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD W2, W18, W3, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W2, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MADD W9, W0, W4, W8	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
MADD W10, W3, W4, W9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W10, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W7, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MADD W3, W3, W4, W7	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W3, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <421280>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADRP X8, <420284>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X9, <420288>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X5, #3240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X8, #2960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X9, #3056	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #246	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101e0 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X10, <4212a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X11, <4202a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X12, <4202a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, X10, #3240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X11, #2960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X12, #3072	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #247	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101e0 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines	linkCells.c:204-250
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:204-250.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=21

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes.

General properties

nb instructions	92
nb uops	92
loop length	368
used w registers	19
used x registers	12
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	16.75	16.75	16.75	16.75	0.00	0.00	0.00	0.00	3.83	3.50	3.67	0.50	0.50
cycles	8.50	8.50	16.75	16.75	16.75	16.75	0.00	0.00	0.00	0.00	3.83	3.50	3.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.50
Dispatch	16.75
Overall L1	16.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	15%
load	18%
store	50%
mul	12%
add-sub	17%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.75 cycles. At this rate:

1% of peak load performance is reached (1.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 417150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #1008]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X5, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W0, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W6, W4, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4171e4 <getBoxFromTuple+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 4171b8 <getBoxFromTuple+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 417238 <getBoxFromTuple+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 417218 <getBoxFromTuple+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 41725c <getBoxFromTuple+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 417270 <getBoxFromTuple+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W2, W6, W1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
MUL W1, W6, W4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
MADD W0, W1, W3, W2	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
TBNZ W0, #31, 417280 <getBoxFromTuple+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X5, #20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4172a0 <getBoxFromTuple+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X29, X30, [SP], #16	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W3, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL W8, W0, W4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W7, W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W9, W0, W7	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
MADD W10, W2, W7, W7	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W11, W3, W8,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W12, W11, W9,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W13, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W6, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL W15, W0, W4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W16, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W17, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W18, W14, W0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
MADD W30, W2, W14, W14	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W4, W6, W15,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W4, W18,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD W2, W16, W14, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W7, W2, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W7, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W14, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL W11, W0, W4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W12, W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W13, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W15, W14, W11,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MADD W16, W12, W3, W15	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W16, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W18, W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W6, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MUL W17, W0, W2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ADD W30, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W4, W6, W17,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MADD W0, W0, W18, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD W2, W18, W3, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W2, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MADD W9, W0, W4, W8	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
MADD W10, W3, W4, W9	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W10, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W7, [X5, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MADD W3, W3, W4, W7	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W3, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4171a0 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <421280>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADRP X8, <420284>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X9, <420288>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X5, #3240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X8, #2960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X9, #3056	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #246	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101e0 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X10, <4212a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X11, <4202a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X12, <4202a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, X10, #3240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X11, #2960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X12, #3072	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #247	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101e0 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
○getBoxFromTuple	0.01	0.00

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code