OV - exec - Function ljForce._omp

	Function: ljForce._omp_fn.1	Module: exec	Source: ljForce.c:172-216 [...]	Coverage (incl. loops): 90.58% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216

--------------------------------------------------------------------------------

172:    #pragma omp parallel for reduction(+:ePot)

173:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

174:    {

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

0x417f88 STP	X29, X30, [SP, #928]!

0x417f8c ADD	X29, SP, #0

0x417f90 STP	X19, X20, [SP, #16]

0x417f94 ORR	X20, XZR, X0

0x417f98 STP	X21, X22, [SP, #32]

0x417f9c LDR	X19, [X0]

0x417fa0 STR	D8, [SP, #80]

0x417fa4 BL	410050

0x417fa8 LDR	D8, [X20, #8]

0x417fac ORR	W21, WZR, W0

0x417fb0 BL	410150

0x417fb4 LDR	X22, [X19, #24]

0x417fb8 ORR	W13, WZR, W0

0x417fbc LDR	W30, [X20, #48]

0x417fc0 LDP	D5, D19, [X20, #16]

0x417fc4 LDR	W0, [X22, #12]

0x417fc8 LDR	D18, [X20, #32]

0x417fcc SDIV	W15, W0, W21

0x417fd0 MSUB	W1, W15, W21, W0

0x417fd4 CMP	W13, W1

0x417fd8 B.LT	418328

0x417fdc MADD	W2, W15, W13, W1

0x417fe0 ADD	W15, W15, W2

0x417fe4 CMP	W2, W15

0x417fe8 B.GE	418340

0x417fec MOVI	D7, #0

0x417ff0 LDR	X21, [X22, #120]

0x417ff4 FMOV	D17, #1.0000000

0x417ff8 FMOV	D16, #0.5000000

0x417ffc FMOV	D22, #-4.0000000

0x418000 SBFM	X16, X2, #0, #31

0x418004 FMOV	D21, #12.0000000

0x418008 FMOV	D20, #-6.0000000

0x41800c UBFM	W13, W2, #26, #25

0x418010 STP	X23, X24, [SP, #48]

0x418014 MOVZ	W23, #24

0x418018 FMOV	D6, D7

0x41801c STP	X25, X26, [SP, #64]

(91) 0x418020 LDR	W17, [X21, X16,LSL #2]

(91) 0x418024 CMP	W30, #0

(91) 0x418028 B.LE	418188

(91) 0x41802c UBFM	W18, W16, #26, #25

(91) 0x418030 SUB	W3, W17, #1

(91) 0x418034 LDR	X6, [X22, #128]

(91) 0x418038 SBFM	X12, X18, #0, #31

(91) 0x41803c ADD	W17, W17, W13

(91) 0x418040 ADD	X4, X12, #1

(91) 0x418044 SBFM	X25, X18, #61, #31

(91) 0x418048 ADD	X5, X4, X3

(91) 0x41804c MOVZ	X14, #0

(91) 0x418050 UBFM	X12, X5, #61, #60

(91) 0x418054 LDR	X24, [X6, X16,LSL #3]

  (93) 0x418058 LDR	W8, [X24, X14,LSL #2]

  (93) 0x41805c TBNZ	W8, #31, 418348

  (93) 0x418060 LDR	W11, [X21, W8,SXTW #2]

  (93) 0x418064 CMP	W18, W17

  (93) 0x418068 B.GE	41817c

  (93) 0x41806c UBFM	W8, W8, #26, #25

  (93) 0x418070 SUB	W26, W11, #1

  (93) 0x418074 ADD	X0, X26, W8,SXTW

  (93) 0x418078 ADD	X1, X0, X0,LSL #1

  (93) 0x41807c ADD	W11, W11, W8

  (93) 0x418080 ORR	X4, XZR, X25

  (93) 0x418084 SMULL	X10, W8, W23

  (93) 0x418088 UBFM	X9, X1, #61, #60

    (94) 0x41808c CMP	W8, W11

    (94) 0x418090 B.GE	418170

    (94) 0x418094 LDR	X6, [X19, #32]

    (94) 0x418098 ADD	X5, X4, X4,LSL #1

    (94) 0x41809c LDR	X2, [X6, #24]

    (94) 0x4180a0 ADD	X3, X2, #24

    (94) 0x4180a4 ADD	X0, X2, X10

    (94) 0x4180a8 ADD	X3, X3, X9

    (94) 0x4180ac ADD	X1, X2, X5

    (94) 0x4180b0 SUB	X7, X3, X0

    (94) 0x4180b4 TBZ	W7, #3, 418100

    (94) 0x4180b8 LDR	D4, [X2, X5]

    (94) 0x4180bc LDR	D1, [X2, X10]

    (94) 0x4180c0 LDP	D0, D2, [X0, #8]

    (94) 0x4180c4 LDP	D3, D23, [X1, #8]

    (94) 0x4180c8 FSUB	D27, D4, S1

    (94) 0x4180cc FSUB	D28, D3, S0

    (94) 0x4180d0 FSUB	D29, D23, S2

    (94) 0x4180d4 FMADD	D24, D27, D27, D6

    (94) 0x4180d8 FMADD	D25, D28, D28, D24

    (94) 0x4180dc FMADD	D26, D29, D29, D25

    (94) 0x4180e0 FCMPE	D5, D26

    (94) 0x4180e4 B.GE	4182b8

    (94) 0x4180e8 ADD	X0, X0, #24

    (94) 0x4180ec CMP	X0, X3

    (94) 0x4180f0 B.EQ	418170

    (94) 0x4180f4 HINT	#0

    (94) 0x4180f8 HINT	#0

    (94) 0x4180fc HINT	#0

      (95) 0x418100 LDP	D23, D24, [X0]

      (95) 0x418104 LDP	D25, D3, [X1]

      (95) 0x418108 LDR	D2, [X0, #16]

      (95) 0x41810c LDR	D27, [X1, #16]

      (95) 0x418110 FSUB	D30, D25, S23

      (95) 0x418114 FSUB	D31, D3, S24

      (95) 0x418118 FSUB	D1, D27, S2

      (95) 0x41811c FMADD	D26, D30, D30, D6

      (95) 0x418120 FMADD	D4, D31, D31, D26

      (95) 0x418124 FMADD	D0, D1, D1, D4

      (95) 0x418128 FCMPE	D5, D0

      (95) 0x41812c B.GE	418248

      (95) 0x418130 LDP	D26, D3, [X1]

      (95) 0x418134 ADD	X2, X0, #24

      (95) 0x418138 LDR	D25, [X0, #24]

      (95) 0x41813c LDP	D0, D28, [X2, #8]

      (95) 0x418140 LDR	D27, [X1, #16]

      (95) 0x418144 FSUB	D4, D26, S25

      (95) 0x418148 FSUB	D29, D3, S0

      (95) 0x41814c FSUB	D30, D27, S28

      (95) 0x418150 FMADD	D23, D4, D4, D6

      (95) 0x418154 FMADD	D24, D29, D29, D23

      (95) 0x418158 FMADD	D2, D30, D30, D24

      (95) 0x41815c FCMPE	D5, D2

      (95) 0x418160 B.GE	4181d8

      (95) 0x418164 ADD	X0, X2, #24

      (95) 0x418168 CMP	X0, X3

      (95) 0x41816c B.NE	418100

    (94) 0x418170 ADD	X4, X4, #8

    (94) 0x418174 CMP	X4, X12

    (94) 0x418178 B.NE	41808c

  (93) 0x41817c ADD	X14, X14, #1

  (93) 0x418180 CMP	W30, W14

  (93) 0x418184 B.GT	418058

(91) 0x418188 ADD	X16, X16, #1

(91) 0x41818c ADD	W13, W13, #64

(91) 0x418190 CMP	W15, W16

(91) 0x418194 B.GT	418020

0x418198 LDP	X23, X24, [SP, #48]

0x41819c LDP	X25, X26, [SP, #64]

0x4181a0 ADD	X20, X20, #40

0x4181a4 LDR	X30, [X20]

(92) 0x4181a8 ORR	X19, XZR, X30

(92) 0x4181ac FMOV	D8, X30

(92) 0x4181b0 FADD	D5, D7, D8

(92) 0x4181b4 FMOV	X22, D5

(92) 0x4181b8 CASAL	X30, X22, [X20]

(92) 0x4181bc CMP	X19, X30

(92) 0x4181c0 B.NE	4181a8

0x4181c4 LDP	X19, X20, [SP, #16]

0x4181c8 LDP	X21, X22, [SP, #32]

0x4181cc LDR	D8, [SP, #80]

0x4181d0 LDP	X29, X30, [SP], #96

0x4181d4 RET

      (95) 0x4181d8 FCMPE	D2, #0

      (95) 0x4181dc B.GT	4181e4

      (95) 0x4181e0 B	418164

      (95) 0x4181e4 FDIV	D31, D17, D2

      (95) 0x4181e8 LDP	X7, X26, [X6, #40]

      (95) 0x4181ec FMUL	D1, D8, D22

      (95) 0x4181f0 LDR	D2, [X26, X4]

      (95) 0x4181f4 ADD	X0, X7, X5

      (95) 0x4181f8 FMUL	D25, D31, D31

      (95) 0x4181fc FMUL	D26, D25, D31

      (95) 0x418200 FMUL	D3, D26, D19

      (95) 0x418204 FMADD	D27, D3, D21, D20

      (95) 0x418208 FSUB	D0, D3, S17

      (95) 0x41820c FMUL	D28, D1, D3

      (95) 0x418210 FNMSUB	D23, D0, D3, D18

      (95) 0x418214 FMUL	D24, D28, D31

      (95) 0x418218 FMADD	D1, D23, D16, D2

      (95) 0x41821c FMADD	D7, D23, D16, D7

      (95) 0x418220 FMUL	D31, D27, D24

      (95) 0x418224 STR	D1, [X26, X4]

      (95) 0x418228 LDR	D25, [X7, X5]

      (95) 0x41822c FMSUB	D4, D31, D4, D25

      (95) 0x418230 STR	D4, [X7, X5]

      (95) 0x418234 LDP	D26, D27, [X0, #8]

      (95) 0x418238 FMSUB	D29, D31, D29, D26

      (95) 0x41823c FMSUB	D30, D31, D30, D27

      (95) 0x418240 STP	D29, D30, [X0, #8]

      (95) 0x418244 B	418164

      (95) 0x418248 FCMPE	D0, #0

      (95) 0x41824c B.GT	418254

      (95) 0x418250 B	418130

      (95) 0x418254 FDIV	D28, D17, D0

      (95) 0x418258 FMUL	D29, D8, D22

      (95) 0x41825c LDP	X7, X26, [X6, #40]

      (95) 0x418260 ADD	X2, X7, X5

      (95) 0x418264 FMUL	D23, D28, D28

      (95) 0x418268 FMUL	D24, D23, D28

      (95) 0x41826c FMUL	D2, D24, D19

      (95) 0x418270 FMADD	D3, D2, D21, D20

      (95) 0x418274 FMUL	D26, D29, D2

      (95) 0x418278 FSUB	D25, D2, S17

      (95) 0x41827c FMUL	D27, D26, D28

      (95) 0x418280 LDR	D28, [X26, X4]

      (95) 0x418284 FNMSUB	D4, D25, D2, D18

      (95) 0x418288 FMADD	D7, D4, D16, D7

      (95) 0x41828c FMADD	D29, D4, D16, D28

      (95) 0x418290 FMUL	D0, D3, D27

      (95) 0x418294 STR	D29, [X26, X4]

      (95) 0x418298 LDR	D23, [X7, X5]

      (95) 0x41829c FMSUB	D30, D0, D30, D23

      (95) 0x4182a0 STR	D30, [X7, X5]

      (95) 0x4182a4 LDP	D24, D2, [X2, #8]

      (95) 0x4182a8 FMSUB	D31, D0, D31, D24

      (95) 0x4182ac FMSUB	D1, D0, D1, D2

      (95) 0x4182b0 STP	D31, D1, [X2, #8]

      (95) 0x4182b4 B	418130

    (94) 0x4182b8 FCMPE	D26, #0

    (94) 0x4182bc B.GT	4182c4

    (94) 0x4182c0 B	4180e8

    (94) 0x4182c4 FDIV	D30, D17, D26

    (94) 0x4182c8 LDP	X7, X26, [X6, #40]

    (94) 0x4182cc FMUL	D31, D8, D22

    (94) 0x4182d0 LDR	D26, [X26, X4]

    (94) 0x4182d4 ADD	X2, X7, X5

    (94) 0x4182d8 FMUL	D4, D30, D30

    (94) 0x4182dc FMUL	D1, D4, D30

    (94) 0x4182e0 FMUL	D0, D1, D19

    (94) 0x4182e4 FMADD	D3, D0, D21, D20

    (94) 0x4182e8 FSUB	D2, D0, S17

    (94) 0x4182ec FMUL	D23, D31, D0

    (94) 0x4182f0 FNMSUB	D24, D2, D0, D18

    (94) 0x4182f4 FMUL	D25, D23, D30

    (94) 0x4182f8 FMADD	D31, D24, D16, D26

    (94) 0x4182fc FMADD	D7, D24, D16, D7

    (94) 0x418300 FMUL	D30, D3, D25

    (94) 0x418304 STR	D31, [X26, X4]

    (94) 0x418308 LDR	D4, [X7, X5]

    (94) 0x41830c FMSUB	D27, D30, D27, D4

    (94) 0x418310 STR	D27, [X7, X5]

    (94) 0x418314 LDP	D1, D0, [X2, #8]

    (94) 0x418318 FMSUB	D28, D30, D28, D1

    (94) 0x41831c FMSUB	D29, D30, D29, D0

    (94) 0x418320 STP	D28, D29, [X2, #8]

    (94) 0x418324 B	4180e8

0x418328 ADD	W15, W15, #1

0x41832c MOVZ	W1, #0

0x418330 MADD	W2, W15, W13, W1

0x418334 ADD	W15, W15, W2

0x418338 CMP	W2, W15

0x41833c B.LT	417fec

0x418340 MOVI	D7, #0

0x418344 B	4181a0

0x418348 ADRP	X7,

0x41834c ADRP	X9,

0x418350 ADRP	X10,

0x418354 ADD	X3, X7, #3288

0x418358 ADD	X1, X9, #3544

0x41835c ADD	X0, X10, #3640

0x418360 MOVZ	W2, #182

0x418364 BL	4101e0

Coverage (%)	Name	Source Location	Module
►98.57+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.42+	GOMP_parallel		libgomp.so.1.0.0
○	ljForce	ljForce.c:172	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ljForce.c:172-216
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 1.83 cycles (6.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 12.50 to 4.75 cycles (2.63x speedup).

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

10% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 7.75 cycles (1.61x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	63
nb uops	63
loop length	252
used w registers	9
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	11
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	7.50	7.50	7.50	7.50	2.25	2.25	2.25	2.25	7.00	7.00	7.00	2.50	2.50
cycles	4.00	4.00	7.50	7.50	7.50	7.50	2.25	2.25	2.25	2.25	7.00	7.00	7.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	7.88
Dispatch	7.50
DIV/SQRT	5.00-12.50
Overall L1	7.88-12.50

Vectorization ratios

INT

all	2%
load	10%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	10%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	27%
load	33%
store	45%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	12%
other	21%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	26%
load	33%
store	45%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	12%
div/sqrt	12%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 417f88

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D8, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D8, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W13, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W30, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP D5, D19, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR W0, [X22, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D18, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
SDIV W15, W0, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W1, W15, W21, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 418328 <ljForce._omp_fn.1+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W15, W13, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W15, W15, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 418340 <ljForce._omp_fn.1+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X21, [X22, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV D17, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D16, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D22, #-4.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SBFM X16, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
FMOV D21, #12.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D20, #-6.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
UBFM W13, W2, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W23, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
FMOV D6, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X20, X20, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MADD W2, W15, W13, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W15, W15, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 417fec <ljForce._omp_fn.1+0x64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 4181a0 <ljForce._omp_fn.1+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X7, <421348>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X9, <42034c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X10, <420350>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X7, #3288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X9, #3544	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X10, #3640	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #182	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101e0 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ljForce.c:172-216
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 1.83 cycles (6.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

10% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 7.75 cycles (1.61x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	63
nb uops	63
loop length	252
used w registers	9
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	11
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	7.50	7.50	7.50	7.50	2.25	2.25	2.25	2.25	7.00	7.00	7.00	2.50	2.50
cycles	4.00	4.00	7.50	7.50	7.50	7.50	2.25	2.25	2.25	2.25	7.00	7.00	7.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	7.88
Dispatch	7.50
DIV/SQRT	5.00-12.50
Overall L1	7.88-12.50

Vectorization ratios

INT

all	2%
load	10%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	10%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	27%
load	33%
store	45%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	12%
other	21%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	26%
load	33%
store	45%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	12%
div/sqrt	12%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 417f88

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D8, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D8, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W13, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W30, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP D5, D19, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR W0, [X22, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D18, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
SDIV W15, W0, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
MSUB W1, W15, W21, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 418328 <ljForce._omp_fn.1+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W15, W13, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W15, W15, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 418340 <ljForce._omp_fn.1+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X21, [X22, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV D17, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D16, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D22, #-4.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SBFM X16, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
FMOV D21, #12.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D20, #-6.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
UBFM W13, W2, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W23, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
FMOV D6, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X20, X20, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MADD W2, W15, W13, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W15, W15, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 417fec <ljForce._omp_fn.1+0x64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 4181a0 <ljForce._omp_fn.1+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X7, <421348>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X9, <42034c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X10, <420350>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X7, #3288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X9, #3544	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X10, #3640	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #182	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101e0 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼ljForce._omp_fn.1–	90.58	13.26
▼Loop 91 - ljForce.c:175-216 - exec–	0.03	0.01
▼Loop 93 - ljForce.c:178-216 - exec–	0.41	0.05
▼Loop 94 - ljForce.c:187-216 - exec–	6.54	0.71
○Loop 95 - ljForce.c:191-216 - exec	83.60	9.13
○Loop 92 - ljForce.c:172-172 - exec	0.00	0.01

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code