OV - exec - Function advanceVelocity._omp

	Function: advanceVelocity._omp_fn.0	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 2.20% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x41a660 STP	X29, X30, [SP, #976]!

0x41a664 ADD	X29, SP, #0

0x41a668 STR	X21, [SP, #32]

0x41a66c LDR	W21, [X0, #16]

0x41a670 STP	X19, X20, [SP, #16]

0x41a674 ORR	X20, XZR, X0

0x41a678 BL	410050

0x41a67c ORR	W19, WZR, W0

0x41a680 BL	410150

0x41a684 SDIV	W11, W21, W19

0x41a688 ORR	W8, WZR, W0

0x41a68c MSUB	W1, W11, W19, W21

0x41a690 CMP	W0, W1

0x41a694 B.LT	41aad0

0x41a698 MADD	W2, W11, W8, W1

0x41a69c ADD	W30, W11, W2

0x41a6a0 CMP	W2, W30

0x41a6a4 B.GE	41a8ec

0x41a6a8 LDR	X13, [X20]

0x41a6ac MOVZ	W0, #1536

0x41a6b0 SBFM	X9, X2, #0, #31

0x41a6b4 MOVZ	W14, #48

0x41a6b8 MOVZ	W10, #24

0x41a6bc LDR	D0, [X20, #8]

0x41a6c0 SMULL	X8, W2, W0

0x41a6c4 LDR	X3, [X13, #24]

0x41a6c8 DUP	V3.2D, V0.D[0]

0x41a6cc LDR	X12, [X3, #120]

(104) 0x41a6d0 UBFM	W20, W9, #26, #25

(104) 0x41a6d4 LDR	W6, [X12, X9,LSL #2]

(104) 0x41a6d8 CMP	W6, #0

(104) 0x41a6dc B.LE	41a8dc

(104) 0x41a6e0 LDR	X4, [X13, #32]

(104) 0x41a6e4 ADD	X5, X8, #48

(104) 0x41a6e8 LDP	X21, X19, [X4, #32]

(104) 0x41a6ec ADD	X7, X21, X5

(104) 0x41a6f0 ADD	X16, X19, X8

(104) 0x41a6f4 ADD	X15, X21, X8

(104) 0x41a6f8 ADD	X17, X19, X5

(104) 0x41a6fc CMP	X16, X7

(104) 0x41a700 CCMP	X15, X17, #2, #3

(104) 0x41a704 CCMP	W6, #1, #4, #2

(104) 0x41a708 B.EQ	41a8fc

(104) 0x41a70c UBFM	W18, W6, #1, #31

(104) 0x41a710 ADD	X11, X15, #48

(104) 0x41a714 SUB	W0, W18, #1

(104) 0x41a718 MOVZ	X3, #43691

(104) 0x41a71c MOVK	X3, #43690

(104) 0x41a720 ORR	X1, XZR, X15

(104) 0x41a724 UMADDL	X4, W0, W14, X11

(104) 0x41a728 MOVK	X3, #43690

(104) 0x41a72c ORR	X2, XZR, X16

(104) 0x41a730 MOVK	X3, #2730

(104) 0x41a734 SUB	X5, X4, X15

(104) 0x41a738 SUB	X7, X5, #48

(104) 0x41a73c UBFM	X17, X7, #4, #63

(104) 0x41a740 MUL	X18, X17, X3

(104) 0x41a744 ADD	X0, X18, #1

(104) 0x41a748 ANDS	X3, X0, #0x3

(104) 0x41a74c B.EQ	41a7ec

(104) 0x41a750 CMP	X3, #1

(104) 0x41a754 B.EQ	41a7b8

(104) 0x41a758 CMP	X3, #2

(104) 0x41a75c B.EQ	41a78c

(104) 0x41a760 LDP	Q1, Q6, [X16]

(104) 0x41a764 ORR	X1, XZR, X11

(104) 0x41a768 ADD	X2, X16, #48

(104) 0x41a76c LDP	Q4, Q2, [X15]

(104) 0x41a770 LDR	Q5, [X16, #32]

(104) 0x41a774 LDR	Q7, [X15, #32]

(104) 0x41a778 FMLA	V4.2D, V3.2D, V1.2D

(104) 0x41a77c FMLA	V2.2D, V3.2D, V6.2D

(104) 0x41a780 FMLA	V7.2D, V3.2D, V5.2D

(104) 0x41a784 STP	Q4, Q2, [X15]

(104) 0x41a788 STR	Q7, [X15, #32]

(104) 0x41a78c LDP	Q18, Q19, [X2]

(104) 0x41a790 ADD	X2, X2, #48

(104) 0x41a794 LDP	Q16, Q17, [X1]

(104) 0x41a798 LDUR	Q20, [X2, #496]

(104) 0x41a79c LDR	Q21, [X1, #32]

(104) 0x41a7a0 FMLA	V16.2D, V3.2D, V18.2D

(104) 0x41a7a4 FMLA	V17.2D, V3.2D, V19.2D

(104) 0x41a7a8 FMLA	V21.2D, V3.2D, V20.2D

(104) 0x41a7ac STP	Q16, Q17, [X1]

(104) 0x41a7b0 ADD	X1, X1, #48

(104) 0x41a7b4 STUR	Q21, [X1, #496]

(104) 0x41a7b8 LDP	Q24, Q25, [X2]

(104) 0x41a7bc ADD	X2, X2, #48

(104) 0x41a7c0 LDP	Q22, Q23, [X1]

(104) 0x41a7c4 LDUR	Q26, [X2, #496]

(104) 0x41a7c8 LDR	Q27, [X1, #32]

(104) 0x41a7cc FMLA	V22.2D, V3.2D, V24.2D

(104) 0x41a7d0 FMLA	V23.2D, V3.2D, V25.2D

(104) 0x41a7d4 FMLA	V27.2D, V3.2D, V26.2D

(104) 0x41a7d8 STP	Q22, Q23, [X1]

(104) 0x41a7dc ADD	X1, X1, #48

(104) 0x41a7e0 STUR	Q27, [X1, #496]

(104) 0x41a7e4 CMP	X4, X1

(104) 0x41a7e8 B.EQ	41a894

  (106) 0x41a7ec LDP	Q30, Q31, [X2]

  (106) 0x41a7f0 ADD	X15, X2, #144

  (106) 0x41a7f4 ADD	X16, X1, #144

  (106) 0x41a7f8 LDP	Q28, Q29, [X1]

  (106) 0x41a7fc LDP	Q1, Q4, [X1, #32]

  (106) 0x41a800 LDR	Q2, [X2, #32]

  (106) 0x41a804 LDR	Q7, [X1, #64]

  (106) 0x41a808 LDR	Q17, [X1, #80]

  (106) 0x41a80c FMLA	V28.2D, V3.2D, V30.2D

  (106) 0x41a810 LDP	Q18, Q19, [X1, #96]

  (106) 0x41a814 FMLA	V29.2D, V3.2D, V31.2D

  (106) 0x41a818 LDR	Q23, [X1, #128]

  (106) 0x41a81c LDP	Q24, Q25, [X1, #144]

  (106) 0x41a820 FMLA	V1.2D, V3.2D, V2.2D

  (106) 0x41a824 STP	Q28, Q29, [X1]

  (106) 0x41a828 STR	Q1, [X1, #32]

  (106) 0x41a82c LDP	Q16, Q6, [X2, #48]

  (106) 0x41a830 LDR	Q5, [X2, #80]

  (106) 0x41a834 FMLA	V17.2D, V3.2D, V5.2D

  (106) 0x41a838 FMLA	V4.2D, V3.2D, V16.2D

  (106) 0x41a83c FMLA	V7.2D, V3.2D, V6.2D

  (106) 0x41a840 STR	Q17, [X1, #80]

  (106) 0x41a844 STP	Q4, Q7, [X1, #48]

  (106) 0x41a848 LDP	Q20, Q21, [X2, #96]

  (106) 0x41a84c LDR	Q22, [X2, #128]

  (106) 0x41a850 FMLA	V23.2D, V3.2D, V22.2D

  (106) 0x41a854 FMLA	V18.2D, V3.2D, V20.2D

  (106) 0x41a858 FMLA	V19.2D, V3.2D, V21.2D

  (106) 0x41a85c STR	Q23, [X1, #128]

  (106) 0x41a860 STP	Q18, Q19, [X1, #96]

  (106) 0x41a864 LDP	Q26, Q27, [X2, #144]

  (106) 0x41a868 ADD	X1, X1, #192

  (106) 0x41a86c ADD	X2, X2, #192

  (106) 0x41a870 LDR	Q28, [X15, #32]

  (106) 0x41a874 LDUR	Q29, [X1, #496]

  (106) 0x41a878 FMLA	V24.2D, V3.2D, V26.2D

  (106) 0x41a87c FMLA	V25.2D, V3.2D, V27.2D

  (106) 0x41a880 FMLA	V29.2D, V3.2D, V28.2D

  (106) 0x41a884 STUR	Q24, [X1, #464]

  (106) 0x41a888 STP	Q25, Q29, [X16, #16]

  (106) 0x41a88c CMP	X4, X1

  (106) 0x41a890 B.NE	41a7ec

(104) 0x41a894 AND	W11, W6, #0xfffffffe

(104) 0x41a898 ADD	W20, W11, W20

(104) 0x41a89c CMP	W6, W11

(104) 0x41a8a0 B.EQ	41a8dc

(104) 0x41a8a4 SMULL	X6, W20, W10

(104) 0x41a8a8 LDR	D30, [X19, X6]

(104) 0x41a8ac ADD	X4, X21, X6

(104) 0x41a8b0 ADD	X19, X19, X6

(104) 0x41a8b4 LDR	D31, [X21, X6]

(104) 0x41a8b8 FMADD	D2, D0, D30, D31

(104) 0x41a8bc STR	D2, [X21, X6]

(104) 0x41a8c0 LDP	D7, D1, [X4, #8]

(104) 0x41a8c4 LDR	D4, [X19, #8]

(104) 0x41a8c8 FMADD	D16, D0, D4, D7

(104) 0x41a8cc STR	D16, [X4, #8]

(104) 0x41a8d0 LDR	D6, [X19, #16]

(104) 0x41a8d4 FMADD	D5, D0, D6, D1

(104) 0x41a8d8 STR	D5, [X4, #16]

(104) 0x41a8dc ADD	X9, X9, #1

(104) 0x41a8e0 ADD	X8, X8, #1536

(104) 0x41a8e4 CMP	W30, W9

(104) 0x41a8e8 B.GT	41a6d0

0x41a8ec LDP	X19, X20, [SP, #16]

0x41a8f0 LDR	X21, [SP, #32]

0x41a8f4 LDP	X29, X30, [SP], #48

0x41a8f8 RET

(104) 0x41a8fc SUB	W5, W6, #1

(104) 0x41a900 ADD	X21, X21, #24

(104) 0x41a904 ADD	X7, X5, X9,LSL #6

(104) 0x41a908 MOVZ	X17, #43691

(104) 0x41a90c ORR	X0, XZR, X15

(104) 0x41a910 MOVK	X17, #43690

(104) 0x41a914 ORR	X1, XZR, X16

(104) 0x41a918 ADD	X18, X7, X7,LSL #1

(104) 0x41a91c MOVK	X17, #43690

(104) 0x41a920 MOVK	X17, #2730

(104) 0x41a924 ADD	X3, X21, X18,LSL #3

(104) 0x41a928 SUB	X2, X3, X15

(104) 0x41a92c SUB	X11, X2, #24

(104) 0x41a930 UBFM	X20, X11, #3, #63

(104) 0x41a934 MUL	X6, X20, X17

(104) 0x41a938 ADD	X19, X6, #1

(104) 0x41a93c ANDS	X4, X19, #0x3

(104) 0x41a940 B.EQ	41a9f8

(104) 0x41a944 CMP	X4, #1

(104) 0x41a948 B.EQ	41a9bc

(104) 0x41a94c CMP	X4, #2

(104) 0x41a950 B.EQ	41a988

(104) 0x41a954 LDP	D17, D18, [X15]

(104) 0x41a958 ADD	X0, X15, #24

(104) 0x41a95c ADD	X1, X16, #24

(104) 0x41a960 LDR	D20, [X16]

(104) 0x41a964 LDR	D19, [X15, #16]

(104) 0x41a968 FMADD	D21, D0, D20, D17

(104) 0x41a96c STR	D21, [X15]

(104) 0x41a970 LDR	D22, [X16, #8]

(104) 0x41a974 FMADD	D23, D22, D0, D18

(104) 0x41a978 STR	D23, [X15, #8]

(104) 0x41a97c LDR	D24, [X16, #16]

(104) 0x41a980 FMADD	D25, D0, D24, D19

(104) 0x41a984 STR	D25, [X15, #16]

(104) 0x41a988 LDP	D26, D27, [X0]

(104) 0x41a98c ADD	X1, X1, #24

(104) 0x41a990 ADD	X0, X0, #24

(104) 0x41a994 LDUR	D29, [X1, #488]

(104) 0x41a998 LDUR	D28, [X0, #504]

(104) 0x41a99c FMADD	D30, D0, D29, D26

(104) 0x41a9a0 STUR	D30, [X0, #488]

(104) 0x41a9a4 LDUR	D31, [X1, #496]

(104) 0x41a9a8 FMADD	D2, D31, D0, D27

(104) 0x41a9ac STUR	D2, [X0, #496]

(104) 0x41a9b0 LDUR	D7, [X1, #504]

(104) 0x41a9b4 FMADD	D1, D0, D7, D28

(104) 0x41a9b8 STUR	D1, [X0, #504]

(104) 0x41a9bc LDP	D4, D16, [X0]

(104) 0x41a9c0 ADD	X0, X0, #24

(104) 0x41a9c4 ADD	X1, X1, #24

(104) 0x41a9c8 LDUR	D5, [X1, #488]

(104) 0x41a9cc LDUR	D6, [X0, #504]

(104) 0x41a9d0 FMADD	D17, D0, D5, D4

(104) 0x41a9d4 STUR	D17, [X0, #488]

(104) 0x41a9d8 LDUR	D18, [X1, #496]

(104) 0x41a9dc FMADD	D19, D18, D0, D16

(104) 0x41a9e0 STUR	D19, [X0, #496]

(104) 0x41a9e4 LDUR	D20, [X1, #504]

(104) 0x41a9e8 FMADD	D21, D0, D20, D6

(104) 0x41a9ec STUR	D21, [X0, #504]

(104) 0x41a9f0 CMP	X3, X0

(104) 0x41a9f4 B.EQ	41a8dc

  (105) 0x41a9f8 LDR	D25, [X1]

  (105) 0x41a9fc ADD	X16, X0, #72

  (105) 0x41aa00 ADD	X15, X1, #72

  (105) 0x41aa04 ADD	X1, X1, #96

  (105) 0x41aa08 LDP	D22, D23, [X0]

  (105) 0x41aa0c ADD	X0, X0, #96

  (105) 0x41aa10 LDUR	D24, [X0, #432]

  (105) 0x41aa14 LDUR	D27, [X0, #440]

  (105) 0x41aa18 FMADD	D26, D0, D25, D22

  (105) 0x41aa1c LDUR	D16, [X0, #448]

  (105) 0x41aa20 LDUR	D1, [X0, #456]

  (105) 0x41aa24 LDUR	D18, [X0, #464]

  (105) 0x41aa28 LDUR	D21, [X0, #472]

  (105) 0x41aa2c LDUR	D22, [X0, #480]

  (105) 0x41aa30 STUR	D26, [X0, #416]

  (105) 0x41aa34 LDUR	D28, [X1, #424]

  (105) 0x41aa38 FMADD	D29, D28, D0, D23

  (105) 0x41aa3c STUR	D29, [X0, #424]

  (105) 0x41aa40 LDUR	D30, [X1, #432]

  (105) 0x41aa44 FMADD	D31, D0, D30, D24

  (105) 0x41aa48 STUR	D31, [X0, #432]

  (105) 0x41aa4c LDUR	D2, [X1, #440]

  (105) 0x41aa50 FMADD	D7, D0, D2, D27

  (105) 0x41aa54 LDUR	D27, [X0, #488]

  (105) 0x41aa58 STUR	D7, [X0, #440]

  (105) 0x41aa5c LDUR	D4, [X1, #448]

  (105) 0x41aa60 FMADD	D6, D4, D0, D16

  (105) 0x41aa64 STUR	D6, [X0, #448]

  (105) 0x41aa68 LDUR	D5, [X1, #456]

  (105) 0x41aa6c FMADD	D17, D0, D5, D1

  (105) 0x41aa70 STUR	D17, [X0, #456]

  (105) 0x41aa74 LDUR	D19, [X1, #464]

  (105) 0x41aa78 FMADD	D20, D0, D19, D18

  (105) 0x41aa7c STUR	D20, [X0, #464]

  (105) 0x41aa80 LDUR	D23, [X1, #472]

  (105) 0x41aa84 FMADD	D24, D23, D0, D21

  (105) 0x41aa88 STUR	D24, [X0, #472]

  (105) 0x41aa8c LDUR	D25, [X1, #480]

  (105) 0x41aa90 FMADD	D26, D0, D25, D22

  (105) 0x41aa94 STUR	D26, [X0, #480]

  (105) 0x41aa98 LDUR	D28, [X1, #488]

  (105) 0x41aa9c FMADD	D29, D0, D28, D27

  (105) 0x41aaa0 STUR	D29, [X0, #488]

  (105) 0x41aaa4 LDR	D30, [X16, #8]

  (105) 0x41aaa8 LDR	D31, [X15, #8]

  (105) 0x41aaac FMADD	D2, D31, D0, D30

  (105) 0x41aab0 STR	D2, [X16, #8]

  (105) 0x41aab4 LDR	D7, [X16, #16]

  (105) 0x41aab8 LDR	D16, [X15, #16]

  (105) 0x41aabc FMADD	D1, D0, D16, D7

  (105) 0x41aac0 STR	D1, [X16, #16]

  (105) 0x41aac4 CMP	X3, X0

  (105) 0x41aac8 B.NE	41a9f8

(104) 0x41aacc B	41a8dc

0x41aad0 ADD	W11, W11, #1

0x41aad4 MOVZ	W1, #0

0x41aad8 B	41a698

0x41aadc HINT	#0

Coverage (%)	Name	Module
►98.28+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 26% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 4.75 cycles (2.63x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	36
nb uops	35
loop length	144
used w registers	11
used x registers	13
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	2
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.38 cycles
front end	4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.00	5.00	5.00	5.00	0.25	0.25	0.25	0.25	3.83	3.50	3.67	1.50	1.50
cycles	3.00	3.00	5.00	5.00	5.00	5.00	0.25	0.25	0.25	0.25	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	4.38
Dispatch	5.00
DIV/SQRT	5.00-12.50
Overall L1	5.00-12.50

Vectorization ratios

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

all	26%
load	27%
store	41%
mul	12%
add-sub	18%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 41a660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV W11, W21, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W1, W11, W19, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 41aad0 <advanceVelocity._omp_fn.0+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W11, W8, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W30, W11, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 41a8ec <advanceVelocity._omp_fn.0+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X9, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MOVZ W14, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W10, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D0, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
SMULL X8, W2, W0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
LDR X3, [X13, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V3.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR X12, [X3, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 41a698 <advanceVelocity._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 26% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 4.75 cycles (2.63x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	36
nb uops	35
loop length	144
used w registers	11
used x registers	13
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	2
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.38 cycles
front end	4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.00	5.00	5.00	5.00	0.25	0.25	0.25	0.25	3.83	3.50	3.67	1.50	1.50
cycles	3.00	3.00	5.00	5.00	5.00	5.00	0.25	0.25	0.25	0.25	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	4.38
Dispatch	5.00
DIV/SQRT	5.00-12.50
Overall L1	5.00-12.50

Vectorization ratios

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

all	26%
load	27%
store	41%
mul	12%
add-sub	18%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 41a660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV W11, W21, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W1, W11, W19, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 41aad0 <advanceVelocity._omp_fn.0+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W11, W8, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W30, W11, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 41a8ec <advanceVelocity._omp_fn.0+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X9, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MOVZ W14, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W10, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D0, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
SMULL X8, W2, W0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
LDR X3, [X13, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V3.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR X12, [X3, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 41a698 <advanceVelocity._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity._omp_fn.0–	2.20	0.32
▼Loop 104 - timestep.c:71-78 - exec–	0.70	0.08
○Loop 106 - timestep.c:74-76 - exec	1.51	0.16
○Loop 105 - timestep.c:74-78 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code