OV - exec - Loop 101

	Loop Id: 101	Module: exec	Source: random.c:26-48 [...]	Coverage: 0.01%

0x41a280 MUL	X6, X13, X5

0x41a284 UDIV	X3, X6, X4

0x41a288 UBFM	X2, X3, #3, #2

0x41a28c SUB	X7, X2, X3

0x41a290 SUB	X8, X6, X7

0x41a294 MUL	X9, X8, X5

0x41a298 SCVTF	D0, X8

0x41a29c UDIV	X10, X9, X4

0x41a2a0 FMUL	D4, D0, D1

0x41a2a4 FMADD	D6, D4, D3, D2

0x41a2a8 UBFM	X11, X10, #3, #2

0x41a2ac SUB	X12, X11, X10

0x41a2b0 SUB	X13, X9, X12

0x41a2b4 SCVTF	D8, X13

0x41a2b8 FMUL	D7, D8, D1

0x41a2bc FMADD	D8, D7, D3, D2

0x41a2c0 FMUL	D9, D8, D8

0x41a2c4 FMADD	D9, D6, D6, D9

0x41a2c8 FCMPE	D9, D5

0x41a2cc B.GE	41a280

0x41a2d0 FCMP	D9, #0

0x41a2d4 B.EQ	41a280

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 26 - 48

--------------------------------------------------------------------------------

26:       v1 = 2.0*lcg61(seed)-1.0;

27:       v2 = 2.0*lcg61(seed)-1.0;

28:       rsq = v1*v1+v2*v2;

29:    } while (rsq >= 1.0 || rsq == 0.0);

[...]

45:    *seed *= UINT64_C(437799614237992725);

46:    *seed %= UINT64_C(2305843009213693951);

47:

48:    return *seed*convertToDouble;

Coverage (%)	Name	Source Location	Module
►44.44+	setTemperature._omp_fn.0	initAtoms.c:160	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►38.89+	setTemperature._omp_fn.0	initAtoms.c:161	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.11+	setTemperature._omp_fn.0	initAtoms.c:162	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.56+	setTemperature._omp_fn.0	initAtoms.c:160	exec
○	GOMP_parallel		libgomp.so.1.0.0
○	setTemperature	initAtoms.c:167	exec
○	main	CoMD.c:200	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.25
CQA speedup if fully vectorized	4.00 - 2.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks
Function	gasdev
Source	random.c:26-29,random.c:45-48
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00 - 50.00
CQA cycles if no scalar integer	20.00 - 50.00
CQA cycles if FP arith vectorized	14.55 - 40.00
CQA cycles if fully vectorized	5.00 - 20.00
Front-end cycles	2.75
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	4.00
P5 cycles	2.50
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	20 - 50
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.45 - 0.18
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.25
CQA speedup if fully vectorized	4.00 - 2.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks
Function	gasdev
Source	random.c:26-29,random.c:45-48
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00 - 50.00
CQA cycles if no scalar integer	20.00 - 50.00
CQA cycles if FP arith vectorized	14.55 - 40.00
CQA cycles if fully vectorized	5.00 - 20.00
Front-end cycles	2.75
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	4.00
P5 cycles	2.50
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	10.00 - 40.00
Inter-iter dependencies cycles	20 - 50
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.45 - 0.18
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	gasdev
Source file and lines	random.c:26-48
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:26-29,45-48.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 50.00 to 20.00 cycles (2.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
6: multiply (3 inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	22
nb uops	22
loop length	88
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	10
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.75	2.75	4.00	2.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	2.75	2.75	4.00	2.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	20.00-50.00

Cycles summary

Front-end	2.75
Dispatch	4.00
DIV/SQRT	10.00-40.00
Data deps.	20.00-50.00
Overall L1	20.00-50.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41a280

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MUL X6, X13, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
UDIV X3, X6, X4	1	0	0	0	0	1	0	0	0	0	0	5-20	5-20	scal (25.0%)
UBFM X2, X3, #3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X7, X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
MUL X9, X8, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
SCVTF D0, X8	1	0	0	0	0	1	0	0	0	0	0	3	1	scal (25.0%)
UDIV X10, X9, X4	1	0	0	0	0	1	0	0	0	0	0	5-20	5-20	scal (25.0%)
FMUL D4, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (25.0%)
FMADD D6, D4, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
UBFM X11, X10, #3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X12, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X13, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SCVTF D8, X13	1	0	0	0	0	1	0	0	0	0	0	3	1	scal (25.0%)
FMUL D7, D8, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (25.0%)
FMADD D8, D7, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
FMUL D9, D8, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (25.0%)
FMADD D9, D6, D6, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
FCMPE D9, D5	1	0	0	0	0	0	0	1	0	0	0	2	1	scal (25.0%)
B.GE 41a280 <gasdev+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D9, #0	1	0	0	0	0	0	0	1	0	0	0	2	1	scal (25.0%)
B.EQ 41a280 <gasdev+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	gasdev
Source file and lines	random.c:26-48
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
6: multiply (3 inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	22
nb uops	22
loop length	88
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	10
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.75	2.75	4.00	2.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	2.75	2.75	4.00	2.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	20.00-50.00

Cycles summary

Front-end	2.75
Dispatch	4.00
DIV/SQRT	10.00-40.00
Data deps.	20.00-50.00
Overall L1	20.00-50.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41a280

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MUL X6, X13, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
UDIV X3, X6, X4	1	0	0	0	0	1	0	0	0	0	0	5-20	5-20	scal (25.0%)
UBFM X2, X3, #3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X7, X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
MUL X9, X8, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
SCVTF D0, X8	1	0	0	0	0	1	0	0	0	0	0	3	1	scal (25.0%)
UDIV X10, X9, X4	1	0	0	0	0	1	0	0	0	0	0	5-20	5-20	scal (25.0%)
FMUL D4, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (25.0%)
FMADD D6, D4, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
UBFM X11, X10, #3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X12, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X13, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SCVTF D8, X13	1	0	0	0	0	1	0	0	0	0	0	3	1	scal (25.0%)
FMUL D7, D8, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (25.0%)
FMADD D8, D7, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
FMUL D9, D8, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (25.0%)
FMADD D9, D6, D6, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
FCMPE D9, D5	1	0	0	0	0	0	0	1	0	0	0	2	1	scal (25.0%)
B.GE 41a280 <gasdev+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D9, #0	1	0	0	0	0	0	0	1	0	0	0	2	1	scal (25.0%)
B.EQ 41a280 <gasdev+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code