OV - exec - Loop 104

	Loop Id: 104	Module: exec	Source: timestep.c:71-78	Coverage: 0.70%

0x41a6d0 UBFM	W20, W9, #26, #25

0x41a6d4 LDR	W6, [X12, X9,LSL #2]

0x41a6d8 CMP	W6, #0

0x41a6dc B.LE	41a8dc

0x41a6e0 LDR	X4, [X13, #32]

0x41a6e4 ADD	X5, X8, #48

0x41a6e8 LDP	X21, X19, [X4, #32]

0x41a6ec ADD	X7, X21, X5

0x41a6f0 ADD	X16, X19, X8

0x41a6f4 ADD	X15, X21, X8

0x41a6f8 ADD	X17, X19, X5

0x41a6fc CMP	X16, X7

0x41a700 CCMP	X15, X17, #2, #3

0x41a704 CCMP	W6, #1, #4, #2

0x41a708 B.EQ	41a8fc

0x41a70c UBFM	W18, W6, #1, #31

0x41a710 ADD	X11, X15, #48

0x41a714 SUB	W0, W18, #1

0x41a718 MOVZ	X3, #43691

0x41a71c MOVK	X3, #43690

0x41a720 ORR	X1, XZR, X15

0x41a724 UMADDL	X4, W0, W14, X11

0x41a728 MOVK	X3, #43690

0x41a72c ORR	X2, XZR, X16

0x41a730 MOVK	X3, #2730

0x41a734 SUB	X5, X4, X15

0x41a738 SUB	X7, X5, #48

0x41a73c UBFM	X17, X7, #4, #63

0x41a740 MUL	X18, X17, X3

0x41a744 ADD	X0, X18, #1

0x41a748 ANDS	X3, X0, #0x3

0x41a74c B.EQ	41a7ec

0x41a750 CMP	X3, #1

0x41a754 B.EQ	41a7b8

0x41a758 CMP	X3, #2

0x41a75c B.EQ	41a78c

0x41a760 LDP	Q1, Q6, [X16]

0x41a764 ORR	X1, XZR, X11

0x41a768 ADD	X2, X16, #48

0x41a76c LDP	Q4, Q2, [X15]

0x41a770 LDR	Q5, [X16, #32]

0x41a774 LDR	Q7, [X15, #32]

0x41a778 FMLA	V4.2D, V3.2D, V1.2D

0x41a77c FMLA	V2.2D, V3.2D, V6.2D

0x41a780 FMLA	V7.2D, V3.2D, V5.2D

0x41a784 STP	Q4, Q2, [X15]

0x41a788 STR	Q7, [X15, #32]

0x41a78c LDP	Q18, Q19, [X2]

0x41a790 ADD	X2, X2, #48

0x41a794 LDP	Q16, Q17, [X1]

0x41a798 LDUR	Q20, [X2, #496]

0x41a79c LDR	Q21, [X1, #32]

0x41a7a0 FMLA	V16.2D, V3.2D, V18.2D

0x41a7a4 FMLA	V17.2D, V3.2D, V19.2D

0x41a7a8 FMLA	V21.2D, V3.2D, V20.2D

0x41a7ac STP	Q16, Q17, [X1]

0x41a7b0 ADD	X1, X1, #48

0x41a7b4 STUR	Q21, [X1, #496]

0x41a7b8 LDP	Q24, Q25, [X2]

0x41a7bc ADD	X2, X2, #48

0x41a7c0 LDP	Q22, Q23, [X1]

0x41a7c4 LDUR	Q26, [X2, #496]

0x41a7c8 LDR	Q27, [X1, #32]

0x41a7cc FMLA	V22.2D, V3.2D, V24.2D

0x41a7d0 FMLA	V23.2D, V3.2D, V25.2D

0x41a7d4 FMLA	V27.2D, V3.2D, V26.2D

0x41a7d8 STP	Q22, Q23, [X1]

0x41a7dc ADD	X1, X1, #48

0x41a7e0 STUR	Q27, [X1, #496]

0x41a7e4 CMP	X4, X1

0x41a7e8 B.EQ	41a894

  (106) 0x41a7ec LDP	Q30, Q31, [X2]

  (106) 0x41a7f0 ADD	X15, X2, #144

  (106) 0x41a7f4 ADD	X16, X1, #144

  (106) 0x41a7f8 LDP	Q28, Q29, [X1]

  (106) 0x41a7fc LDP	Q1, Q4, [X1, #32]

  (106) 0x41a800 LDR	Q2, [X2, #32]

  (106) 0x41a804 LDR	Q7, [X1, #64]

  (106) 0x41a808 LDR	Q17, [X1, #80]

  (106) 0x41a80c FMLA	V28.2D, V3.2D, V30.2D

  (106) 0x41a810 LDP	Q18, Q19, [X1, #96]

  (106) 0x41a814 FMLA	V29.2D, V3.2D, V31.2D

  (106) 0x41a818 LDR	Q23, [X1, #128]

  (106) 0x41a81c LDP	Q24, Q25, [X1, #144]

  (106) 0x41a820 FMLA	V1.2D, V3.2D, V2.2D

  (106) 0x41a824 STP	Q28, Q29, [X1]

  (106) 0x41a828 STR	Q1, [X1, #32]

  (106) 0x41a82c LDP	Q16, Q6, [X2, #48]

  (106) 0x41a830 LDR	Q5, [X2, #80]

  (106) 0x41a834 FMLA	V17.2D, V3.2D, V5.2D

  (106) 0x41a838 FMLA	V4.2D, V3.2D, V16.2D

  (106) 0x41a83c FMLA	V7.2D, V3.2D, V6.2D

  (106) 0x41a840 STR	Q17, [X1, #80]

  (106) 0x41a844 STP	Q4, Q7, [X1, #48]

  (106) 0x41a848 LDP	Q20, Q21, [X2, #96]

  (106) 0x41a84c LDR	Q22, [X2, #128]

  (106) 0x41a850 FMLA	V23.2D, V3.2D, V22.2D

  (106) 0x41a854 FMLA	V18.2D, V3.2D, V20.2D

  (106) 0x41a858 FMLA	V19.2D, V3.2D, V21.2D

  (106) 0x41a85c STR	Q23, [X1, #128]

  (106) 0x41a860 STP	Q18, Q19, [X1, #96]

  (106) 0x41a864 LDP	Q26, Q27, [X2, #144]

  (106) 0x41a868 ADD	X1, X1, #192

  (106) 0x41a86c ADD	X2, X2, #192

  (106) 0x41a870 LDR	Q28, [X15, #32]

  (106) 0x41a874 LDUR	Q29, [X1, #496]

  (106) 0x41a878 FMLA	V24.2D, V3.2D, V26.2D

  (106) 0x41a87c FMLA	V25.2D, V3.2D, V27.2D

  (106) 0x41a880 FMLA	V29.2D, V3.2D, V28.2D

  (106) 0x41a884 STUR	Q24, [X1, #464]

  (106) 0x41a888 STP	Q25, Q29, [X16, #16]

  (106) 0x41a88c CMP	X4, X1

  (106) 0x41a890 B.NE	41a7ec

0x41a894 AND	W11, W6, #0xfffffffe

0x41a898 ADD	W20, W11, W20

0x41a89c CMP	W6, W11

0x41a8a0 B.EQ	41a8dc

0x41a8a4 SMULL	X6, W20, W10

0x41a8a8 LDR	D30, [X19, X6]

0x41a8ac ADD	X4, X21, X6

0x41a8b0 ADD	X19, X19, X6

0x41a8b4 LDR	D31, [X21, X6]

0x41a8b8 FMADD	D2, D0, D30, D31

0x41a8bc STR	D2, [X21, X6]

0x41a8c0 LDP	D7, D1, [X4, #8]

0x41a8c4 LDR	D4, [X19, #8]

0x41a8c8 FMADD	D16, D0, D4, D7

0x41a8cc STR	D16, [X4, #8]

0x41a8d0 LDR	D6, [X19, #16]

0x41a8d4 FMADD	D5, D0, D6, D1

0x41a8d8 STR	D5, [X4, #16]

0x41a8dc ADD	X9, X9, #1

0x41a8e0 ADD	X8, X8, #1536

0x41a8e4 CMP	W30, W9

0x41a8e8 B.GT	41a6d0

0x41a8fc SUB	W5, W6, #1

0x41a900 ADD	X21, X21, #24

0x41a904 ADD	X7, X5, X9,LSL #6

0x41a908 MOVZ	X17, #43691

0x41a90c ORR	X0, XZR, X15

0x41a910 MOVK	X17, #43690

0x41a914 ORR	X1, XZR, X16

0x41a918 ADD	X18, X7, X7,LSL #1

0x41a91c MOVK	X17, #43690

0x41a920 MOVK	X17, #2730

0x41a924 ADD	X3, X21, X18,LSL #3

0x41a928 SUB	X2, X3, X15

0x41a92c SUB	X11, X2, #24

0x41a930 UBFM	X20, X11, #3, #63

0x41a934 MUL	X6, X20, X17

0x41a938 ADD	X19, X6, #1

0x41a93c ANDS	X4, X19, #0x3

0x41a940 B.EQ	41a9f8

0x41a944 CMP	X4, #1

0x41a948 B.EQ	41a9bc

0x41a94c CMP	X4, #2

0x41a950 B.EQ	41a988

0x41a954 LDP	D17, D18, [X15]

0x41a958 ADD	X0, X15, #24

0x41a95c ADD	X1, X16, #24

0x41a960 LDR	D20, [X16]

0x41a964 LDR	D19, [X15, #16]

0x41a968 FMADD	D21, D0, D20, D17

0x41a96c STR	D21, [X15]

0x41a970 LDR	D22, [X16, #8]

0x41a974 FMADD	D23, D22, D0, D18

0x41a978 STR	D23, [X15, #8]

0x41a97c LDR	D24, [X16, #16]

0x41a980 FMADD	D25, D0, D24, D19

0x41a984 STR	D25, [X15, #16]

0x41a988 LDP	D26, D27, [X0]

0x41a98c ADD	X1, X1, #24

0x41a990 ADD	X0, X0, #24

0x41a994 LDUR	D29, [X1, #488]

0x41a998 LDUR	D28, [X0, #504]

0x41a99c FMADD	D30, D0, D29, D26

0x41a9a0 STUR	D30, [X0, #488]

0x41a9a4 LDUR	D31, [X1, #496]

0x41a9a8 FMADD	D2, D31, D0, D27

0x41a9ac STUR	D2, [X0, #496]

0x41a9b0 LDUR	D7, [X1, #504]

0x41a9b4 FMADD	D1, D0, D7, D28

0x41a9b8 STUR	D1, [X0, #504]

0x41a9bc LDP	D4, D16, [X0]

0x41a9c0 ADD	X0, X0, #24

0x41a9c4 ADD	X1, X1, #24

0x41a9c8 LDUR	D5, [X1, #488]

0x41a9cc LDUR	D6, [X0, #504]

0x41a9d0 FMADD	D17, D0, D5, D4

0x41a9d4 STUR	D17, [X0, #488]

0x41a9d8 LDUR	D18, [X1, #496]

0x41a9dc FMADD	D19, D18, D0, D16

0x41a9e0 STUR	D19, [X0, #496]

0x41a9e4 LDUR	D20, [X1, #504]

0x41a9e8 FMADD	D21, D0, D20, D6

0x41a9ec STUR	D21, [X0, #504]

0x41a9f0 CMP	X3, X0

0x41a9f4 B.EQ	41a8dc

  (105) 0x41a9f8 LDR	D25, [X1]

  (105) 0x41a9fc ADD	X16, X0, #72

  (105) 0x41aa00 ADD	X15, X1, #72

  (105) 0x41aa04 ADD	X1, X1, #96

  (105) 0x41aa08 LDP	D22, D23, [X0]

  (105) 0x41aa0c ADD	X0, X0, #96

  (105) 0x41aa10 LDUR	D24, [X0, #432]

  (105) 0x41aa14 LDUR	D27, [X0, #440]

  (105) 0x41aa18 FMADD	D26, D0, D25, D22

  (105) 0x41aa1c LDUR	D16, [X0, #448]

  (105) 0x41aa20 LDUR	D1, [X0, #456]

  (105) 0x41aa24 LDUR	D18, [X0, #464]

  (105) 0x41aa28 LDUR	D21, [X0, #472]

  (105) 0x41aa2c LDUR	D22, [X0, #480]

  (105) 0x41aa30 STUR	D26, [X0, #416]

  (105) 0x41aa34 LDUR	D28, [X1, #424]

  (105) 0x41aa38 FMADD	D29, D28, D0, D23

  (105) 0x41aa3c STUR	D29, [X0, #424]

  (105) 0x41aa40 LDUR	D30, [X1, #432]

  (105) 0x41aa44 FMADD	D31, D0, D30, D24

  (105) 0x41aa48 STUR	D31, [X0, #432]

  (105) 0x41aa4c LDUR	D2, [X1, #440]

  (105) 0x41aa50 FMADD	D7, D0, D2, D27

  (105) 0x41aa54 LDUR	D27, [X0, #488]

  (105) 0x41aa58 STUR	D7, [X0, #440]

  (105) 0x41aa5c LDUR	D4, [X1, #448]

  (105) 0x41aa60 FMADD	D6, D4, D0, D16

  (105) 0x41aa64 STUR	D6, [X0, #448]

  (105) 0x41aa68 LDUR	D5, [X1, #456]

  (105) 0x41aa6c FMADD	D17, D0, D5, D1

  (105) 0x41aa70 STUR	D17, [X0, #456]

  (105) 0x41aa74 LDUR	D19, [X1, #464]

  (105) 0x41aa78 FMADD	D20, D0, D19, D18

  (105) 0x41aa7c STUR	D20, [X0, #464]

  (105) 0x41aa80 LDUR	D23, [X1, #472]

  (105) 0x41aa84 FMADD	D24, D23, D0, D21

  (105) 0x41aa88 STUR	D24, [X0, #472]

  (105) 0x41aa8c LDUR	D25, [X1, #480]

  (105) 0x41aa90 FMADD	D26, D0, D25, D22

  (105) 0x41aa94 STUR	D26, [X0, #480]

  (105) 0x41aa98 LDUR	D28, [X1, #488]

  (105) 0x41aa9c FMADD	D29, D0, D28, D27

  (105) 0x41aaa0 STUR	D29, [X0, #488]

  (105) 0x41aaa4 LDR	D30, [X16, #8]

  (105) 0x41aaa8 LDR	D31, [X15, #8]

  (105) 0x41aaac FMADD	D2, D31, D0, D30

  (105) 0x41aab0 STR	D2, [X16, #8]

  (105) 0x41aab4 LDR	D7, [X16, #16]

  (105) 0x41aab8 LDR	D16, [X15, #16]

  (105) 0x41aabc FMADD	D1, D0, D16, D7

  (105) 0x41aac0 STR	D1, [X16, #16]

  (105) 0x41aac4 CMP	X3, X0

  (105) 0x41aac8 B.NE	41a9f8

0x41aacc B	41a8dc

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Module
►98.36+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.18
CQA speedup if FP arith vectorized	1.32
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:71-71,timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.63
CQA cycles if no scalar integer	16.67
CQA cycles if FP arith vectorized	14.88
CQA cycles if fully vectorized	11.78
Front-end cycles	19.63
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	17.50
P3 cycles	17.50
P4 cycles	17.50
P5 cycles	17.50
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	9.75
P9 cycles	9.75
P10 cycles	17.67
P11 cycles	17.67
P12 cycles	17.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	157.00
Nb uops	157.00
Nb loads	NA
Nb stores	18.00
Nb stack references	0.00
FLOP/cycle	3.06
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	30.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.15
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	29.81
Vectorization ratio load	50.00
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	42.86
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.70
Vector-efficiency ratio load	46.88
Vector-efficiency ratio store	41.67
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	35.71
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.63

Metric	Value
CQA speedup if no scalar integer	1.18
CQA speedup if FP arith vectorized	1.32
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:71-71,timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.63
CQA cycles if no scalar integer	16.67
CQA cycles if FP arith vectorized	14.88
CQA cycles if fully vectorized	11.78
Front-end cycles	19.63
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	17.50
P3 cycles	17.50
P4 cycles	17.50
P5 cycles	17.50
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	9.75
P9 cycles	9.75
P10 cycles	17.67
P11 cycles	17.67
P12 cycles	17.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	157.00
Nb uops	157.00
Nb loads	NA
Nb stores	18.00
Nb stack references	0.00
FLOP/cycle	3.06
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	30.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.15
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	29.81
Vectorization ratio load	50.00
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	42.86
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.70
Vector-efficiency ratio load	46.88
Vector-efficiency ratio store	41.67
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	35.71
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:71-78
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71,74-78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=22
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 22 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.63 to 16.67 cycles (1.18x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 19.63 to 11.78 cycles (1.67x speedup).

Details

29% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
42% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 30 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

30: addition or subtraction (all inside FMA instructions)
30: multiply (all inside FMA instructions)

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 20.00 FP operations per loaded or stored byte.

General properties

nb instructions	157
nb uops	157
loop length	628
used w registers	10
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	23
used q registers	18
used v registers	19
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.63 cycles
front end	19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	17.50	17.50	17.50	17.50	9.75	9.75	9.75	9.75	17.67	17.67	17.67	0.00	0.00
cycles	6.50	6.50	17.50	17.50	17.50	17.50	9.75	9.75	9.75	9.75	17.67	17.67	17.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.63
Dispatch	17.67
Overall L1	19.63

Vectorization ratios

INT

all	26%
load	50%
store	33%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	42%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	29%
load	50%
store	33%
mul	0%
add-sub	0%
fma	42%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	35%
load	46%
store	41%
mul	25%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	35%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	35%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	35%
load	46%
store	41%
mul	25%
add-sub	22%
fma	35%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.63 cycles. At this rate:

0% of peak load performance is reached (0.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.63 to 17.67 cycles (1.11x speedup).

ASM code

In the binary file, the address of the loop is: 41a6d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
UBFM W20, W9, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W6, [X12, X9,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 41a8dc <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X13, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X5, X8, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X21, X19, [X4, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
ADD X7, X21, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X19, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X15, X17, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP W6, #1, #4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.EQ 41a8fc <advanceVelocity._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W18, W6, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X11, X15, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W0, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X3, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UMADDL X4, W0, W14, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MOVK X3, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X3, #2730	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X4, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X7, X5, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X17, X7, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X18, X17, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X0, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X3, X0, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a7ec <advanceVelocity._omp_fn.0+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a7b8 <advanceVelocity._omp_fn.0+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a78c <advanceVelocity._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q1, Q6, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR X1, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X16, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q4, Q2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR Q5, [X16, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q7, [X15, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V4.2D, V3.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V2.2D, V3.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V7.2D, V3.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q4, Q2, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q7, [X15, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDP Q18, Q19, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X2, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q16, Q17, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDUR Q20, [X2, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q21, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V16.2D, V3.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V17.2D, V3.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V21.2D, V3.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q16, Q17, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q21, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDP Q24, Q25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X2, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q22, Q23, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDUR Q26, [X2, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q27, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V22.2D, V3.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V23.2D, V3.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V27.2D, V3.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q22, Q23, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q27, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
CMP X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a894 <advanceVelocity._omp_fn.0+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W11, W6, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W20, W11, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W6, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 41a8dc <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SMULL X6, W20, W10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR D30, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X4, X21, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X19, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X21, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D2, D0, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D2, [X21, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D7, D1, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR D4, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D16, D0, D4, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D16, [X4, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D6, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D5, D0, D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D5, [X4, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W30, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GT 41a6d0 <advanceVelocity._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X21, X21, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X5, X9,LSL #6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MOVZ X17, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X17, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X7, X7,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X17, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X17, #2730	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X21, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X3, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X20, X11, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X6, X20, X17	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X19, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X4, X19, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a9f8 <advanceVelocity._omp_fn.0+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a9bc <advanceVelocity._omp_fn.0+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a988 <advanceVelocity._omp_fn.0+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D17, D18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X0, X15, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X16, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D21, D0, D20, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D21, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D22, [X16, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D23, D22, D0, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D23, [X15, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D24, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D25, D0, D24, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D25, [X15, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D26, D27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D29, [X1, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDUR D28, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D30, D0, D29, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D30, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D31, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D2, D31, D0, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D2, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D7, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D1, D0, D7, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D1, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D4, D16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D5, [X1, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDUR D6, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D17, D0, D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D17, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D18, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D19, D18, D0, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D19, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D20, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D21, D0, D20, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D21, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a8dc <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41a8dc <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:71-78
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=22
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

29% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
42% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 30 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

30: addition or subtraction (all inside FMA instructions)
30: multiply (all inside FMA instructions)

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 20.00 FP operations per loaded or stored byte.

General properties

nb instructions	157
nb uops	157
loop length	628
used w registers	10
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	23
used q registers	18
used v registers	19
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.63 cycles
front end	19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	17.50	17.50	17.50	17.50	9.75	9.75	9.75	9.75	17.67	17.67	17.67	0.00	0.00
cycles	6.50	6.50	17.50	17.50	17.50	17.50	9.75	9.75	9.75	9.75	17.67	17.67	17.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.63
Dispatch	17.67
Overall L1	19.63

Vectorization ratios

INT

all	26%
load	50%
store	33%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	42%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	29%
load	50%
store	33%
mul	0%
add-sub	0%
fma	42%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	35%
load	46%
store	41%
mul	25%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	35%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	35%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	35%
load	46%
store	41%
mul	25%
add-sub	22%
fma	35%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.63 cycles. At this rate:

0% of peak load performance is reached (0.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 41a6d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
UBFM W20, W9, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W6, [X12, X9,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 41a8dc <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X13, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X5, X8, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X21, X19, [X4, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
ADD X7, X21, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X19, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X15, X17, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP W6, #1, #4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.EQ 41a8fc <advanceVelocity._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W18, W6, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X11, X15, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W0, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X3, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UMADDL X4, W0, W14, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MOVK X3, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X3, #2730	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X4, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X7, X5, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X17, X7, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X18, X17, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X0, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X3, X0, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a7ec <advanceVelocity._omp_fn.0+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a7b8 <advanceVelocity._omp_fn.0+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a78c <advanceVelocity._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q1, Q6, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR X1, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X16, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q4, Q2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR Q5, [X16, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q7, [X15, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V4.2D, V3.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V2.2D, V3.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V7.2D, V3.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q4, Q2, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q7, [X15, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDP Q18, Q19, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X2, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q16, Q17, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDUR Q20, [X2, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q21, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V16.2D, V3.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V17.2D, V3.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V21.2D, V3.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q16, Q17, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q21, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDP Q24, Q25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X2, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q22, Q23, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDUR Q26, [X2, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q27, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V22.2D, V3.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V23.2D, V3.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V27.2D, V3.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q22, Q23, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q27, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
CMP X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a894 <advanceVelocity._omp_fn.0+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W11, W6, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W20, W11, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W6, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 41a8dc <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SMULL X6, W20, W10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR D30, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X4, X21, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X19, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X21, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D2, D0, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D2, [X21, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D7, D1, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR D4, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D16, D0, D4, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D16, [X4, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D6, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D5, D0, D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D5, [X4, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W30, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GT 41a6d0 <advanceVelocity._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X21, X21, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X5, X9,LSL #6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MOVZ X17, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X17, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X7, X7,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X17, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X17, #2730	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X21, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X3, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X20, X11, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X6, X20, X17	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X19, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X4, X19, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a9f8 <advanceVelocity._omp_fn.0+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a9bc <advanceVelocity._omp_fn.0+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a988 <advanceVelocity._omp_fn.0+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D17, D18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X0, X15, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X16, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D21, D0, D20, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D21, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D22, [X16, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D23, D22, D0, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D23, [X15, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D24, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D25, D0, D24, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D25, [X15, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D26, D27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D29, [X1, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDUR D28, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D30, D0, D29, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D30, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D31, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D2, D31, D0, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D2, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D7, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D1, D0, D7, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D1, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D4, D16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D5, [X1, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDUR D6, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D17, D0, D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D17, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D18, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D19, D18, D0, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D19, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D20, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D21, D0, D20, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D21, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a8dc <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41a8dc <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code