OV - exec - Loop 109

	Loop Id: 109	Module: exec	Source: timestep.c:110-116	Coverage: 0.10%

0x41ab8c LD3D	{Z1.D, Z2.D, Z3.D}, P1/Z, [X20, MUL VL]    [1]

0x41ab90 LD1SW	{Z0.D}, P1/Z, [X18, X30,LSL #2]    [3]

0x41ab94 FMUL	Z2.D, Z2.D, Z2.D

0x41ab98 ADD	X30, X30, X7

0x41ab9c LSL	Z4.D, Z0.D, #4

0x41aba0 FMLA	Z2.D, P0/M, Z1.D, Z1.D

0x41aba4 LD1D	{Z16.D}, P1/Z, [X15, Z4.D]    [2]

0x41aba8 MOVPRFX	Z1, Z2

0x41abac FMLA	Z1.D, P0/M, Z3.D, Z3.D

0x41abb0 FDIVR	Z16.D, P0/M, Z16.D, Z6.D

0x41abb4 ADD	X20, X20, X6

0x41abb8 FMUL	Z7.D, Z16.D, Z1.D

0x41abbc FADDA	D5, P1, D5, Z7.D

0x41abc0 WHILELO	P1.D, W30, W13

0x41abc4 B.NE	41ab8c

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 116

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

Coverage (%)	Name	Module
►99.26+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.05 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.13
Bottlenecks	P6, P8,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00 - 14.08
CQA cycles if no scalar integer	8.00 - 14.08
CQA cycles if FP arith vectorized	8.00 - 14.08
CQA cycles if fully vectorized	7.60 - 14.08
Front-end cycles	1.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.00 - 2.27
Nb FLOP add-sub	4.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.54 - 8.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	81.82
Vectorization ratio load	66.67
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	93.18
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.05 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.13
Bottlenecks	P6, P8,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00 - 14.08
CQA cycles if no scalar integer	8.00 - 14.08
CQA cycles if FP arith vectorized	8.00 - 14.08
CQA cycles if fully vectorized	7.60 - 14.08
Front-end cycles	1.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	6.99 - 14.08
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.00 - 2.27
Nb FLOP add-sub	4.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.54 - 8.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	81.82
Vectorization ratio load	66.67
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	93.18
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

81% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.08 to 8.00 cycles (1.76x speedup).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

12: addition or subtraction (8 inside FMA instructions)
16: multiply (8 inside FMA instructions)
4: divide

The binary loop is loading 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	15
nb uops	15
loop length	60
used w registers	2
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	1
used q registers	0
used v registers	0
used z registers	8
nb stack references	0
ADD-SUB / MUL ratio	0.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.88 cycles
front end	1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	4.50	4.50	0.00	0.00	1.50	1.50	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	4.50	4.50	2.50	2.50	1.50	1.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	1.88
Dispatch	4.50
DIV/SQRT	6.99-14.08
Data deps.	8.00
Overall L1	8.00-14.08

Vectorization ratios

INT

all	60%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	81%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	85%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	93%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.08 cycles. At this rate:

4% of peak load performance is reached (4.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41ab8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD3D {Z1.D, Z2.D, Z3.D}, P1/Z, [X20, MUL VL]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	11	3.00	scal (25.0%)
LD1SW {Z0.D}, P1/Z, [X18, X30,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
ADD X30, X30, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LSL Z4.D, Z0.D, #4	1	0	0	0	0	0	0	0	1	0	0	2	1	vect (100.0%)
FMLA Z2.D, P0/M, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z16.D}, P1/Z, [X15, Z4.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z1, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z1.D, P0/M, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FDIVR Z16.D, P0/M, Z16.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADD X20, X20, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z7.D, Z16.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADDA D5, P1, D5, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
WHILELO P1.D, W30, W13	1	0	0	0	0	1	0	0	0	0	0	3	2	N/A
B.NE 41ab8c <kineticEnergy._omp_fn.0+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 93% of vector register length is used (average across all VPU instructions).

Details

81% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.08 to 8.00 cycles (1.76x speedup).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

12: addition or subtraction (8 inside FMA instructions)
16: multiply (8 inside FMA instructions)
4: divide

The binary loop is loading 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	15
nb uops	15
loop length	60
used w registers	2
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	1
used q registers	0
used v registers	0
used z registers	8
nb stack references	0
ADD-SUB / MUL ratio	0.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.88 cycles
front end	1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	4.50	4.50	0.00	0.00	1.50	1.50	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	4.50	4.50	2.50	2.50	1.50	1.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-14.08
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	1.88
Dispatch	4.50
DIV/SQRT	6.99-14.08
Data deps.	8.00
Overall L1	8.00-14.08

Vectorization ratios

INT

all	60%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	81%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	85%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	93%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.08 cycles. At this rate:

4% of peak load performance is reached (4.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41ab8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD3D {Z1.D, Z2.D, Z3.D}, P1/Z, [X20, MUL VL]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	11	3.00	scal (25.0%)
LD1SW {Z0.D}, P1/Z, [X18, X30,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
ADD X30, X30, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LSL Z4.D, Z0.D, #4	1	0	0	0	0	0	0	0	1	0	0	2	1	vect (100.0%)
FMLA Z2.D, P0/M, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1D {Z16.D}, P1/Z, [X15, Z4.D]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z1, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z1.D, P0/M, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FDIVR Z16.D, P0/M, Z16.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADD X20, X20, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
FMUL Z7.D, Z16.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FADDA D5, P1, D5, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50	vect (100.0%)
WHILELO P1.D, W30, W13	1	0	0	0	0	1	0	0	0	0	0	3	2	N/A
B.NE 41ab8c <kineticEnergy._omp_fn.0+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code