OV - exec - Loop 63

	Loop Id: 63	Module: exec	Source: haloExchange.c:623-628	Coverage: 0.97%

0x415180 LDR	D24, [X13, X4,LSL #3]    [12]

0x415184 ADD	X5, X2, #48

0x415188 ADD	X7, X2, #52

0x41518c ADD	X30, X2, #56

0x415190 ADD	X18, X2, #72

0x415194 LDP	Q26, Q27, [X12]    [11]

0x415198 ADD	X17, X2, #80

0x41519c ADD	X15, X2, #96

0x4151a0 LDR	D25, [X14, X4,LSL #3]    [13]

0x4151a4 ADD	X4, X4, #1

0x4151a8 LDR	Q28, [X12, #32]    [11]

0x4151ac STUR	S24, [X2, #504]    [16]

0x4151b0 ST1	{V24.S[1]}, [X5]    [3]

0x4151b4 STUR	S25, [X2, #508]    [16]

0x4151b8 ADD	X5, X12, #48

0x4151bc ST1	{V25.S[1]}, [X7]    [6]

0x4151c0 STR	Q26, [X2]    [16]

0x4151c4 ADD	X7, X2, #160

0x4151c8 STR	D27, [X2, #16]    [16]

0x4151cc ST1	{V27.D[1]}, [X30]    [9]

0x4151d0 STR	D28, [X2, #64]    [16]

0x4151d4 ADD	X30, X2, #164

0x4151d8 ST1	{V28.D[1]}, [X18]    [20]

0x4151dc LDP	Q30, Q31, [X11]    [10]

0x4151e0 ADD	X18, X2, #168

0x4151e4 LDR	Q3, [X11, #32]    [10]

0x4151e8 LDR	D29, [X13, X4,LSL #3]    [12]

0x4151ec LDR	D2, [X14, X4,LSL #3]    [13]

0x4151f0 ADD	X4, X4, #1

0x4151f4 STUR	Q30, [X2, #24]    [16]

0x4151f8 STR	D31, [X2, #40]    [16]

0x4151fc ST1	{V31.D[1]}, [X17]    [18]

0x415200 STR	D3, [X2, #88]    [16]

0x415204 ADD	X17, X2, #184

0x415208 ST1	{V3.D[1]}, [X15]    [14]

0x41520c LDP	Q4, Q1, [X12, #48]    [11]

0x415210 ADD	X15, X11, #48

0x415214 ADD	X12, X12, #96

0x415218 STR	S29, [X2, #104]    [16]

0x41521c LDR	Q0, [X5, #32]    [2]

0x415220 ADD	X5, X2, #192

0x415224 ST1	{V29.S[1]}, [X7]    [5]

0x415228 STR	S2, [X2, #108]    [16]

0x41522c ADD	X7, X2, #208

0x415230 ADD	X2, X2, #224

0x415234 ST1	{V2.S[1]}, [X30]    [8]

0x415238 STUR	Q4, [X2, #400]    [15]

0x41523c STUR	D1, [X2, #416]    [15]

0x415240 ST1	{V1.D[1]}, [X18]    [19]

0x415244 STUR	D0, [X2, #464]    [15]

0x415248 ST1	{V0.D[1]}, [X17]    [17]

0x41524c LDP	Q5, Q6, [X11, #48]    [10]

0x415250 ADD	X11, X11, #96

0x415254 LDR	Q7, [X15, #32]    [7]

0x415258 STUR	Q5, [X2, #424]    [15]

0x41525c STUR	D6, [X2, #440]    [15]

0x415260 ST1	{V6.D[1]}, [X5]    [1]

0x415264 STUR	D7, [X2, #488]    [15]

0x415268 ST1	{V7.D[1]}, [X7]    [4]

0x41526c CMP	W16, W4

0x415270 B.HI	415180

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 623 - 628

--------------------------------------------------------------------------------

623:       tmp[iTmp].gid  = atoms->gid[ii];

624:       tmp[iTmp].type = atoms->iSpecies[ii];

625:       tmp[iTmp].rx =   atoms->r[ii][0];

626:       tmp[iTmp].ry =   atoms->r[ii][1];

627:       tmp[iTmp].rz =   atoms->r[ii][2];

628:       tmp[iTmp].px =   atoms->p[ii][0];

Coverage (%)	Name	Source Location	Module
►13.74+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►13.08+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.34+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.12+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.98+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.83+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.76+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.46+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P6, P7, P10, P11,
Function	sortAtomsInCell
Source	haloExchange.c:623-628
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	5.00
Front-end cycles	7.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	12.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	61.00
Nb loads	NA
Nb stores	28.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.57
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	204.00
Stride 0	0.00
Stride 1	0.00
Stride n	5.00
Stride unknown	14.00
Stride indirect	0.00
Vectorization ratio all	30.00
Vectorization ratio load	66.67
Vectorization ratio store	14.29
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	35.00
Vector-efficiency ratio load	58.33
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P6, P7, P10, P11,
Function	sortAtomsInCell
Source	haloExchange.c:623-628
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	5.00
Front-end cycles	7.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	12.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	61.00
Nb loads	NA
Nb stores	28.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.57
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	204.00
Stride 0	0.00
Stride 1	0.00
Stride n	5.00
Stride unknown	14.00
Stride indirect	0.00
Vectorization ratio all	30.00
Vectorization ratio load	66.67
Vectorization ratio store	14.29
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	35.00
Vector-efficiency ratio load	58.33
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:623-628
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:623-628.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 14.00 to 5.00 cycles (2.80x speedup).

Details

30% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)
Constant non-unit stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 204 bytes.

General properties

nb instructions	61
nb uops	61
loop length	244
used w registers	2
used x registers	12
used b registers	0
used h registers	0
used s registers	4
used d registers	12
used q registers	12
used v registers	12
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.63 cycles
front end	7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.00	5.00	5.00	5.00	14.00	14.00	0.00	0.00	14.00	14.00	12.00	0.00	0.00
cycles	0.50	0.50	5.00	5.00	5.00	5.00	14.00	14.00	0.00	0.00	14.00	14.00	12.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.63
Dispatch	14.00
Data deps.	2.00
Overall L1	14.00

Vectorization ratios

all	30%
load	66%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	35%
load	58%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

30% of peak store performance is reached (14.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 415180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR D24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X5, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X7, X2, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X30, X2, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X18, X2, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP Q26, Q27, [X12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X17, X2, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X15, X2, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D25, [X14, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q28, [X12, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STUR S24, [X2, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ST1 {V24.S[1]}, [X5]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
STUR S25, [X2, #508]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ADD X5, X12, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V25.S[1]}, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
STR Q26, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X7, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR D27, [X2, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V27.D[1]}, [X30]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STR D28, [X2, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X30, X2, #164	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V28.D[1]}, [X18]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
LDP Q30, Q31, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X18, X2, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q3, [X11, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR D29, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D2, [X14, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STUR Q30, [X2, #24]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR D31, [X2, #40]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V31.D[1]}, [X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STR D3, [X2, #88]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X17, X2, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V3.D[1]}, [X15]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
LDP Q4, Q1, [X12, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X15, X11, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR S29, [X2, #104]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
LDR Q0, [X5, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X5, X2, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V29.S[1]}, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
STR S2, [X2, #108]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ADD X7, X2, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V2.S[1]}, [X30]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
STUR Q4, [X2, #400]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STUR D1, [X2, #416]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V1.D[1]}, [X18]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D0, [X2, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V0.D[1]}, [X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
LDP Q5, Q6, [X11, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X11, X11, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q7, [X15, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STUR Q5, [X2, #424]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STUR D6, [X2, #440]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V6.D[1]}, [X5]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D7, [X2, #488]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V7.D[1]}, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
CMP W16, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.HI 415180 <sortAtomsInCell+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	sortAtomsInCell
Source file and lines	haloExchange.c:623-628
Module	exec

gain
potential
hint
expert

Vectorization

Details

30% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)
Constant non-unit stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 204 bytes.

General properties

nb instructions	61
nb uops	61
loop length	244
used w registers	2
used x registers	12
used b registers	0
used h registers	0
used s registers	4
used d registers	12
used q registers	12
used v registers	12
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.63 cycles
front end	7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.00	5.00	5.00	5.00	14.00	14.00	0.00	0.00	14.00	14.00	12.00	0.00	0.00
cycles	0.50	0.50	5.00	5.00	5.00	5.00	14.00	14.00	0.00	0.00	14.00	14.00	12.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.63
Dispatch	14.00
Data deps.	2.00
Overall L1	14.00

Vectorization ratios

all	30%
load	66%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	35%
load	58%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

30% of peak store performance is reached (14.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 415180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR D24, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X5, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X7, X2, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X30, X2, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X18, X2, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP Q26, Q27, [X12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X17, X2, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X15, X2, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D25, [X14, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q28, [X12, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STUR S24, [X2, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ST1 {V24.S[1]}, [X5]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
STUR S25, [X2, #508]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ADD X5, X12, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V25.S[1]}, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
STR Q26, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X7, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR D27, [X2, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V27.D[1]}, [X30]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STR D28, [X2, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X30, X2, #164	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V28.D[1]}, [X18]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
LDP Q30, Q31, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X18, X2, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q3, [X11, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR D29, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D2, [X14, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STUR Q30, [X2, #24]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR D31, [X2, #40]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V31.D[1]}, [X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STR D3, [X2, #88]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X17, X2, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V3.D[1]}, [X15]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
LDP Q4, Q1, [X12, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X15, X11, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR S29, [X2, #104]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
LDR Q0, [X5, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X5, X2, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V29.S[1]}, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
STR S2, [X2, #108]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ADD X7, X2, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V2.S[1]}, [X30]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
STUR Q4, [X2, #400]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STUR D1, [X2, #416]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V1.D[1]}, [X18]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D0, [X2, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V0.D[1]}, [X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
LDP Q5, Q6, [X11, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X11, X11, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q7, [X15, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STUR Q5, [X2, #424]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STUR D6, [X2, #440]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V6.D[1]}, [X5]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D7, [X2, #488]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V7.D[1]}, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
CMP W16, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.HI 415180 <sortAtomsInCell+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code