OV - exec - Loop 91

0x418020 LDR	W17, [X21, X16,LSL #2]

0x418024 CMP	W30, #0

0x418028 B.LE	418188

0x41802c UBFM	W18, W16, #26, #25

0x418030 SUB	W3, W17, #1

0x418034 LDR	X6, [X22, #128]

0x418038 SBFM	X12, X18, #0, #31

0x41803c ADD	W17, W17, W13

0x418040 ADD	X4, X12, #1

0x418044 SBFM	X25, X18, #61, #31

0x418048 ADD	X5, X4, X3

0x41804c MOVZ	X14, #0

0x418050 UBFM	X12, X5, #61, #60

0x418054 LDR	X24, [X6, X16,LSL #3]

  (93) 0x418058 LDR	W8, [X24, X14,LSL #2]

  (93) 0x41805c TBNZ	W8, #31, 418348

  (93) 0x418060 LDR	W11, [X21, W8,SXTW #2]

  (93) 0x418064 CMP	W18, W17

  (93) 0x418068 B.GE	41817c

  (93) 0x41806c UBFM	W8, W8, #26, #25

  (93) 0x418070 SUB	W26, W11, #1

  (93) 0x418074 ADD	X0, X26, W8,SXTW

  (93) 0x418078 ADD	X1, X0, X0,LSL #1

  (93) 0x41807c ADD	W11, W11, W8

  (93) 0x418080 ORR	X4, XZR, X25

  (93) 0x418084 SMULL	X10, W8, W23

  (93) 0x418088 UBFM	X9, X1, #61, #60

    (94) 0x41808c CMP	W8, W11

    (94) 0x418090 B.GE	418170

    (94) 0x418094 LDR	X6, [X19, #32]

    (94) 0x418098 ADD	X5, X4, X4,LSL #1

    (94) 0x41809c LDR	X2, [X6, #24]

    (94) 0x4180a0 ADD	X3, X2, #24

    (94) 0x4180a4 ADD	X0, X2, X10

    (94) 0x4180a8 ADD	X3, X3, X9

    (94) 0x4180ac ADD	X1, X2, X5

    (94) 0x4180b0 SUB	X7, X3, X0

    (94) 0x4180b4 TBZ	W7, #3, 418100

    (94) 0x4180b8 LDR	D4, [X2, X5]

    (94) 0x4180bc LDR	D1, [X2, X10]

    (94) 0x4180c0 LDP	D0, D2, [X0, #8]

    (94) 0x4180c4 LDP	D3, D23, [X1, #8]

    (94) 0x4180c8 FSUB	D27, D4, S1

    (94) 0x4180cc FSUB	D28, D3, S0

    (94) 0x4180d0 FSUB	D29, D23, S2

    (94) 0x4180d4 FMADD	D24, D27, D27, D6

    (94) 0x4180d8 FMADD	D25, D28, D28, D24

    (94) 0x4180dc FMADD	D26, D29, D29, D25

    (94) 0x4180e0 FCMPE	D5, D26

    (94) 0x4180e4 B.GE	4182b8

    (94) 0x4180e8 ADD	X0, X0, #24

    (94) 0x4180ec CMP	X0, X3

    (94) 0x4180f0 B.EQ	418170

    (94) 0x4180f4 HINT	#0

    (94) 0x4180f8 HINT	#0

    (94) 0x4180fc HINT	#0

      (95) 0x418100 LDP	D23, D24, [X0]

      (95) 0x418104 LDP	D25, D3, [X1]

      (95) 0x418108 LDR	D2, [X0, #16]

      (95) 0x41810c LDR	D27, [X1, #16]

      (95) 0x418110 FSUB	D30, D25, S23

      (95) 0x418114 FSUB	D31, D3, S24

      (95) 0x418118 FSUB	D1, D27, S2

      (95) 0x41811c FMADD	D26, D30, D30, D6

      (95) 0x418120 FMADD	D4, D31, D31, D26

      (95) 0x418124 FMADD	D0, D1, D1, D4

      (95) 0x418128 FCMPE	D5, D0

      (95) 0x41812c B.GE	418248

      (95) 0x418130 LDP	D26, D3, [X1]

      (95) 0x418134 ADD	X2, X0, #24

      (95) 0x418138 LDR	D25, [X0, #24]

      (95) 0x41813c LDP	D0, D28, [X2, #8]

      (95) 0x418140 LDR	D27, [X1, #16]

      (95) 0x418144 FSUB	D4, D26, S25

      (95) 0x418148 FSUB	D29, D3, S0

      (95) 0x41814c FSUB	D30, D27, S28

      (95) 0x418150 FMADD	D23, D4, D4, D6

      (95) 0x418154 FMADD	D24, D29, D29, D23

      (95) 0x418158 FMADD	D2, D30, D30, D24

      (95) 0x41815c FCMPE	D5, D2

      (95) 0x418160 B.GE	4181d8

      (95) 0x418164 ADD	X0, X2, #24

      (95) 0x418168 CMP	X0, X3

      (95) 0x41816c B.NE	418100

    (94) 0x418170 ADD	X4, X4, #8

    (94) 0x418174 CMP	X4, X12

    (94) 0x418178 B.NE	41808c

  (93) 0x41817c ADD	X14, X14, #1

  (93) 0x418180 CMP	W30, W14

  (93) 0x418184 B.GT	418058

0x418188 ADD	X16, X16, #1

0x41818c ADD	W13, W13, #64

0x418190 CMP	W15, W16

0x418194 B.GT	418020

      (95) 0x4181d8 FCMPE	D2, #0

      (95) 0x4181dc B.GT	4181e4

      (95) 0x4181e0 B	418164

      (95) 0x4181e4 FDIV	D31, D17, D2

      (95) 0x4181e8 LDP	X7, X26, [X6, #40]

      (95) 0x4181ec FMUL	D1, D8, D22

      (95) 0x4181f0 LDR	D2, [X26, X4]

      (95) 0x4181f4 ADD	X0, X7, X5

      (95) 0x4181f8 FMUL	D25, D31, D31

      (95) 0x4181fc FMUL	D26, D25, D31

      (95) 0x418200 FMUL	D3, D26, D19

      (95) 0x418204 FMADD	D27, D3, D21, D20

      (95) 0x418208 FSUB	D0, D3, S17

      (95) 0x41820c FMUL	D28, D1, D3

      (95) 0x418210 FNMSUB	D23, D0, D3, D18

      (95) 0x418214 FMUL	D24, D28, D31

      (95) 0x418218 FMADD	D1, D23, D16, D2

      (95) 0x41821c FMADD	D7, D23, D16, D7

      (95) 0x418220 FMUL	D31, D27, D24

      (95) 0x418224 STR	D1, [X26, X4]

      (95) 0x418228 LDR	D25, [X7, X5]

      (95) 0x41822c FMSUB	D4, D31, D4, D25

      (95) 0x418230 STR	D4, [X7, X5]

      (95) 0x418234 LDP	D26, D27, [X0, #8]

      (95) 0x418238 FMSUB	D29, D31, D29, D26

      (95) 0x41823c FMSUB	D30, D31, D30, D27

      (95) 0x418240 STP	D29, D30, [X0, #8]

      (95) 0x418244 B	418164

      (95) 0x418248 FCMPE	D0, #0

      (95) 0x41824c B.GT	418254

      (95) 0x418250 B	418130

      (95) 0x418254 FDIV	D28, D17, D0

      (95) 0x418258 FMUL	D29, D8, D22

      (95) 0x41825c LDP	X7, X26, [X6, #40]

      (95) 0x418260 ADD	X2, X7, X5

      (95) 0x418264 FMUL	D23, D28, D28

      (95) 0x418268 FMUL	D24, D23, D28

      (95) 0x41826c FMUL	D2, D24, D19

      (95) 0x418270 FMADD	D3, D2, D21, D20

      (95) 0x418274 FMUL	D26, D29, D2

      (95) 0x418278 FSUB	D25, D2, S17

      (95) 0x41827c FMUL	D27, D26, D28

      (95) 0x418280 LDR	D28, [X26, X4]

      (95) 0x418284 FNMSUB	D4, D25, D2, D18

      (95) 0x418288 FMADD	D7, D4, D16, D7

      (95) 0x41828c FMADD	D29, D4, D16, D28

      (95) 0x418290 FMUL	D0, D3, D27

      (95) 0x418294 STR	D29, [X26, X4]

      (95) 0x418298 LDR	D23, [X7, X5]

      (95) 0x41829c FMSUB	D30, D0, D30, D23

      (95) 0x4182a0 STR	D30, [X7, X5]

      (95) 0x4182a4 LDP	D24, D2, [X2, #8]

      (95) 0x4182a8 FMSUB	D31, D0, D31, D24

      (95) 0x4182ac FMSUB	D1, D0, D1, D2

      (95) 0x4182b0 STP	D31, D1, [X2, #8]

      (95) 0x4182b4 B	418130

    (94) 0x4182b8 FCMPE	D26, #0

    (94) 0x4182bc B.GT	4182c4

    (94) 0x4182c0 B	4180e8

    (94) 0x4182c4 FDIV	D30, D17, D26

    (94) 0x4182c8 LDP	X7, X26, [X6, #40]

    (94) 0x4182cc FMUL	D31, D8, D22

    (94) 0x4182d0 LDR	D26, [X26, X4]

    (94) 0x4182d4 ADD	X2, X7, X5

    (94) 0x4182d8 FMUL	D4, D30, D30

    (94) 0x4182dc FMUL	D1, D4, D30

    (94) 0x4182e0 FMUL	D0, D1, D19

    (94) 0x4182e4 FMADD	D3, D0, D21, D20

    (94) 0x4182e8 FSUB	D2, D0, S17

    (94) 0x4182ec FMUL	D23, D31, D0

    (94) 0x4182f0 FNMSUB	D24, D2, D0, D18

    (94) 0x4182f4 FMUL	D25, D23, D30

    (94) 0x4182f8 FMADD	D31, D24, D16, D26

    (94) 0x4182fc FMADD	D7, D24, D16, D7

    (94) 0x418300 FMUL	D30, D3, D25

    (94) 0x418304 STR	D31, [X26, X4]

    (94) 0x418308 LDR	D4, [X7, X5]

    (94) 0x41830c FMSUB	D27, D30, D27, D4

    (94) 0x418310 STR	D27, [X7, X5]

    (94) 0x418314 LDP	D1, D0, [X2, #8]

    (94) 0x418318 FMSUB	D28, D30, D28, D1

    (94) 0x41831c FMSUB	D29, D30, D29, D0

    (94) 0x418320 STP	D28, D29, [X2, #8]

    (94) 0x418324 B	4180e8

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 175 - 216

--------------------------------------------------------------------------------

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
►97.37+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.63+	GOMP_parallel		libgomp.so.1.0.0
○	ljForce	ljForce.c:172	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks
Function	ljForce._omp_fn.1
Source	ljForce.c:175-175,ljForce.c:178-180,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.75
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	1.75
CQA cycles if fully vectorized	0.89
Front-end cycles	1.31
P0 cycles	0.75
P1 cycles	0.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	1.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.50
Nb uops	10.50
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.10
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.31
Vector-efficiency ratio load	15.63
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	29.17

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.51
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P2, P3, P4, P5,
Function	ljForce._omp_fn.1
Source	ljForce.c:175-175,ljForce.c:178-180,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	1.66
Front-end cycles	1.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	14.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.20
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	36.11
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	45.83

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P0, P1, P2, P3, P4, P5,
Function	ljForce._omp_fn.1
Source	ljForce.c:175-175,ljForce.c:178-180,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.13
Front-end cycles	0.88
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	7.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.00
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:175-216
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:175-191,197-216.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:175,178-180,187.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.75 to 0.89 cycles (1.96x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 3 bytes.

General properties

nb instructions	10.50
nb uops	10.50
loop length	42
used w registers	5.50
used x registers	7
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	1.31 cycles
front end	1.31 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.75	0.75	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	0.75	0.75	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.31
Dispatch	1.75
Data deps.	1.00
Overall L1	1.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	24%
load	15%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.75 cycles. At this rate:

2% of peak load performance is reached (2.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:175-216
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:175-191,197-216.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:175,178-180,187.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 36% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 1.66 cycles (1.51x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 3 bytes.

General properties

nb instructions	14
nb uops	14
loop length	56
used w registers	6
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.75 cycles
front end	1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00
cycles	0.50	0.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.75
Dispatch	2.50
Data deps.	1.00
Overall L1	2.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	36%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 418020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR W17, [X21, X16,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
CMP W30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.LE 418188 <ljForce._omp_fn.1+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W18, W16, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
SUB W3, W17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X6, [X22, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SBFM X12, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (100.0%)
ADD W17, W17, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ADD X4, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
SBFM X25, X18, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (100.0%)
ADD X5, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
MOVZ X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
UBFM X12, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
LDR X24, [X6, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:175-216
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:175-191,197-216.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:175,178-180,187.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.12 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 3 bytes.

General properties

nb instructions	7
nb uops	7
loop length	28
used w registers	5
used x registers	2
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	0.88 cycles
front end	0.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	0.88
Dispatch	1.00
Data deps.	1.00
Overall L1	1.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

3% of peak load performance is reached (3.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 418020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR W17, [X21, X16,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
CMP W30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (12.5%)
B.LE 418188 <ljForce._omp_fn.1+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ADD W13, W13, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
CMP W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
B.GT 418020 <ljForce._omp_fn.1+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code