OV - exec - Loop 94

	Loop Id: 94	Module: exec	Source: ljForce.c:187-216 [...]	Coverage: 6.54%

0x41808c CMP	W8, W11

0x418090 B.GE	418170

0x418094 LDR	X6, [X19, #32]

0x418098 ADD	X5, X4, X4,LSL #1

0x41809c LDR	X2, [X6, #24]

0x4180a0 ADD	X3, X2, #24

0x4180a4 ADD	X0, X2, X10

0x4180a8 ADD	X3, X3, X9

0x4180ac ADD	X1, X2, X5

0x4180b0 SUB	X7, X3, X0

0x4180b4 TBZ	W7, #3, 418100

0x4180b8 LDR	D4, [X2, X5]

0x4180bc LDR	D1, [X2, X10]

0x4180c0 LDP	D0, D2, [X0, #8]

0x4180c4 LDP	D3, D23, [X1, #8]

0x4180c8 FSUB	D27, D4, S1

0x4180cc FSUB	D28, D3, S0

0x4180d0 FSUB	D29, D23, S2

0x4180d4 FMADD	D24, D27, D27, D6

0x4180d8 FMADD	D25, D28, D28, D24

0x4180dc FMADD	D26, D29, D29, D25

0x4180e0 FCMPE	D5, D26

0x4180e4 B.GE	4182b8

0x4180e8 ADD	X0, X0, #24

0x4180ec CMP	X0, X3

0x4180f0 B.EQ	418170

0x4180f4 HINT	#0

0x4180f8 HINT	#0

0x4180fc HINT	#0

  (95) 0x418100 LDP	D23, D24, [X0]

  (95) 0x418104 LDP	D25, D3, [X1]

  (95) 0x418108 LDR	D2, [X0, #16]

  (95) 0x41810c LDR	D27, [X1, #16]

  (95) 0x418110 FSUB	D30, D25, S23

  (95) 0x418114 FSUB	D31, D3, S24

  (95) 0x418118 FSUB	D1, D27, S2

  (95) 0x41811c FMADD	D26, D30, D30, D6

  (95) 0x418120 FMADD	D4, D31, D31, D26

  (95) 0x418124 FMADD	D0, D1, D1, D4

  (95) 0x418128 FCMPE	D5, D0

  (95) 0x41812c B.GE	418248

  (95) 0x418130 LDP	D26, D3, [X1]

  (95) 0x418134 ADD	X2, X0, #24

  (95) 0x418138 LDR	D25, [X0, #24]

  (95) 0x41813c LDP	D0, D28, [X2, #8]

  (95) 0x418140 LDR	D27, [X1, #16]

  (95) 0x418144 FSUB	D4, D26, S25

  (95) 0x418148 FSUB	D29, D3, S0

  (95) 0x41814c FSUB	D30, D27, S28

  (95) 0x418150 FMADD	D23, D4, D4, D6

  (95) 0x418154 FMADD	D24, D29, D29, D23

  (95) 0x418158 FMADD	D2, D30, D30, D24

  (95) 0x41815c FCMPE	D5, D2

  (95) 0x418160 B.GE	4181d8

  (95) 0x418164 ADD	X0, X2, #24

  (95) 0x418168 CMP	X0, X3

  (95) 0x41816c B.NE	418100

0x418170 ADD	X4, X4, #8

0x418174 CMP	X4, X12

0x418178 B.NE	41808c

  (95) 0x4181d8 FCMPE	D2, #0

  (95) 0x4181dc B.GT	4181e4

  (95) 0x4181e0 B	418164

  (95) 0x4181e4 FDIV	D31, D17, D2

  (95) 0x4181e8 LDP	X7, X26, [X6, #40]

  (95) 0x4181ec FMUL	D1, D8, D22

  (95) 0x4181f0 LDR	D2, [X26, X4]

  (95) 0x4181f4 ADD	X0, X7, X5

  (95) 0x4181f8 FMUL	D25, D31, D31

  (95) 0x4181fc FMUL	D26, D25, D31

  (95) 0x418200 FMUL	D3, D26, D19

  (95) 0x418204 FMADD	D27, D3, D21, D20

  (95) 0x418208 FSUB	D0, D3, S17

  (95) 0x41820c FMUL	D28, D1, D3

  (95) 0x418210 FNMSUB	D23, D0, D3, D18

  (95) 0x418214 FMUL	D24, D28, D31

  (95) 0x418218 FMADD	D1, D23, D16, D2

  (95) 0x41821c FMADD	D7, D23, D16, D7

  (95) 0x418220 FMUL	D31, D27, D24

  (95) 0x418224 STR	D1, [X26, X4]

  (95) 0x418228 LDR	D25, [X7, X5]

  (95) 0x41822c FMSUB	D4, D31, D4, D25

  (95) 0x418230 STR	D4, [X7, X5]

  (95) 0x418234 LDP	D26, D27, [X0, #8]

  (95) 0x418238 FMSUB	D29, D31, D29, D26

  (95) 0x41823c FMSUB	D30, D31, D30, D27

  (95) 0x418240 STP	D29, D30, [X0, #8]

  (95) 0x418244 B	418164

  (95) 0x418248 FCMPE	D0, #0

  (95) 0x41824c B.GT	418254

  (95) 0x418250 B	418130

  (95) 0x418254 FDIV	D28, D17, D0

  (95) 0x418258 FMUL	D29, D8, D22

  (95) 0x41825c LDP	X7, X26, [X6, #40]

  (95) 0x418260 ADD	X2, X7, X5

  (95) 0x418264 FMUL	D23, D28, D28

  (95) 0x418268 FMUL	D24, D23, D28

  (95) 0x41826c FMUL	D2, D24, D19

  (95) 0x418270 FMADD	D3, D2, D21, D20

  (95) 0x418274 FMUL	D26, D29, D2

  (95) 0x418278 FSUB	D25, D2, S17

  (95) 0x41827c FMUL	D27, D26, D28

  (95) 0x418280 LDR	D28, [X26, X4]

  (95) 0x418284 FNMSUB	D4, D25, D2, D18

  (95) 0x418288 FMADD	D7, D4, D16, D7

  (95) 0x41828c FMADD	D29, D4, D16, D28

  (95) 0x418290 FMUL	D0, D3, D27

  (95) 0x418294 STR	D29, [X26, X4]

  (95) 0x418298 LDR	D23, [X7, X5]

  (95) 0x41829c FMSUB	D30, D0, D30, D23

  (95) 0x4182a0 STR	D30, [X7, X5]

  (95) 0x4182a4 LDP	D24, D2, [X2, #8]

  (95) 0x4182a8 FMSUB	D31, D0, D31, D24

  (95) 0x4182ac FMSUB	D1, D0, D1, D2

  (95) 0x4182b0 STP	D31, D1, [X2, #8]

  (95) 0x4182b4 B	418130

0x4182b8 FCMPE	D26, #0

0x4182bc B.GT	4182c4

0x4182c0 B	4180e8

0x4182c4 FDIV	D30, D17, D26

0x4182c8 LDP	X7, X26, [X6, #40]

0x4182cc FMUL	D31, D8, D22

0x4182d0 LDR	D26, [X26, X4]

0x4182d4 ADD	X2, X7, X5

0x4182d8 FMUL	D4, D30, D30

0x4182dc FMUL	D1, D4, D30

0x4182e0 FMUL	D0, D1, D19

0x4182e4 FMADD	D3, D0, D21, D20

0x4182e8 FSUB	D2, D0, S17

0x4182ec FMUL	D23, D31, D0

0x4182f0 FNMSUB	D24, D2, D0, D18

0x4182f4 FMUL	D25, D23, D30

0x4182f8 FMADD	D31, D24, D16, D26

0x4182fc FMADD	D7, D24, D16, D7

0x418300 FMUL	D30, D3, D25

0x418304 STR	D31, [X26, X4]

0x418308 LDR	D4, [X7, X5]

0x41830c FMSUB	D27, D30, D27, D4

0x418310 STR	D27, [X7, X5]

0x418314 LDP	D1, D0, [X2, #8]

0x418318 FMSUB	D28, D30, D28, D1

0x41831c FMSUB	D29, D30, D29, D0

0x418320 STP	D28, D29, [X2, #8]

0x418324 B	4180e8

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 187 - 216

--------------------------------------------------------------------------------

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
►98.51+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.49+	GOMP_parallel		libgomp.so.1.0.0
○	ljForce	ljForce.c:172	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.04
CQA speedup if FP arith vectorized	1.99
CQA speedup if fully vectorized	4.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	micro-operation queue,
Function	ljForce._omp_fn.1
Source	ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.13
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.58
CQA cycles if fully vectorized	1.75
Front-end cycles	7.13
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	4.50
P11 cycles	4.17
P12 cycles	4.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	57.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	4.49
Nb FLOP add-sub	4.00
Nb FLOP mul	7.00
Nb FLOP fma	10.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	10.26
Vectorization ratio load	42.86
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	27.24
Vector-efficiency ratio load	35.71
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	22.50

Metric	Value
CQA speedup if no scalar integer	2.04
CQA speedup if FP arith vectorized	1.99
CQA speedup if fully vectorized	4.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	micro-operation queue,
Function	ljForce._omp_fn.1
Source	ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.13
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.58
CQA cycles if fully vectorized	1.75
Front-end cycles	7.13
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	4.50
P11 cycles	4.17
P12 cycles	4.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	57.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	4.49
Nb FLOP add-sub	4.00
Nb FLOP mul	7.00
Nb FLOP fma	10.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	10.26
Vectorization ratio load	42.86
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	27.24
Vector-efficiency ratio load	35.71
Vector-efficiency ratio store	33.33
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	22.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:187-216
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187-191,197-216.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187,191,197-198,201,206-210,213-216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 40 paths individually, rerun with max-paths=40
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 40 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.13 to 3.50 cycles (2.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.13 to 1.75 cycles (4.07x speedup).

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

14: addition or subtraction (10 inside FMA instructions)
17: multiply (10 inside FMA instructions)
1: divide

The binary loop does not load or store any data.

General properties

nb instructions	60
nb uops	57
loop length	240
used w registers	3
used x registers	13
used b registers	0
used h registers	0
used s registers	4
used d registers	25
used q registers	0
used v registers	0
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.57

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	3.00	3.00	3.00	3.00	6.75	6.75	6.75	6.75	4.50	4.17	4.33	0.00	0.00
cycles	4.00	4.00	3.00	3.00	3.00	3.00	6.75	6.75	6.75	6.75	4.50	4.17	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	7.13
Dispatch	6.75
DIV/SQRT	1.75-3.50
Overall L1	7.13

Vectorization ratios

INT

all	26%
load	42%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	10%
load	42%
store	33%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	30%
load	35%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	27%
load	35%
store	33%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.13 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.13 to 6.75 cycles (1.06x speedup).

ASM code

In the binary file, the address of the loop is: 41808c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP W8, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 418170 <ljForce._omp_fn.1+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X4, X4,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X2, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X2, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W7, #3, 418100 <ljForce._omp_fn.1+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X2, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X2, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D0, D2, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D3, D23, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FSUB D27, D4, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D28, D3, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D29, D23, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMADD D24, D27, D27, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D25, D28, D28, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D26, D29, D29, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D5, D26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 4182b8 <ljForce._omp_fn.1+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 418170 <ljForce._omp_fn.1+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 41808c <ljForce._omp_fn.1+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4182c4 <ljForce._omp_fn.1+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4180e8 <ljForce._omp_fn.1+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D30, D17, D26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDP X7, X26, [X6, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FMUL D31, D8, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D26, [X26, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X2, X7, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL D4, D30, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMUL D1, D4, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMUL D0, D1, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D3, D0, D21, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FSUB D2, D0, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D23, D31, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FNMSUB D24, D2, D0, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMUL D25, D23, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D31, D24, D16, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D7, D24, D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMUL D30, D3, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D31, [X26, X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D4, [X7, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMSUB D27, D30, D27, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D27, [X7, X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP D1, D0, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMSUB D28, D30, D28, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMSUB D29, D30, D29, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STP D28, D29, [X2, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
B 4180e8 <ljForce._omp_fn.1+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:187-216
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 40 paths individually, rerun with max-paths=40
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.13 to 3.50 cycles (2.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

14: addition or subtraction (10 inside FMA instructions)
17: multiply (10 inside FMA instructions)
1: divide

The binary loop does not load or store any data.

General properties

nb instructions	60
nb uops	57
loop length	240
used w registers	3
used x registers	13
used b registers	0
used h registers	0
used s registers	4
used d registers	25
used q registers	0
used v registers	0
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.57

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	3.00	3.00	3.00	3.00	6.75	6.75	6.75	6.75	4.50	4.17	4.33	0.00	0.00
cycles	4.00	4.00	3.00	3.00	3.00	3.00	6.75	6.75	6.75	6.75	4.50	4.17	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	7.13
Dispatch	6.75
DIV/SQRT	1.75-3.50
Overall L1	7.13

Vectorization ratios

INT

all	26%
load	42%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	10%
load	42%
store	33%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	30%
load	35%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	27%
load	35%
store	33%
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.13 cycles.

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 41808c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP W8, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 418170 <ljForce._omp_fn.1+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X4, X4,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X2, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X2, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X7, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W7, #3, 418100 <ljForce._omp_fn.1+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X2, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X2, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D0, D2, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D3, D23, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FSUB D27, D4, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D28, D3, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D29, D23, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMADD D24, D27, D27, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D25, D28, D28, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D26, D29, D29, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D5, D26	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 4182b8 <ljForce._omp_fn.1+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 418170 <ljForce._omp_fn.1+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 41808c <ljForce._omp_fn.1+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4182c4 <ljForce._omp_fn.1+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4180e8 <ljForce._omp_fn.1+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D30, D17, D26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDP X7, X26, [X6, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FMUL D31, D8, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR D26, [X26, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X2, X7, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL D4, D30, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMUL D1, D4, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMUL D0, D1, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D3, D0, D21, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FSUB D2, D0, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D23, D31, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FNMSUB D24, D2, D0, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMUL D25, D23, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D31, D24, D16, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMADD D7, D24, D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMUL D30, D3, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
STR D31, [X26, X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D4, [X7, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMSUB D27, D30, D27, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D27, [X7, X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDP D1, D0, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMSUB D28, D30, D28, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FMSUB D29, D30, D29, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STP D28, D29, [X2, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
B 4180e8 <ljForce._omp_fn.1+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code