OV - exec - Function sortAtomsById

	Function: sortAtomsById	Module: exec	Source: haloExchange.c:654-661	Coverage (incl. loops): 0.07% \| (excl. loops): 0.07%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 654 - 661

--------------------------------------------------------------------------------

654:    int aId = ((AtomMsg*) a)->gid;

655:    int bId = ((AtomMsg*) b)->gid;

656:    assert(aId != bId);

657:

658:    if (aId < bId)

659:       return -1;

660:    return 1;

661: }

0x414330 LDR	W8, [X0]

0x414334 LDR	W9, [X1]

0x414338 CMP	W8, W9

0x41433c B.EQ	41434c

0x414340 MOVN	W8, #0

0x414344 CSNEG	W0, W8, W8, #11

0x414348 RET

0x41434c STP	X29, X30, [SP, #1008]!

0x414350 ADD	X29, SP, #0

0x414354 ADRP	X0,

0x414358 ADD	X0, X0, #3272

0x41435c ADRP	X1,

0x414360 ADD	X1, X1, #2819

0x414364 ADRP	X3,

0x414368 ADD	X3, X3, #3283

0x41436c MOVZ	W2, #656

0x414370 BL	4101b0

0x414374 HINT	#0

0x414378 HINT	#0

0x41437c HINT	#0

Coverage (%)	Name	Source Location	Module
►12.96+	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►8.02+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.41+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.41+	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.79+	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.17+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.56+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.56+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.56+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.56+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.56+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►4.94+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.70+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.70+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.47+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.85+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.23+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.23+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.23+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	indirect_msort_with_tmp		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.07% of application time for run armclang_9

Source file and lines	haloExchange.c:654-661
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:654-661.

The structure of this function is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 20% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	12
nb uops	10.50
loop length	48
used w registers	3
used x registers	3.50
used b registers	0
used h registers	0
used s registers	0.50
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	1.31 cycles
front end	1.31 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.92	0.75	0.83	0.25	0.25
cycles	1.00	1.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.92	0.75	0.83	0.25	0.25

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.31
Dispatch	1.88
Overall L1	1.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	20%
load	12%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 1.88 cycles. At this rate:

4% of peak load performance is reached (4.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

The code analyzed by CQA in that panel excludes loops and represents 0.07% of application time for run armclang_9

Source file and lines	haloExchange.c:654-661
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	7
nb uops	7
loop length	28
used w registers	3
used x registers	2
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	0.88 cycles
front end	0.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	0.88
Dispatch	1.00
Overall L1	1.00

Vectorization ratios

No vectorizable/vectorized instructions

Vector efficiency ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 1.00 cycles. At this rate:

6% of peak load performance is reached (6.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 414330

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR W8, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR W9, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
B.EQ 41434c <sortAtomsById+0x1c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CSNEG W0, W8, W8, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.07% of application time for run armclang_9

Source file and lines	haloExchange.c:654-661
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 2.75 to 0.47 cycles (5.87x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:656

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	17
nb uops	14
loop length	68
used w registers	3
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.75 cycles
front end	1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50
cycles	1.00	1.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.75
Dispatch	2.75
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	20%
load	12%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 2.75 cycles. At this rate:

2% of peak load performance is reached (2.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 414330

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR W8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W9, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 41434c <sortAtomsById+0x1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X29, X30, [SP, #1008]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <420354>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X1, <42035c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #2819	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X3, <420364>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #3283	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
○sortAtomsById	0.07	0.01

Report Configuration

Vectorization

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code