OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:288-385 [...]	Coverage (incl. loops): 0.17% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 288 - 385

--------------------------------------------------------------------------------

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

378:    return getBoxFromTuple(boxes, ix, iy, iz);

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x415ca0 STP	X29, X30, [SP, #960]!

0x415ca4 STP	X24, X23, [SP, #16]

0x415ca8 STP	X22, X21, [SP, #32]

0x415cac STP	X20, X19, [SP, #48]

0x415cb0 ADD	X29, SP, #0

0x415cb4 LDR	W8, [X0, #12]

0x415cb8 LDR	W9, [X0, #20]

0x415cbc ORR	X19, XZR, X1

0x415cc0 ORR	X20, XZR, X0

0x415cc4 CMP	W8, W9

0x415cc8 B.GE	415cf8

0x415ccc LDR	X9, [X20, #120]

0x415cd0 SBFM	X8, X8, #0, #31

0x415cd4 HINT	#0

0x415cd8 HINT	#0

0x415cdc HINT	#0

(92) 0x415ce0 STR	WZR, [X9, X8,LSL #2]

(92) 0x415ce4 ADD	X8, X8, #1

(92) 0x415ce8 LDRSW	X10, [X20, #20]

(92) 0x415cec CMP	X8, X10

(92) 0x415cf0 B.LT	415ce0

0x415cf4 LDR	W8, [X20, #12]

0x415cf8 CMP	W8, #1

0x415cfc B.LT	415e28

0x415d00 LDR	X9, [X20, #120]

0x415d04 MOVZ	W23, #24

0x415d08 ORR	X21, XZR, XZR

0x415d0c B	415d30

0x415d10 HINT	#0

0x415d14 HINT	#0

0x415d18 HINT	#0

0x415d1c HINT	#0

(90) 0x415d20 LDR	W8, [X20, #12]

  (89) 0x415d24 ADD	X21, X21, #1

  (89) 0x415d28 CMP	X21, W8,SXTW

  (89) 0x415d2c B.GE	415e28

  (89) 0x415d30 LDR	W10, [X9, X21,LSL #2]

  (89) 0x415d34 CMP	W10, #1

  (89) 0x415d38 B.LT	415d24

(90) 0x415d3c ADD	X8, X21, X21,LSL #1

(90) 0x415d40 ORR	W22, WZR, WZR

(90) 0x415d44 UBFM	X24, X8, #55, #54

(90) 0x415d48 B	415d60

  (91) 0x415d4c ADD	W22, W22, #1

  (91) 0x415d50 LDR	X9, [X20, #120]

  (91) 0x415d54 LDR	W8, [X9, X21,LSL #2]

  (91) 0x415d58 CMP	W22, W8

  (91) 0x415d5c B.GE	415d20

  (91) 0x415d60 LDR	X8, [X19, #24]

  (91) 0x415d64 LDR	D1, [X20, #48]

  (91) 0x415d68 ADD	X8, X8, X24

  (91) 0x415d6c SMADDL	X8, W22, W23, X8

  (91) 0x415d70 LDR	D0, [X8]

  (91) 0x415d74 FCMP	D0, D1

  (91) 0x415d78 B.GE	415da4

  (91) 0x415d7c LDR	D1, [X20, #24]

  (91) 0x415d80 LDR	W10, [X20]

  (91) 0x415d84 SUB	W11, W10, #1

  (91) 0x415d88 FSUB	D0, D0, S1

  (91) 0x415d8c LDR	D1, [X20, #96]

  (91) 0x415d90 FMUL	D0, D0, D1

  (91) 0x415d94 FCVTMS	W9, D0

  (91) 0x415d98 CMP	W10, W9

  (91) 0x415d9c CSEL	W1, W11, W9, #0

  (91) 0x415da0 B	415da8

  (91) 0x415da4 LDR	W1, [X20]

  (91) 0x415da8 LDP	D0, D1, [X8, #8]

  (91) 0x415dac LDP	D2, D3, [X20, #32]

  (91) 0x415db0 LDP	D4, D5, [X20, #104]

  (91) 0x415db4 FSUB	D3, D1, S3

  (91) 0x415db8 ORR	X0, XZR, X20

  (91) 0x415dbc FMUL	D3, D3, D5

  (91) 0x415dc0 LDP	W9, W10, [X20, #4]

  (91) 0x415dc4 SUB	W11, W9, #1

  (91) 0x415dc8 FSUB	D2, D0, S2

  (91) 0x415dcc FMUL	D2, D2, D4

  (91) 0x415dd0 FCVTMS	W8, D2

  (91) 0x415dd4 CMP	W9, W8

  (91) 0x415dd8 CSEL	W8, W11, W8, #0

  (91) 0x415ddc FCVTMS	W11, D3

  (91) 0x415de0 LDP	D2, D3, [X20, #56]

  (91) 0x415de4 FCMP	D0, D2

  (91) 0x415de8 CSEL	W2, W8, W9, #11

  (91) 0x415dec SUB	W8, W10, #1

  (91) 0x415df0 CMP	W10, W11

  (91) 0x415df4 CSEL	W8, W8, W11, #0

  (91) 0x415df8 FCMP	D1, D3

  (91) 0x415dfc CSEL	W3, W8, W10, #11

  (91) 0x415e00 BL	415830

  (91) 0x415e04 CMP	X21, W0,UXTW

  (91) 0x415e08 B.EQ	415d4c

  (91) 0x415e0c ORR	W4, WZR, W0

  (91) 0x415e10 ORR	X0, XZR, X20

  (91) 0x415e14 ORR	X1, XZR, X19

  (91) 0x415e18 ORR	W2, WZR, W22

  (91) 0x415e1c ORR	W3, WZR, W21

  (91) 0x415e20 BL	415b10

  (91) 0x415e24 B	415d50

0x415e28 LDP	X20, X19, [SP, #48]

0x415e2c LDP	X22, X21, [SP, #32]

0x415e30 LDP	X24, X23, [SP, #16]

0x415e34 LDP	X29, X30, [SP], #64

0x415e38 RET

0x415e3c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.48+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	eam.c:831	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_9

Source file and lines	linkCells.c:288-385
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:288-304,352-365,371,378,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 34% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.33 to 1.50 cycles (2.89x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes.

General properties

nb instructions	33
nb uops	25
loop length	132
used w registers	3
used x registers	13
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00
cycles	2.00	2.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.13
Dispatch	4.33
Overall L1	4.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	34%
load	35%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.33 cycles. At this rate:

2% of peak load performance is reached (2.08 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 415ca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W8, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 415cf8 <updateLinkCells+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X8, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W8, [X20, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 415e28 <updateLinkCells+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W23, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 415d30 <updateLinkCells+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #64	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_9

Source file and lines	linkCells.c:288-385
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:288-304,352-365,371,378,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes.

General properties

nb instructions	33
nb uops	25
loop length	132
used w registers	3
used x registers	13
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00
cycles	2.00	2.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.13
Dispatch	4.33
Overall L1	4.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	34%
load	35%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.33 cycles. At this rate:

2% of peak load performance is reached (2.08 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 415ca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W8, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X19, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 415cf8 <updateLinkCells+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SBFM X8, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W8, [X20, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 415e28 <updateLinkCells+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W23, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 415d30 <updateLinkCells+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #64	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.17	0.03
▼Loop 90 - linkCells.c:291-378 - exec–	0.00	0.01
○Loop 91 - linkCells.c:295-378 - exec	0.17	1.91
○Loop 89 - linkCells.c:291-295 - exec	0.00	0.02
○Loop 92 - linkCells.c:384-385 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code