| Loop Id: 100 | Module: exec | Source: ljForce.c:173-216 [...] | Coverage: 55.70% |
|---|
| Loop Id: 100 | Module: exec | Source: ljForce.c:173-216 [...] | Coverage: 55.70% |
|---|
(97) 0x416484 ADD X8, X8, #1 |
(97) 0x416488 ADD W16, W16, #64 |
(97) 0x41648c CMP W14, W8 |
(97) 0x416490 B.EQ 4163c8 |
(97) 0x416494 SBFM X16, X16, #0, #31 |
(97) 0x416498 CMP W13, #1 |
(97) 0x41649c B.LT 416484 |
(98) 0x4164a0 LDR X0, [X11, #128] |
(98) 0x4164a4 LDRSW X18, [X12, X8,LSL #2] |
(98) 0x4164a8 ORR X17, XZR, XZR |
(98) 0x4164ac LDR X0, [X0, X8,LSL #3] |
(98) 0x4164b0 ADD X1, X18, X8,LSL #6 |
(98) 0x4164b4 B 4164cc |
(98) 0x4164c0 ADD X17, X17, #1 |
(98) 0x4164c4 CMP X17, X13 |
(98) 0x4164c8 B.EQ 416484 |
(98) 0x4164cc LDR W3, [X0, X17,LSL #2] |
(98) 0x4164d0 TBNZ W3, #31, 416644 |
(98) 0x4164d4 CMP W18, #1 |
(98) 0x4164d8 B.LT 4164c0 |
(99) 0x4164dc LDR W2, [X12, X3,LSL #2] |
(99) 0x4164e0 UBFM W3, W3, #26, #25 |
(99) 0x4164e4 ORR X6, XZR, X16 |
(99) 0x4164e8 UMULL X5, W3, W15 |
(99) 0x4164ec ADD W4, W2, W3 |
(99) 0x4164f0 B 41650c |
(99) 0x416500 ADD X6, X6, #1 |
(99) 0x416504 CMP X6, X1 |
(99) 0x416508 B.GE 4164c0 |
(99) 0x41650c CMP W2, #1 |
(99) 0x416510 B.LT 416500 |
0x416514 LDR X7, [X10, #32] |
0x416518 ORR W26, WZR, W3 |
0x41651c LDR X25, [X7, #24] |
0x416520 MADD X24, X6, X15, X25 |
0x416524 ADD X25, X25, X5 |
0x416528 ADD X25, X25, #16 |
0x41652c B 416550 |
0x416540 ADD W26, W26, #1 |
0x416544 ADD X25, X25, #24 |
0x416548 CMP W4, W26 |
0x41654c B.LE 416500 |
0x416550 LDR Q6, [X24] |
0x416554 LDUR Q7, [X25, #496] |
0x416558 LDR D17, [X25] |
0x41655c FSUB V6.2D, V6.2D, V7.2D |
0x416560 FMUL V7.2D, V6.2D, V6.2D |
0x416564 FADDP D16, V7.2D |
0x416568 LDR D7, [X24, #16] |
0x41656c FSUB D7, D7, S17 |
0x416570 LDR D17, [X23] |
0x416574 FMADD D16, D7, D7, D16 |
0x416578 FCMP D16, D17 |
0x41657c B.GT 416540 |
0x416580 FCMP D16, #0 |
0x416584 B.LE 416540 |
0x416588 FDIV D16, D1, D16 |
0x41658c LDR D17, [X22] |
0x416590 LDR D19, [X21] |
0x416594 LDP X28, X27, [X7, #40] |
0x416598 FMUL D18, D16, D16 |
0x41659c FMUL D17, D16, D17 |
0x4165a0 FMUL D16, D16, D5 |
0x4165a4 FMUL D17, D18, D17 |
0x4165a8 FSUB D18, D1, S17 |
0x4165ac FMUL D16, D16, D17 |
0x4165b0 FMADD D18, D18, D17, D19 |
0x4165b4 LDR D19, [X27, X6,LSL #3] |
0x4165b8 FMUL D18, D18, D2 |
0x4165bc FADD D19, D18, D19 |
0x4165c0 FADD D0, D0, D18 |
0x4165c4 STR D19, [X27, X6,LSL #3] |
0x4165c8 MADD X27, X6, X15, X28 |
0x4165cc FMADD D19, D17, D4, D3 |
0x4165d0 STR D0, [SP, #24] |
0x4165d4 LDR D18, [X9] |
0x4165d8 LDR Q17, [X27] |
0x4165dc FMUL D16, D16, D18 |
0x4165e0 FMUL D16, D16, D19 |
0x4165e4 FMLA V17.2D, V6.2D, V16.D[0] |
0x4165e8 LDR D6, [X27, #16] |
0x4165ec STR Q17, [X27] |
0x4165f0 FMADD D6, D16, D7, D6 |
0x4165f4 STR D6, [X27, #16] |
0x4165f8 B 416540 |
/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 173 - 216 |
-------------------------------------------------------------------------------- |
173: for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++) |
174: { |
175: int nIBox = s->boxes->nAtoms[iBox]; |
176: |
177: // loop over neighbors of iBox |
178: for (int jTmp=0; jTmp<nNbrBoxes; jTmp++) |
179: { |
180: int jBox = s->boxes->nbrBoxes[iBox][jTmp]; |
181: |
182: assert(jBox>=0); |
183: |
184: int nJBox = s->boxes->nAtoms[jBox]; |
185: |
186: // loop over atoms in iBox |
187: for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++) |
188: { |
189: |
190: // loop over atoms in jBox |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.57+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_launch_thread | libomp.so | |
| ○ | __kmp_launch_worker(void*) | libomp.so | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 | |
| ►1.42+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_fork_call | libomp.so | |
| ○ | __kmpc_fork_call | libomp.so | |
| ○ | ljForce | ljForce.c:224 | exec |
| ○ | timestep | timestep.c:51 | exec |
| ○ | main | CoMD.c:125 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | eam.c:831 | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.35 |
| CQA speedup if FP arith vectorized | 1.27 |
| CQA speedup if fully vectorized | 3.38 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.13 |
| Bottlenecks | micro-operation queue, P6, P7, P8, P9, |
| Function | ljForce.omp_outlined.2 |
| Source | ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.75 |
| CQA cycles if no scalar integer | 5.00 |
| CQA cycles if FP arith vectorized | 5.33 |
| CQA cycles if fully vectorized | 2.00 |
| Front-end cycles | 6.75 |
| P0 cycles | 2.50 |
| P1 cycles | 2.50 |
| P2 cycles | 2.00 |
| P3 cycles | 2.00 |
| P4 cycles | 2.00 |
| P5 cycles | 2.00 |
| P6 cycles | 6.75 |
| P7 cycles | 6.75 |
| P8 cycles | 6.75 |
| P9 cycles | 6.75 |
| P10 cycles | 6.00 |
| P11 cycles | 6.00 |
| P12 cycles | 6.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 1.75 - 3.50 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 54.00 |
| Nb uops | 54.00 |
| Nb loads | NA |
| Nb stores | 4.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 4.44 |
| Nb FLOP add-sub | 7.00 |
| Nb FLOP mul | 10.00 |
| Nb FLOP fma | 6.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 0.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 0.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 17.07 |
| Vectorization ratio load | 27.27 |
| Vectorization ratio store | 25.00 |
| Vectorization ratio mul | 11.11 |
| Vectorization ratio add_sub | 14.29 |
| Vectorization ratio fma | 20.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 28.96 |
| Vector-efficiency ratio load | 31.82 |
| Vector-efficiency ratio store | 31.25 |
| Vector-efficiency ratio mul | 27.78 |
| Vector-efficiency ratio add_sub | 30.36 |
| Vector-efficiency ratio fma | 30.00 |
| Vector-efficiency ratio div_sqrt | 25.00 |
| Vector-efficiency ratio other | 18.75 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.35 |
| CQA speedup if FP arith vectorized | 1.27 |
| CQA speedup if fully vectorized | 3.38 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.13 |
| Bottlenecks | micro-operation queue, P6, P7, P8, P9, |
| Function | ljForce.omp_outlined.2 |
| Source | ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.75 |
| CQA cycles if no scalar integer | 5.00 |
| CQA cycles if FP arith vectorized | 5.33 |
| CQA cycles if fully vectorized | 2.00 |
| Front-end cycles | 6.75 |
| P0 cycles | 2.50 |
| P1 cycles | 2.50 |
| P2 cycles | 2.00 |
| P3 cycles | 2.00 |
| P4 cycles | 2.00 |
| P5 cycles | 2.00 |
| P6 cycles | 6.75 |
| P7 cycles | 6.75 |
| P8 cycles | 6.75 |
| P9 cycles | 6.75 |
| P10 cycles | 6.00 |
| P11 cycles | 6.00 |
| P12 cycles | 6.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 1.75 - 3.50 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 54.00 |
| Nb uops | 54.00 |
| Nb loads | NA |
| Nb stores | 4.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 4.44 |
| Nb FLOP add-sub | 7.00 |
| Nb FLOP mul | 10.00 |
| Nb FLOP fma | 6.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 0.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 0.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 17.07 |
| Vectorization ratio load | 27.27 |
| Vectorization ratio store | 25.00 |
| Vectorization ratio mul | 11.11 |
| Vectorization ratio add_sub | 14.29 |
| Vectorization ratio fma | 20.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 28.96 |
| Vector-efficiency ratio load | 31.82 |
| Vector-efficiency ratio store | 31.25 |
| Vector-efficiency ratio mul | 27.78 |
| Vector-efficiency ratio add_sub | 30.36 |
| Vector-efficiency ratio fma | 30.00 |
| Vector-efficiency ratio div_sqrt | 25.00 |
| Vector-efficiency ratio other | 18.75 |
| Path / |
| Function | ljForce.omp_outlined.2 |
| Source file and lines | ljForce.c:173-216 |
| Module | exec |
| nb instructions | 54 |
| nb uops | 54 |
| loop length | 216 |
| used w registers | 4 |
| used x registers | 13 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 2 |
| used d registers | 12 |
| used q registers | 3 |
| used v registers | 4 |
| used z registers | 0 |
| nb stack references | 1 |
| ADD-SUB / MUL ratio | 0.67 |
| micro-operation queue | 6.75 cycles |
| front end | 6.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 2.00 | 2.00 | 2.00 | 2.00 | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
| cycles | 2.50 | 2.50 | 2.00 | 2.00 | 2.00 | 2.00 | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 1.75-3.50 |
| Front-end | 6.75 |
| Dispatch | 6.75 |
| DIV/SQRT | 1.75-3.50 |
| Overall L1 | 6.75 |
| all | 22% |
| load | 27% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 13% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 11% |
| add-sub | 16% |
| fma | 20% |
| div/sqrt | 0% |
| other | 0% |
| all | 17% |
| load | 27% |
| store | 25% |
| mul | 11% |
| add-sub | 14% |
| fma | 20% |
| div/sqrt | 0% |
| other | 0% |
| all | 28% |
| load | 31% |
| store | 31% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 29% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 27% |
| add-sub | 33% |
| fma | 30% |
| div/sqrt | 25% |
| other | 25% |
| all | 28% |
| load | 31% |
| store | 31% |
| mul | 27% |
| add-sub | 30% |
| fma | 30% |
| div/sqrt | 25% |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR X7, [X10, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ORR W26, WZR, W3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| LDR X25, [X7, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| MADD X24, X6, X15, X25 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| ADD X25, X25, X5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X25, X25, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B 416550 <ljForce.omp_outlined.2+0x230> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W26, W26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD X25, X25, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W4, W26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LE 416500 <ljForce.omp_outlined.2+0x1e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR Q6, [X24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | vect (50.0%) |
| LDUR Q7, [X25, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | vect (50.0%) |
| LDR D17, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FSUB V6.2D, V6.2D, V7.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (50.0%) |
| FMUL V7.2D, V6.2D, V6.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | vect (50.0%) |
| FADDP D16, V7.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| LDR D7, [X24, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FSUB D7, D7, S17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| LDR D17, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FMADD D16, D7, D7, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| FCMP D16, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.GT 416540 <ljForce.omp_outlined.2+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| FCMP D16, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.LE 416540 <ljForce.omp_outlined.2+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| FDIV D16, D1, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1.75-3.50 | scal (25.0%) |
| LDR D17, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR D19, [X21] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDP X28, X27, [X7, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| FMUL D18, D16, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMUL D17, D16, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMUL D16, D16, D5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMUL D17, D18, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FSUB D18, D1, S17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FMUL D16, D16, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMADD D18, D18, D17, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| LDR D19, [X27, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FMUL D18, D18, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FADD D19, D18, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FADD D0, D0, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D19, [X27, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| MADD X27, X6, X15, X28 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| FMADD D19, D17, D4, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D0, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LDR D18, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR Q17, [X27] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | vect (50.0%) |
| FMUL D16, D16, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMUL D16, D16, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMLA V17.2D, V6.2D, V16.D[0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | vect (50.0%) |
| LDR D6, [X27, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| STR Q17, [X27] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (50.0%) |
| FMADD D6, D16, D7, D6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D6, [X27, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 416540 <ljForce.omp_outlined.2+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| Function | ljForce.omp_outlined.2 |
| Source file and lines | ljForce.c:173-216 |
| Module | exec |
| nb instructions | 54 |
| nb uops | 54 |
| loop length | 216 |
| used w registers | 4 |
| used x registers | 13 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 2 |
| used d registers | 12 |
| used q registers | 3 |
| used v registers | 4 |
| used z registers | 0 |
| nb stack references | 1 |
| ADD-SUB / MUL ratio | 0.67 |
| micro-operation queue | 6.75 cycles |
| front end | 6.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 2.00 | 2.00 | 2.00 | 2.00 | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
| cycles | 2.50 | 2.50 | 2.00 | 2.00 | 2.00 | 2.00 | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 1.75-3.50 |
| Front-end | 6.75 |
| Dispatch | 6.75 |
| DIV/SQRT | 1.75-3.50 |
| Overall L1 | 6.75 |
| all | 22% |
| load | 27% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 13% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 11% |
| add-sub | 16% |
| fma | 20% |
| div/sqrt | 0% |
| other | 0% |
| all | 17% |
| load | 27% |
| store | 25% |
| mul | 11% |
| add-sub | 14% |
| fma | 20% |
| div/sqrt | 0% |
| other | 0% |
| all | 28% |
| load | 31% |
| store | 31% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 29% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 27% |
| add-sub | 33% |
| fma | 30% |
| div/sqrt | 25% |
| other | 25% |
| all | 28% |
| load | 31% |
| store | 31% |
| mul | 27% |
| add-sub | 30% |
| fma | 30% |
| div/sqrt | 25% |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR X7, [X10, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| ORR W26, WZR, W3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| LDR X25, [X7, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 | N/A |
| MADD X24, X6, X15, X25 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| ADD X25, X25, X5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| ADD X25, X25, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| B 416550 <ljForce.omp_outlined.2+0x230> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| ADD W26, W26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD X25, X25, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP W4, W26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| B.LE 416500 <ljForce.omp_outlined.2+0x1e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| LDR Q6, [X24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | vect (50.0%) |
| LDUR Q7, [X25, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | vect (50.0%) |
| LDR D17, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FSUB V6.2D, V6.2D, V7.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | vect (50.0%) |
| FMUL V7.2D, V6.2D, V6.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | vect (50.0%) |
| FADDP D16, V7.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (50.0%) |
| LDR D7, [X24, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FSUB D7, D7, S17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| LDR D17, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FMADD D16, D7, D7, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| FCMP D16, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.GT 416540 <ljForce.omp_outlined.2+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| FCMP D16, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | scal (25.0%) |
| B.LE 416540 <ljForce.omp_outlined.2+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| FDIV D16, D1, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1.75-3.50 | scal (25.0%) |
| LDR D17, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR D19, [X21] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDP X28, X27, [X7, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 | N/A |
| FMUL D18, D16, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMUL D17, D16, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMUL D16, D16, D5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMUL D17, D18, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FSUB D18, D1, S17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FMUL D16, D16, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMADD D18, D18, D17, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| LDR D19, [X27, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| FMUL D18, D18, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FADD D19, D18, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| FADD D0, D0, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 | scal (25.0%) |
| STR D19, [X27, X6,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| MADD X27, X6, X15, X28 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | N/A |
| FMADD D19, D17, D4, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D0, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LDR D18, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| LDR Q17, [X27] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | vect (50.0%) |
| FMUL D16, D16, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMUL D16, D16, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (25.0%) |
| FMLA V17.2D, V6.2D, V16.D[0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | vect (50.0%) |
| LDR D6, [X27, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 | scal (25.0%) |
| STR Q17, [X27] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | vect (50.0%) |
| FMADD D6, D16, D7, D6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 | scal (25.0%) |
| STR D6, [X27, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| B 416540 <ljForce.omp_outlined.2+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
