OV - exec - Loop 105

	Loop Id: 105	Module: exec	Source: random.c:26-48 [...]	Coverage: 0.01%

0x417c00 MUL	X10, X10, X8

0x417c04 UMULH	X11, X10, X9

0x417c08 SUB	X12, X10, X11

0x417c0c ADD	X11, X11, X12,LSR #1

0x417c10 UBFM	X11, X11, #60, #63

0x417c14 SUB	X11, X11, X11,LSL #61

0x417c18 ADD	X10, X10, X11

0x417c1c UCVTF	D3, X10

0x417c20 MUL	X10, X10, X8

0x417c24 UMULH	X11, X10, X9

0x417c28 FMADD	D3, D3, D0, D1

0x417c2c SUB	X12, X10, X11

0x417c30 ADD	X11, X11, X12,LSR #1

0x417c34 FMUL	D3, D3, D3

0x417c38 UBFM	X11, X11, #60, #63

0x417c3c SUB	X11, X11, X11,LSL #61

0x417c40 ADD	X10, X10, X11

0x417c44 UCVTF	D4, X10

0x417c48 FMADD	D9, D4, D0, D1

0x417c4c FMADD	D8, D9, D9, D3

0x417c50 FCMP	D8, D2

0x417c54 B.GE	417c00

0x417c58 FCMP	D8, #0

0x417c5c B.EQ	417c00

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 26 - 48

--------------------------------------------------------------------------------

26:       v1 = 2.0*lcg61(seed)-1.0;

27:       v2 = 2.0*lcg61(seed)-1.0;

28:       rsq = v1*v1+v2*v2;

29:    } while (rsq >= 1.0 || rsq == 0.0);

[...]

45:    *seed *= UINT64_C(437799614237992725);

46:    *seed %= UINT64_C(2305843009213693951);

47:

48:    return *seed*convertToDouble;

Coverage (%)	Name	Source Location	Module
►62.50+	setTemperature.omp_outlined	initAtoms.c:160	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►16.67+	setTemperature.omp_outlined	initAtoms.c:161	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►16.67+	setTemperature.omp_outlined	initAtoms.c:162	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►4.17+	setTemperature.omp_outlined	initAtoms.c:162	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	setTemperature	initAtoms.c:167	exec
○	main	CoMD.c:200	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	eam.c:831	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.80
Bottlenecks
Function	gasdev
Source	random.c:26-29,random.c:45-48
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	19.50
CQA cycles if fully vectorized	6.00
Front-end cycles	3.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	2.00
P7 cycles	1.50
P8 cycles	1.25
P9 cycles	1.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	24
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.29
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.80
Bottlenecks
Function	gasdev
Source	random.c:26-29,random.c:45-48
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	19.50
CQA cycles if fully vectorized	6.00
Front-end cycles	3.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	2.00
P7 cycles	1.50
P8 cycles	1.25
P9 cycles	1.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	24
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.29
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	gasdev
Source file and lines	random.c:26-48
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:26-29,45-48.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 24.00 to 6.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
4: multiply (3 inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	24
nb uops	24
loop length	96
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	3.00	3.00	5.00	5.00	2.00	1.50	1.25	1.25	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	3.00	3.00	5.00	5.00	2.00	1.50	1.25	1.25	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	24.00

Cycles summary

Front-end	3.00
Dispatch	5.00
Data deps.	24.00
Overall L1	24.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 417c00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MUL X10, X10, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
UMULH X11, X10, X9	1	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (25.0%)
SUB X12, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X11, X12,LSR #1	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
UBFM X11, X11, #60, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X11, X11, X11,LSL #61	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
UCVTF D3, X10	1	0	0	0	0	1	0	0	0	0	0	3	1	scal (25.0%)
MUL X10, X10, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
UMULH X11, X10, X9	1	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (25.0%)
FMADD D3, D3, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
SUB X12, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X11, X12,LSR #1	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
FMUL D3, D3, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (25.0%)
UBFM X11, X11, #60, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X11, X11, X11,LSL #61	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
UCVTF D4, X10	1	0	0	0	0	1	0	0	0	0	0	3	1	scal (25.0%)
FMADD D9, D4, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
FMADD D8, D9, D9, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
FCMP D8, D2	1	0	0	0	0	0	0	1	0	0	0	2	1	scal (25.0%)
B.GE 417c00 <gasdev+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D8, #0	1	0	0	0	0	0	0	1	0	0	0	2	1	scal (25.0%)
B.EQ 417c00 <gasdev+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	gasdev
Source file and lines	random.c:26-48
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
4: multiply (3 inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	24
nb uops	24
loop length	96
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	3.00	3.00	5.00	5.00	2.00	1.50	1.25	1.25	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	3.00	3.00	5.00	5.00	2.00	1.50	1.25	1.25	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	24.00

Cycles summary

Front-end	3.00
Dispatch	5.00
Data deps.	24.00
Overall L1	24.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 417c00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MUL X10, X10, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
UMULH X11, X10, X9	1	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (25.0%)
SUB X12, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X11, X12,LSR #1	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
UBFM X11, X11, #60, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X11, X11, X11,LSL #61	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
UCVTF D3, X10	1	0	0	0	0	1	0	0	0	0	0	3	1	scal (25.0%)
MUL X10, X10, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
UMULH X11, X10, X9	1	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (25.0%)
FMADD D3, D3, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
SUB X12, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X11, X12,LSR #1	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
FMUL D3, D3, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (25.0%)
UBFM X11, X11, #60, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
SUB X11, X11, X11,LSL #61	1	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (25.0%)
UCVTF D4, X10	1	0	0	0	0	1	0	0	0	0	0	3	1	scal (25.0%)
FMADD D9, D4, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
FMADD D8, D9, D9, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.25	scal (25.0%)
FCMP D8, D2	1	0	0	0	0	0	0	1	0	0	0	2	1	scal (25.0%)
B.GE 417c00 <gasdev+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D8, #0	1	0	0	0	0	0	0	1	0	0	0	2	1	scal (25.0%)
B.EQ 417c00 <gasdev+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code