OV - exec - Function moveAtom

	Function: moveAtom	Module: exec	Source: linkCells.c:257-335 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.01%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 257 - 335

--------------------------------------------------------------------------------

257: {

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

270:

271:    return;

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

335: }

0x41738c LDR	X5, [X0, #120]

0x417390 SBFM	X13, X4, #0, #31

0x417394 UBFM	W12, W3, #26, #25

0x417398 LDP	X17, X8, [X1, #8]

0x41739c ADD	W2, W2, W12

0x4173a0 MOVZ	W11, #24

0x4173a4 SBFM	X10, X2, #0, #31

0x4173a8 SMULL	X15, W2, W11

0x4173ac LDR	W6, [X5, X13,LSL #2]

0x4173b0 LDR	W9, [X17, X10,LSL #2]

0x4173b4 LDR	X18, [X1, #24]

0x4173b8 ADD	W7, W6, W4,LSL #6

0x4173bc SBFM	X14, X7, #0, #31

0x4173c0 SMULL	X16, W7, W11

0x4173c4 STR	W9, [X17, X14,LSL #2]

0x4173c8 ADD	X2, X18, X15

0x4173cc LDR	W5, [X8, X10,LSL #2]

0x4173d0 ADD	X6, X18, X16

0x4173d4 STR	W5, [X8, X14,LSL #2]

0x4173d8 LDP	X8, X9, [X2]

0x4173dc STP	X8, X9, [X6]

0x4173e0 LDR	X7, [X2, #16]

0x4173e4 STR	X7, [X6, #16]

0x4173e8 LDR	X17, [X1, #32]

0x4173ec ADD	X18, X17, X15

0x4173f0 ADD	X2, X17, X16

0x4173f4 LDP	X6, X7, [X18]

0x4173f8 STP	X6, X7, [X2]

0x4173fc LDR	X9, [X18, #16]

0x417400 STR	X9, [X2, #16]

0x417404 LDR	X5, [X1, #40]

0x417408 ADD	X8, X5, X15

0x41740c ADD	X16, X5, X16

0x417410 LDP	X6, X7, [X8]

0x417414 STP	X6, X7, [X16]

0x417418 LDR	X7, [X8, #16]

0x41741c STR	X7, [X16, #16]

0x417420 LDR	X17, [X1, #48]

0x417424 LDR	X18, [X17, X10,LSL #3]

0x417428 STR	X18, [X17, X14,LSL #3]

0x41742c LDR	X14, [X0, #120]

0x417430 LDR	W2, [X14, X13,LSL #2]

0x417434 ADD	W9, W2, #1

0x417438 STR	W9, [X14, X13,LSL #2]

0x41743c CMP	W9, #63

0x417440 B.GT	4174f8

0x417444 SBFM	X13, X3, #0, #31

0x417448 LDR	W5, [X14, X13,LSL #2]

0x41744c SUB	W8, W5, #1

0x417450 STR	W8, [X14, X13,LSL #2]

0x417454 CBNZ	W8, 417474

0x417458 LDR	W10, [X0, #12]

0x41745c CMP	W10, W4

0x417460 B.GE	417470

0x417464 LDR	W4, [X1]

0x417468 SUB	W0, W4, #1

0x41746c STR	W0, [X1]

0x417470 RET

0x417474 LDP	X7, X6, [X1, #8]

0x417478 ADD	W12, W8, W12

0x41747c SBFM	X16, X12, #0, #31

0x417480 SMULL	X17, W12, W11

0x417484 LDR	X18, [X1, #24]

0x417488 LDR	W11, [X7, X16,LSL #2]

0x41748c ADD	X14, X18, X17

0x417490 ADD	X2, X18, X15

0x417494 STR	W11, [X7, X10,LSL #2]

0x417498 LDR	W9, [X6, X16,LSL #2]

0x41749c STR	W9, [X6, X10,LSL #2]

0x4174a0 LDP	X8, X9, [X14]

0x4174a4 STP	X8, X9, [X2]

0x4174a8 LDR	X3, [X14, #16]

0x4174ac STR	X3, [X2, #16]

0x4174b0 LDR	X13, [X1, #32]

0x4174b4 ADD	X5, X13, X17

0x4174b8 ADD	X12, X13, X15

0x4174bc LDP	X6, X7, [X5]

0x4174c0 STP	X6, X7, [X12]

0x4174c4 LDR	X7, [X5, #16]

0x4174c8 STR	X7, [X12, #16]

0x4174cc LDR	X18, [X1, #40]

0x4174d0 ADD	X17, X18, X17

0x4174d4 ADD	X15, X18, X15

0x4174d8 LDP	X2, X3, [X17]

0x4174dc STP	X2, X3, [X15]

0x4174e0 LDR	X11, [X17, #16]

0x4174e4 STR	X11, [X15, #16]

0x4174e8 LDR	X14, [X1, #48]

0x4174ec LDR	X16, [X14, X16,LSL #3]

0x4174f0 STR	X16, [X14, X10,LSL #3]

0x4174f4 B	417458

0x4174f8 ADRP	X3,

0x4174fc ADRP	X1,

0x417500 STP	X29, X30, [SP, #1008]!

0x417504 ADD	X4, X3, #3440

0x417508 ADRP	X0,

0x41750c ADD	X29, SP, #0

0x417510 ADD	X3, X4, #32

0x417514 ADD	X1, X1, #2960

0x417518 ADD	X0, X0, #3192

0x41751c MOVZ	W2, #262

0x417520 BL	4101c0

Coverage (%)	Name	Source Location	Module
►100.00+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_4

Source file and lines	linkCells.c:257-335
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:257-271,327-335.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This function has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 19.00 to 3.73 cycles (5.09x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 27 bytes. The binary function is storing 21 bytes.

General properties

nb instructions	102
nb uops	102
loop length	408
used w registers	12
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.75 cycles
front end	12.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	10.25	10.25	10.25	10.25	0.00	0.00	0.00	0.00	19.00	19.00	19.00	11.00	11.00
cycles	3.00	3.00	10.25	10.25	10.25	10.25	0.00	0.00	0.00	0.00	19.00	19.00	19.00	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.75
Dispatch	19.00
Overall L1	19.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	24%
load	17%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.00 cycles. At this rate:

1% of peak load performance is reached (1.42 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 41738c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X5, [X0, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X13, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM W12, W3, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X17, X8, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W2, W2, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W11, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X10, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SMULL X15, W2, W11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR W6, [X5, X13,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X17, X10,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X18, [X1, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W7, W6, W4,LSL #6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
SBFM X14, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SMULL X16, W7, W11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
STR W9, [X17, X14,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD X2, X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W5, [X8, X10,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X18, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W5, [X8, X14,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X7, [X2, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [X6, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X1, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X17, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X2, X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X6, X7, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X6, X7, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X18, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X9, [X2, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X5, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X16, X5, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X6, X7, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X6, X7, [X16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X7, [X8, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [X16, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X1, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X17, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X14, X13,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W9, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR W9, [X14, X13,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W9, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GT 4174f8 <moveAtom+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X13, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W5, [X14, X13,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W8, [X14, X13,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CBNZ W8, 417474 <moveAtom+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [X0, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W10, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 417470 <moveAtom+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W4, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W0, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W0, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X6, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W12, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X16, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SMULL X17, W12, W11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR X18, [X1, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W11, [X7, X16,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD X14, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X2, X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W11, [X7, X10,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W9, [X6, X16,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W9, [X6, X10,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X8, X9, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X14, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X3, [X2, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X1, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X13, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X12, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X6, X7, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X6, X7, [X12]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X7, [X5, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [X12, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X1, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X15, X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X2, X3, [X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X2, X3, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X17, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X11, [X15, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X1, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 417458 <moveAtom+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <4214f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X1, <4204fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #1008]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X3, #3440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <420508>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X4, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #2960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #262	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_4

Source file and lines	linkCells.c:257-335
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:257-271,327-335.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 27 bytes. The binary function is storing 21 bytes.

General properties

nb instructions	102
nb uops	102
loop length	408
used w registers	12
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.75 cycles
front end	12.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	10.25	10.25	10.25	10.25	0.00	0.00	0.00	0.00	19.00	19.00	19.00	11.00	11.00
cycles	3.00	3.00	10.25	10.25	10.25	10.25	0.00	0.00	0.00	0.00	19.00	19.00	19.00	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.75
Dispatch	19.00
Overall L1	19.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	24%
load	17%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.00 cycles. At this rate:

1% of peak load performance is reached (1.42 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 41738c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X5, [X0, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X13, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM W12, W3, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X17, X8, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W2, W2, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W11, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X10, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SMULL X15, W2, W11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR W6, [X5, X13,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X17, X10,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X18, [X1, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W7, W6, W4,LSL #6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
SBFM X14, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SMULL X16, W7, W11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
STR W9, [X17, X14,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD X2, X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W5, [X8, X10,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X18, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W5, [X8, X14,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X8, X9, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X7, [X2, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [X6, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X1, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X17, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X2, X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X6, X7, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X6, X7, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X18, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X9, [X2, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X1, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X5, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X16, X5, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X6, X7, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X6, X7, [X16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X7, [X8, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [X16, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X1, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X17, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X14, X13,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W9, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR W9, [X14, X13,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W9, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GT 4174f8 <moveAtom+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X13, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W5, [X14, X13,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W8, [X14, X13,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CBNZ W8, 417474 <moveAtom+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [X0, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W10, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 417470 <moveAtom+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W4, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W0, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W0, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X6, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD W12, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X16, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SMULL X17, W12, W11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR X18, [X1, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W11, [X7, X16,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD X14, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X2, X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W11, [X7, X10,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDR W9, [X6, X16,LSL #2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W9, [X6, X10,LSL #2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
LDP X8, X9, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X14, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X3, [X2, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X1, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X13, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X12, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X6, X7, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X6, X7, [X12]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X7, [X5, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [X12, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X1, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X15, X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X2, X3, [X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X2, X3, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X17, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X11, [X15, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X1, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 417458 <moveAtom+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <4214f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X1, <4204fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #1008]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X3, #3440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <420508>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X4, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X1, #2960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #262	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
○moveAtom	0.01	0.00

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code