OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.46% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

366:    {

367:       if (iy == gridSize[1]) iy = gridSize[1] - 1;

368:    }

369:    else

370:       iy = gridSize[1];

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x417524 STP	X29, X30, [SP, #928]!

0x417528 ADD	X29, SP, #0

0x41752c LDR	W2, [X0, #12]

0x417530 STP	X25, X26, [SP, #64]

0x417534 ORR	X25, XZR, X1

0x417538 LDR	W1, [X0, #20]

0x41753c STP	X19, X20, [SP, #16]

0x417540 ORR	X20, XZR, X0

0x417544 CMP	W2, W1

0x417548 B.GE	417578

0x41754c SBFM	X0, X2, #0, #31

0x417550 LDR	X2, [X20, #120]

0x417554 HINT	#0

0x417558 HINT	#0

0x41755c HINT	#0

(86) 0x417560 STR	WZR, [X2, X0,LSL #2]

(86) 0x417564 ADD	X0, X0, #1

(86) 0x417568 LDR	W3, [X20, #20]

(86) 0x41756c CMP	W3, W0

(86) 0x417570 B.GT	417560

0x417574 LDR	W2, [X20, #12]

0x417578 CMP	W2, #0

0x41757c B.LE	4177a4

0x417580 MOVZ	W26, #24

0x417584 STP	X21, X22, [SP, #32]

0x417588 MOVZ	X22, #0

0x41758c STP	X23, X24, [SP, #48]

0x417590 LDR	X5, [X20, #120]

0x417594 STR	X27, [SP, #80]

0x417598 HINT	#0

0x41759c HINT	#0

(84) 0x4175a0 LDR	W4, [X5, X22,LSL #2]

(84) 0x4175a4 ORR	W27, WZR, W22

(84) 0x4175a8 UBFM	W19, W22, #26, #25

(84) 0x4175ac UBFM	X24, X22, #62, #61

(84) 0x4175b0 CMP	W4, #0

(84) 0x4175b4 B.LE	41778c

(84) 0x4175b8 LDP	D19, D18, [X20, #24]

(84) 0x4175bc MOVZ	W21, #0

(84) 0x4175c0 ORR	W23, WZR, W19

(84) 0x4175c4 LDP	D17, D5, [X20, #40]

(84) 0x4175c8 LDP	D4, D3, [X20, #56]

(84) 0x4175cc LDP	D16, D7, [X20, #96]

(84) 0x4175d0 LDR	D6, [X20, #112]

(84) 0x4175d4 LDP	W2, W0, [X20]

(84) 0x4175d8 LDR	W1, [X20, #8]

(84) 0x4175dc LDR	X3, [X25, #24]

  (85) 0x4175e0 SMULL	X6, W23, W26

  (85) 0x4175e4 ORR	W11, WZR, W2

  (85) 0x4175e8 LDR	D2, [X3, X6]

  (85) 0x4175ec ADD	X7, X3, X6

  (85) 0x4175f0 LDP	D1, D0, [X7, #8]

  (85) 0x4175f4 FCMPE	D2, D5

  (85) 0x4175f8 B.GE	417614

  (85) 0x4175fc FSUB	D20, D2, S19

  (85) 0x417600 FMUL	D21, D20, D16

  (85) 0x417604 FCVTMS	W8, D21

  (85) 0x417608 CMP	W8, W2

  (85) 0x41760c CSINC	W9, WZR, WZR, #1

  (85) 0x417610 SUB	W11, W8, W9

  (85) 0x417614 FCMPE	D1, D4

  (85) 0x417618 ORR	W13, WZR, W0

  (85) 0x41761c B.GE	417638

  (85) 0x417620 FSUB	D22, D1, S18

  (85) 0x417624 FMUL	D23, D22, D7

  (85) 0x417628 FCVTMS	W10, D23

  (85) 0x41762c CMP	W10, W0

  (85) 0x417630 CSINC	W12, WZR, WZR, #1

  (85) 0x417634 SUB	W13, W10, W12

  (85) 0x417638 FCMPE	D0, D3

  (85) 0x41763c B.GE	417704

  (85) 0x417640 FSUB	D24, D0, S17

  (85) 0x417644 FMUL	D25, D24, D6

  (85) 0x417648 FCVTMS	W10, D25

  (85) 0x41764c CMP	W10, W1

  (85) 0x417650 CSINC	W12, WZR, WZR, #1

  (85) 0x417654 SUB	W14, W10, W12

  (85) 0x417658 CMN	W14, #1

  (85) 0x41765c B.EQ	417738

  (85) 0x417660 CMP	W13, W0

  (85) 0x417664 B.EQ	417764

  (85) 0x417668 CMN	W13, #1

  (85) 0x41766c B.EQ	4177b4

  (85) 0x417670 CMP	W11, W2

  (85) 0x417674 B.EQ	4177d4

  (85) 0x417678 CMN	W11, #1

  (85) 0x41767c B.EQ	4177e8

  (85) 0x417680 MADD	W11, W13, W2, W11

  (85) 0x417684 MUL	W13, W0, W2

  (85) 0x417688 MADD	W4, W13, W14, W11

  (85) 0x41768c TBNZ	W4, #31, 4177f8

  (85) 0x417690 LDR	W13, [X20, #20]

  (85) 0x417694 CMP	W4, W13

  (85) 0x417698 B.GE	417818

  (85) 0x41769c CMP	W4, W22

  (85) 0x4176a0 B.EQ	4176ec

  (85) 0x4176a4 ORR	X1, XZR, X25

  (85) 0x4176a8 ORR	W3, WZR, W27

  (85) 0x4176ac ORR	W2, WZR, W21

  (85) 0x4176b0 ORR	X0, XZR, X20

  (85) 0x4176b4 BL	41738c

  (85) 0x4176b8 LDR	X5, [X20, #120]

  (85) 0x4176bc LDR	W1, [X5, X24]

  (85) 0x4176c0 CMP	W21, W1

  (85) 0x4176c4 B.GE	417788

  (85) 0x4176c8 LDP	W2, W0, [X20]

  (85) 0x4176cc LDR	W1, [X20, #8]

  (85) 0x4176d0 LDP	D19, D18, [X20, #24]

  (85) 0x4176d4 LDR	X3, [X25, #24]

  (85) 0x4176d8 LDP	D17, D5, [X20, #40]

  (85) 0x4176dc LDP	D4, D3, [X20, #56]

  (85) 0x4176e0 LDP	D16, D7, [X20, #96]

  (85) 0x4176e4 LDR	D6, [X20, #112]

  (85) 0x4176e8 B	4175e0

  (85) 0x4176ec LDR	W11, [X5, X24]

  (85) 0x4176f0 ADD	W21, W21, #1

  (85) 0x4176f4 CMP	W11, W21

  (85) 0x4176f8 B.LE	417788

  (85) 0x4176fc ADD	W23, W19, W21

  (85) 0x417700 B	4175e0

  (85) 0x417704 LDR	W4, [X20, #12]

  (85) 0x417708 ADD	W15, W2, #2

  (85) 0x41770c MUL	W14, W1, W0

  (85) 0x417710 ADD	W16, W0, #2

  (85) 0x417714 ADD	W17, W11, #1

  (85) 0x417718 MUL	W18, W15, W1

  (85) 0x41771c MADD	W30, W13, W15, W15

  (85) 0x417720 ADD	W6, W4, W14,LSL #1

  (85) 0x417724 ADD	W7, W6, W18,LSL #1

  (85) 0x417728 MADD	W8, W16, W15, W7

  (85) 0x41772c ADD	W9, W8, W30

  (85) 0x417730 ADD	W4, W9, W17

  (85) 0x417734 B	41768c

  (85) 0x417738 LDR	W8, [X20, #12]

  (85) 0x41773c ADD	W30, W2, #2

  (85) 0x417740 MUL	W18, W1, W0

  (85) 0x417744 ADD	W6, W11, #1

  (85) 0x417748 MUL	W4, W30, W1

  (85) 0x41774c MADD	W7, W13, W30, W30

  (85) 0x417750 ADD	W9, W8, W18,LSL #1

  (85) 0x417754 ADD	W10, W9, W4,LSL #1

  (85) 0x417758 ADD	W12, W10, W7

  (85) 0x41775c ADD	W4, W12, W6

  (85) 0x417760 B	41768c

  (85) 0x417764 LDR	W15, [X20, #12]

  (85) 0x417768 MUL	W12, W1, W0

  (85) 0x41776c ADD	W13, W2, #2

  (85) 0x417770 ADD	W11, W11, #1

  (85) 0x417774 ADD	W16, W15, W12,LSL #1

  (85) 0x417778 MADD	W17, W13, W1, W16

  (85) 0x41777c MADD	W14, W14, W13, W17

  (85) 0x417780 ADD	W4, W14, W11

  (85) 0x417784 B	41768c

(84) 0x417788 LDR	W2, [X20, #12]

(84) 0x41778c ADD	X22, X22, #1

(84) 0x417790 CMP	W2, W22

(84) 0x417794 B.GT	4175a0

0x417798 LDP	X21, X22, [SP, #32]

0x41779c LDP	X23, X24, [SP, #48]

0x4177a0 LDR	X27, [SP, #80]

0x4177a4 LDP	X19, X20, [SP, #16]

0x4177a8 LDP	X25, X26, [SP, #64]

0x4177ac LDP	X29, X30, [SP], #96

0x4177b0 RET

  (85) 0x4177b4 LDR	W8, [X20, #12]

  (85) 0x4177b8 MUL	W7, W1, W0

  (85) 0x4177bc ADD	W4, W2, #2

  (85) 0x4177c0 ADD	W6, W11, #1

  (85) 0x4177c4 ADD	W9, W8, W7,LSL #1

  (85) 0x4177c8 MADD	W10, W4, W14, W9

  (85) 0x4177cc ADD	W4, W10, W6

  (85) 0x4177d0 B	41768c

  (85) 0x4177d4 LDR	W17, [X20, #12]

  (85) 0x4177d8 MADD	W18, W1, W0, W17

  (85) 0x4177dc MADD	W30, W14, W0, W18

  (85) 0x4177e0 ADD	W4, W30, W13

  (85) 0x4177e4 B	41768c

  (85) 0x4177e8 LDR	W15, [X20, #12]

  (85) 0x4177ec MADD	W16, W14, W0, W15

  (85) 0x4177f0 ADD	W4, W16, W13

  (85) 0x4177f4 B	41768c

0x4177f8 ADRP	X5,

0x4177fc ADRP	X21,

0x417800 ADRP	X22,

0x417804 ADD	X3, X5, #3440

0x417808 ADD	X1, X21, #2960

0x41780c ADD	X0, X22, #3056

0x417810 MOVZ	W2, #246

0x417814 BL	4101c0

0x417818 ADRP	X23,

0x41781c ADRP	X20,

0x417820 ADRP	X25,

0x417824 ADD	X3, X23, #3440

0x417828 ADD	X1, X20, #2960

0x41782c ADD	X0, X25, #3072

0x417830 MOVZ	W2, #247

0x417834 BL	4101c0

0x417838 HINT	#0

0x41783c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.08+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,288-304,352-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 6.25 to 1.88 cycles (3.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes.

General properties

nb instructions	51
nb uops	44
loop length	204
used w registers	3
used x registers	17
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	3.00	3.00
cycles	2.50	2.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Dispatch	6.25
Overall L1	6.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	29%
store	45%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.25 cycles. At this rate:

1% of peak load performance is reached (1.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 417524

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W2, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W1, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 417578 <updateLinkCells+0x54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X0, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W2, [X20, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4177a4 <updateLinkCells+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W26, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X5, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <4217f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X21, <4207fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X22, <420800>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X5, #3440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X21, #2960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X22, #3056	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #246	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X23, <421818>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X20, <42081c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X25, <420820>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X23, #3440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X20, #2960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X25, #3072	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #247	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,288-304,352-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 9 bytes.

General properties

nb instructions	51
nb uops	44
loop length	204
used w registers	3
used x registers	17
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	3.00	3.00
cycles	2.50	2.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Dispatch	6.25
Overall L1	6.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	29%
store	45%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.25 cycles. At this rate:

1% of peak load performance is reached (1.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 417524

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W2, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W1, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 417578 <updateLinkCells+0x54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X0, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR W2, [X20, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4177a4 <updateLinkCells+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W26, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X5, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <4217f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X21, <4207fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X22, <420800>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X5, #3440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X21, #2960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X22, #3056	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #246	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X23, <421818>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X20, <42081c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X25, <420820>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X23, #3440	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X20, #2960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X25, #3072	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #247	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.46	0.07
▼Loop 84 - linkCells.c:211-373 - exec–	0.00	0.03
○Loop 85 - linkCells.c:211-373 - exec	0.45	3.23
○Loop 86 - linkCells.c:384-385 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code