OV - exec - Function advanceVelocity._omp

	Function: advanceVelocity._omp_fn.0	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 2.13% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x41a400 STP	X29, X30, [SP, #976]!

0x41a404 ADD	X29, SP, #0

0x41a408 STR	X21, [SP, #32]

0x41a40c LDR	W21, [X0, #16]

0x41a410 STP	X19, X20, [SP, #16]

0x41a414 ORR	X20, XZR, X0

0x41a418 BL	410120

0x41a41c ORR	W19, WZR, W0

0x41a420 BL	410140

0x41a424 SDIV	W11, W21, W19

0x41a428 ORR	W8, WZR, W0

0x41a42c MSUB	W1, W11, W19, W21

0x41a430 CMP	W0, W1

0x41a434 B.LT	41a870

0x41a438 MADD	W2, W11, W8, W1

0x41a43c ADD	W30, W11, W2

0x41a440 CMP	W2, W30

0x41a444 B.GE	41a68c

0x41a448 LDR	X13, [X20]

0x41a44c MOVZ	W0, #1536

0x41a450 SBFM	X9, X2, #0, #31

0x41a454 MOVZ	W14, #48

0x41a458 MOVZ	W10, #24

0x41a45c LDR	D0, [X20, #8]

0x41a460 SMULL	X8, W2, W0

0x41a464 LDR	X3, [X13, #24]

0x41a468 DUP	V3.2D, V0.D[0]

0x41a46c LDR	X12, [X3, #120]

(103) 0x41a470 UBFM	W20, W9, #26, #25

(103) 0x41a474 LDR	W6, [X12, X9,LSL #2]

(103) 0x41a478 CMP	W6, #0

(103) 0x41a47c B.LE	41a67c

(103) 0x41a480 LDR	X4, [X13, #32]

(103) 0x41a484 ADD	X5, X8, #48

(103) 0x41a488 LDP	X21, X19, [X4, #32]

(103) 0x41a48c ADD	X7, X21, X5

(103) 0x41a490 ADD	X16, X19, X8

(103) 0x41a494 ADD	X15, X21, X8

(103) 0x41a498 ADD	X17, X19, X5

(103) 0x41a49c CMP	X16, X7

(103) 0x41a4a0 CCMP	X15, X17, #2, #3

(103) 0x41a4a4 CCMP	W6, #1, #4, #2

(103) 0x41a4a8 B.EQ	41a69c

(103) 0x41a4ac UBFM	W18, W6, #1, #31

(103) 0x41a4b0 ADD	X11, X15, #48

(103) 0x41a4b4 SUB	W0, W18, #1

(103) 0x41a4b8 MOVZ	X3, #43691

(103) 0x41a4bc MOVK	X3, #43690

(103) 0x41a4c0 ORR	X1, XZR, X15

(103) 0x41a4c4 UMADDL	X4, W0, W14, X11

(103) 0x41a4c8 MOVK	X3, #43690

(103) 0x41a4cc ORR	X2, XZR, X16

(103) 0x41a4d0 MOVK	X3, #2730

(103) 0x41a4d4 SUB	X5, X4, X15

(103) 0x41a4d8 SUB	X7, X5, #48

(103) 0x41a4dc UBFM	X17, X7, #4, #63

(103) 0x41a4e0 MUL	X18, X17, X3

(103) 0x41a4e4 ADD	X0, X18, #1

(103) 0x41a4e8 ANDS	X3, X0, #0x3

(103) 0x41a4ec B.EQ	41a58c

(103) 0x41a4f0 CMP	X3, #1

(103) 0x41a4f4 B.EQ	41a558

(103) 0x41a4f8 CMP	X3, #2

(103) 0x41a4fc B.EQ	41a52c

(103) 0x41a500 LDP	Q1, Q6, [X16]

(103) 0x41a504 ORR	X1, XZR, X11

(103) 0x41a508 ADD	X2, X16, #48

(103) 0x41a50c LDP	Q4, Q2, [X15]

(103) 0x41a510 LDR	Q5, [X16, #32]

(103) 0x41a514 LDR	Q7, [X15, #32]

(103) 0x41a518 FMLA	V4.2D, V3.2D, V1.2D

(103) 0x41a51c FMLA	V2.2D, V3.2D, V6.2D

(103) 0x41a520 FMLA	V7.2D, V3.2D, V5.2D

(103) 0x41a524 STP	Q4, Q2, [X15]

(103) 0x41a528 STR	Q7, [X15, #32]

(103) 0x41a52c LDP	Q18, Q19, [X2]

(103) 0x41a530 ADD	X2, X2, #48

(103) 0x41a534 LDP	Q16, Q17, [X1]

(103) 0x41a538 LDUR	Q20, [X2, #496]

(103) 0x41a53c LDR	Q21, [X1, #32]

(103) 0x41a540 FMLA	V16.2D, V3.2D, V18.2D

(103) 0x41a544 FMLA	V17.2D, V3.2D, V19.2D

(103) 0x41a548 FMLA	V21.2D, V3.2D, V20.2D

(103) 0x41a54c STP	Q16, Q17, [X1]

(103) 0x41a550 ADD	X1, X1, #48

(103) 0x41a554 STUR	Q21, [X1, #496]

(103) 0x41a558 LDP	Q24, Q25, [X2]

(103) 0x41a55c ADD	X2, X2, #48

(103) 0x41a560 LDP	Q22, Q23, [X1]

(103) 0x41a564 LDUR	Q26, [X2, #496]

(103) 0x41a568 LDR	Q27, [X1, #32]

(103) 0x41a56c FMLA	V22.2D, V3.2D, V24.2D

(103) 0x41a570 FMLA	V23.2D, V3.2D, V25.2D

(103) 0x41a574 FMLA	V27.2D, V3.2D, V26.2D

(103) 0x41a578 STP	Q22, Q23, [X1]

(103) 0x41a57c ADD	X1, X1, #48

(103) 0x41a580 STUR	Q27, [X1, #496]

(103) 0x41a584 CMP	X1, X4

(103) 0x41a588 B.EQ	41a634

  (105) 0x41a58c LDP	Q30, Q31, [X2]

  (105) 0x41a590 ADD	X15, X2, #144

  (105) 0x41a594 ADD	X16, X1, #144

  (105) 0x41a598 LDP	Q28, Q29, [X1]

  (105) 0x41a59c LDP	Q1, Q4, [X1, #32]

  (105) 0x41a5a0 LDR	Q2, [X2, #32]

  (105) 0x41a5a4 LDR	Q7, [X1, #64]

  (105) 0x41a5a8 LDR	Q17, [X1, #80]

  (105) 0x41a5ac FMLA	V28.2D, V3.2D, V30.2D

  (105) 0x41a5b0 LDP	Q18, Q19, [X1, #96]

  (105) 0x41a5b4 FMLA	V29.2D, V3.2D, V31.2D

  (105) 0x41a5b8 LDR	Q23, [X1, #128]

  (105) 0x41a5bc LDP	Q24, Q25, [X1, #144]

  (105) 0x41a5c0 FMLA	V1.2D, V3.2D, V2.2D

  (105) 0x41a5c4 STP	Q28, Q29, [X1]

  (105) 0x41a5c8 STR	Q1, [X1, #32]

  (105) 0x41a5cc LDP	Q16, Q6, [X2, #48]

  (105) 0x41a5d0 LDR	Q5, [X2, #80]

  (105) 0x41a5d4 FMLA	V17.2D, V3.2D, V5.2D

  (105) 0x41a5d8 FMLA	V4.2D, V3.2D, V16.2D

  (105) 0x41a5dc FMLA	V7.2D, V3.2D, V6.2D

  (105) 0x41a5e0 STR	Q17, [X1, #80]

  (105) 0x41a5e4 STP	Q4, Q7, [X1, #48]

  (105) 0x41a5e8 LDP	Q20, Q21, [X2, #96]

  (105) 0x41a5ec LDR	Q22, [X2, #128]

  (105) 0x41a5f0 FMLA	V23.2D, V3.2D, V22.2D

  (105) 0x41a5f4 FMLA	V18.2D, V3.2D, V20.2D

  (105) 0x41a5f8 FMLA	V19.2D, V3.2D, V21.2D

  (105) 0x41a5fc STR	Q23, [X1, #128]

  (105) 0x41a600 STP	Q18, Q19, [X1, #96]

  (105) 0x41a604 LDP	Q26, Q27, [X2, #144]

  (105) 0x41a608 ADD	X1, X1, #192

  (105) 0x41a60c ADD	X2, X2, #192

  (105) 0x41a610 LDR	Q28, [X15, #32]

  (105) 0x41a614 LDUR	Q29, [X1, #496]

  (105) 0x41a618 FMLA	V24.2D, V3.2D, V26.2D

  (105) 0x41a61c FMLA	V25.2D, V3.2D, V27.2D

  (105) 0x41a620 FMLA	V29.2D, V3.2D, V28.2D

  (105) 0x41a624 STUR	Q24, [X1, #464]

  (105) 0x41a628 STP	Q25, Q29, [X16, #16]

  (105) 0x41a62c CMP	X1, X4

  (105) 0x41a630 B.NE	41a58c

(103) 0x41a634 AND	W11, W6, #0xfffffffe

(103) 0x41a638 ADD	W20, W11, W20

(103) 0x41a63c CMP	W6, W11

(103) 0x41a640 B.EQ	41a67c

(103) 0x41a644 SMULL	X6, W20, W10

(103) 0x41a648 LDR	D30, [X19, X6]

(103) 0x41a64c ADD	X4, X21, X6

(103) 0x41a650 ADD	X19, X19, X6

(103) 0x41a654 LDR	D31, [X21, X6]

(103) 0x41a658 FMADD	D2, D0, D30, D31

(103) 0x41a65c STR	D2, [X21, X6]

(103) 0x41a660 LDP	D7, D1, [X4, #8]

(103) 0x41a664 LDR	D4, [X19, #8]

(103) 0x41a668 FMADD	D16, D0, D4, D7

(103) 0x41a66c STR	D16, [X4, #8]

(103) 0x41a670 LDR	D6, [X19, #16]

(103) 0x41a674 FMADD	D5, D0, D6, D1

(103) 0x41a678 STR	D5, [X4, #16]

(103) 0x41a67c ADD	X9, X9, #1

(103) 0x41a680 ADD	X8, X8, #1536

(103) 0x41a684 CMP	W30, W9

(103) 0x41a688 B.GT	41a470

0x41a68c LDP	X19, X20, [SP, #16]

0x41a690 LDR	X21, [SP, #32]

0x41a694 LDP	X29, X30, [SP], #48

0x41a698 RET

(103) 0x41a69c SUB	W5, W6, #1

(103) 0x41a6a0 ADD	X21, X21, #24

(103) 0x41a6a4 ADD	X7, X5, X9,LSL #6

(103) 0x41a6a8 MOVZ	X17, #43691

(103) 0x41a6ac ORR	X0, XZR, X15

(103) 0x41a6b0 MOVK	X17, #43690

(103) 0x41a6b4 ORR	X1, XZR, X16

(103) 0x41a6b8 ADD	X18, X7, X7,LSL #1

(103) 0x41a6bc MOVK	X17, #43690

(103) 0x41a6c0 MOVK	X17, #2730

(103) 0x41a6c4 ADD	X3, X21, X18,LSL #3

(103) 0x41a6c8 SUB	X2, X3, X15

(103) 0x41a6cc SUB	X11, X2, #24

(103) 0x41a6d0 UBFM	X20, X11, #3, #63

(103) 0x41a6d4 MUL	X6, X20, X17

(103) 0x41a6d8 ADD	X19, X6, #1

(103) 0x41a6dc ANDS	X4, X19, #0x3

(103) 0x41a6e0 B.EQ	41a798

(103) 0x41a6e4 CMP	X4, #1

(103) 0x41a6e8 B.EQ	41a75c

(103) 0x41a6ec CMP	X4, #2

(103) 0x41a6f0 B.EQ	41a728

(103) 0x41a6f4 LDP	D17, D18, [X15]

(103) 0x41a6f8 ADD	X0, X15, #24

(103) 0x41a6fc ADD	X1, X16, #24

(103) 0x41a700 LDR	D20, [X16]

(103) 0x41a704 LDR	D19, [X15, #16]

(103) 0x41a708 FMADD	D21, D0, D20, D17

(103) 0x41a70c STR	D21, [X15]

(103) 0x41a710 LDR	D22, [X16, #8]

(103) 0x41a714 FMADD	D23, D0, D22, D18

(103) 0x41a718 STR	D23, [X15, #8]

(103) 0x41a71c LDR	D24, [X16, #16]

(103) 0x41a720 FMADD	D25, D24, D0, D19

(103) 0x41a724 STR	D25, [X15, #16]

(103) 0x41a728 LDP	D26, D27, [X0]

(103) 0x41a72c ADD	X1, X1, #24

(103) 0x41a730 ADD	X0, X0, #24

(103) 0x41a734 LDUR	D29, [X1, #488]

(103) 0x41a738 LDUR	D28, [X0, #504]

(103) 0x41a73c FMADD	D30, D0, D29, D26

(103) 0x41a740 STUR	D30, [X0, #488]

(103) 0x41a744 LDUR	D31, [X1, #496]

(103) 0x41a748 FMADD	D2, D0, D31, D27

(103) 0x41a74c STUR	D2, [X0, #496]

(103) 0x41a750 LDUR	D7, [X1, #504]

(103) 0x41a754 FMADD	D1, D7, D0, D28

(103) 0x41a758 STUR	D1, [X0, #504]

(103) 0x41a75c LDP	D4, D16, [X0]

(103) 0x41a760 ADD	X0, X0, #24

(103) 0x41a764 ADD	X1, X1, #24

(103) 0x41a768 LDUR	D5, [X1, #488]

(103) 0x41a76c LDUR	D6, [X0, #504]

(103) 0x41a770 FMADD	D17, D0, D5, D4

(103) 0x41a774 STUR	D17, [X0, #488]

(103) 0x41a778 LDUR	D18, [X1, #496]

(103) 0x41a77c FMADD	D19, D0, D18, D16

(103) 0x41a780 STUR	D19, [X0, #496]

(103) 0x41a784 LDUR	D20, [X1, #504]

(103) 0x41a788 FMADD	D21, D20, D0, D6

(103) 0x41a78c STUR	D21, [X0, #504]

(103) 0x41a790 CMP	X3, X0

(103) 0x41a794 B.EQ	41a67c

  (104) 0x41a798 LDR	D25, [X1]

  (104) 0x41a79c ADD	X16, X0, #72

  (104) 0x41a7a0 ADD	X15, X1, #72

  (104) 0x41a7a4 ADD	X1, X1, #96

  (104) 0x41a7a8 LDP	D22, D23, [X0]

  (104) 0x41a7ac ADD	X0, X0, #96

  (104) 0x41a7b0 LDUR	D24, [X0, #432]

  (104) 0x41a7b4 LDUR	D27, [X0, #440]

  (104) 0x41a7b8 FMADD	D26, D0, D25, D22

  (104) 0x41a7bc LDUR	D16, [X0, #448]

  (104) 0x41a7c0 LDUR	D1, [X0, #456]

  (104) 0x41a7c4 LDUR	D18, [X0, #464]

  (104) 0x41a7c8 LDUR	D21, [X0, #472]

  (104) 0x41a7cc LDUR	D22, [X0, #480]

  (104) 0x41a7d0 STUR	D26, [X0, #416]

  (104) 0x41a7d4 LDUR	D28, [X1, #424]

  (104) 0x41a7d8 FMADD	D29, D0, D28, D23

  (104) 0x41a7dc STUR	D29, [X0, #424]

  (104) 0x41a7e0 LDUR	D30, [X1, #432]

  (104) 0x41a7e4 FMADD	D31, D30, D0, D24

  (104) 0x41a7e8 STUR	D31, [X0, #432]

  (104) 0x41a7ec LDUR	D2, [X1, #440]

  (104) 0x41a7f0 FMADD	D7, D0, D2, D27

  (104) 0x41a7f4 LDUR	D27, [X0, #488]

  (104) 0x41a7f8 STUR	D7, [X0, #440]

  (104) 0x41a7fc LDUR	D4, [X1, #448]

  (104) 0x41a800 FMADD	D6, D0, D4, D16

  (104) 0x41a804 STUR	D6, [X0, #448]

  (104) 0x41a808 LDUR	D5, [X1, #456]

  (104) 0x41a80c FMADD	D17, D5, D0, D1

  (104) 0x41a810 STUR	D17, [X0, #456]

  (104) 0x41a814 LDUR	D19, [X1, #464]

  (104) 0x41a818 FMADD	D20, D0, D19, D18

  (104) 0x41a81c STUR	D20, [X0, #464]

  (104) 0x41a820 LDUR	D23, [X1, #472]

  (104) 0x41a824 FMADD	D24, D0, D23, D21

  (104) 0x41a828 STUR	D24, [X0, #472]

  (104) 0x41a82c LDUR	D25, [X1, #480]

  (104) 0x41a830 FMADD	D26, D25, D0, D22

  (104) 0x41a834 STUR	D26, [X0, #480]

  (104) 0x41a838 LDUR	D28, [X1, #488]

  (104) 0x41a83c FMADD	D29, D0, D28, D27

  (104) 0x41a840 STUR	D29, [X0, #488]

  (104) 0x41a844 LDR	D30, [X16, #8]

  (104) 0x41a848 LDR	D31, [X15, #8]

  (104) 0x41a84c FMADD	D2, D0, D31, D30

  (104) 0x41a850 STR	D2, [X16, #8]

  (104) 0x41a854 LDR	D7, [X16, #16]

  (104) 0x41a858 LDR	D16, [X15, #16]

  (104) 0x41a85c FMADD	D1, D16, D0, D7

  (104) 0x41a860 STR	D1, [X16, #16]

  (104) 0x41a864 CMP	X3, X0

  (104) 0x41a868 B.NE	41a798

(103) 0x41a86c B	41a67c

0x41a870 ADD	W11, W11, #1

0x41a874 MOVZ	W1, #0

0x41a878 B	41a438

0x41a87c HINT	#0

Coverage (%)	Name	Module
►98.48+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 26% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 4.75 cycles (2.63x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	36
nb uops	35
loop length	144
used w registers	11
used x registers	13
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	2
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.38 cycles
front end	4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.00	5.00	5.00	5.00	0.25	0.25	0.25	0.25	3.83	3.50	3.67	1.50	1.50
cycles	3.00	3.00	5.00	5.00	5.00	5.00	0.25	0.25	0.25	0.25	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	4.38
Dispatch	5.00
DIV/SQRT	5.00-12.50
Overall L1	5.00-12.50

Vectorization ratios

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

all	26%
load	27%
store	41%
mul	12%
add-sub	18%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 41a400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV W11, W21, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W1, W11, W19, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 41a870 <advanceVelocity._omp_fn.0+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W11, W8, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W30, W11, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 41a68c <advanceVelocity._omp_fn.0+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X9, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MOVZ W14, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W10, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D0, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
SMULL X8, W2, W0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
LDR X3, [X13, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V3.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR X12, [X3, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 41a438 <advanceVelocity._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 26% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 4.75 cycles (2.63x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	36
nb uops	35
loop length	144
used w registers	11
used x registers	13
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	2
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.38 cycles
front end	4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.00	5.00	5.00	5.00	0.25	0.25	0.25	0.25	3.83	3.50	3.67	1.50	1.50
cycles	3.00	3.00	5.00	5.00	5.00	5.00	0.25	0.25	0.25	0.25	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	4.38
Dispatch	5.00
DIV/SQRT	5.00-12.50
Overall L1	5.00-12.50

Vectorization ratios

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

all	26%
load	27%
store	41%
mul	12%
add-sub	18%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 41a400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410140 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV W11, W21, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W1, W11, W19, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 41a870 <advanceVelocity._omp_fn.0+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W11, W8, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W30, W11, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 41a68c <advanceVelocity._omp_fn.0+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X9, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MOVZ W14, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W10, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR D0, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
SMULL X8, W2, W0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
LDR X3, [X13, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V3.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
LDR X12, [X3, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 41a438 <advanceVelocity._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity._omp_fn.0–	2.13	0.31
▼Loop 103 - timestep.c:71-78 - exec–	0.66	0.07
○Loop 105 - timestep.c:74-76 - exec	1.47	0.16
○Loop 104 - timestep.c:74-78 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code