OV - exec - Loop 103

	Loop Id: 103	Module: exec	Source: timestep.c:71-78	Coverage: 0.66%

0x41a470 UBFM	W20, W9, #26, #25

0x41a474 LDR	W6, [X12, X9,LSL #2]

0x41a478 CMP	W6, #0

0x41a47c B.LE	41a67c

0x41a480 LDR	X4, [X13, #32]

0x41a484 ADD	X5, X8, #48

0x41a488 LDP	X21, X19, [X4, #32]

0x41a48c ADD	X7, X21, X5

0x41a490 ADD	X16, X19, X8

0x41a494 ADD	X15, X21, X8

0x41a498 ADD	X17, X19, X5

0x41a49c CMP	X16, X7

0x41a4a0 CCMP	X15, X17, #2, #3

0x41a4a4 CCMP	W6, #1, #4, #2

0x41a4a8 B.EQ	41a69c

0x41a4ac UBFM	W18, W6, #1, #31

0x41a4b0 ADD	X11, X15, #48

0x41a4b4 SUB	W0, W18, #1

0x41a4b8 MOVZ	X3, #43691

0x41a4bc MOVK	X3, #43690

0x41a4c0 ORR	X1, XZR, X15

0x41a4c4 UMADDL	X4, W0, W14, X11

0x41a4c8 MOVK	X3, #43690

0x41a4cc ORR	X2, XZR, X16

0x41a4d0 MOVK	X3, #2730

0x41a4d4 SUB	X5, X4, X15

0x41a4d8 SUB	X7, X5, #48

0x41a4dc UBFM	X17, X7, #4, #63

0x41a4e0 MUL	X18, X17, X3

0x41a4e4 ADD	X0, X18, #1

0x41a4e8 ANDS	X3, X0, #0x3

0x41a4ec B.EQ	41a58c

0x41a4f0 CMP	X3, #1

0x41a4f4 B.EQ	41a558

0x41a4f8 CMP	X3, #2

0x41a4fc B.EQ	41a52c

0x41a500 LDP	Q1, Q6, [X16]

0x41a504 ORR	X1, XZR, X11

0x41a508 ADD	X2, X16, #48

0x41a50c LDP	Q4, Q2, [X15]

0x41a510 LDR	Q5, [X16, #32]

0x41a514 LDR	Q7, [X15, #32]

0x41a518 FMLA	V4.2D, V3.2D, V1.2D

0x41a51c FMLA	V2.2D, V3.2D, V6.2D

0x41a520 FMLA	V7.2D, V3.2D, V5.2D

0x41a524 STP	Q4, Q2, [X15]

0x41a528 STR	Q7, [X15, #32]

0x41a52c LDP	Q18, Q19, [X2]

0x41a530 ADD	X2, X2, #48

0x41a534 LDP	Q16, Q17, [X1]

0x41a538 LDUR	Q20, [X2, #496]

0x41a53c LDR	Q21, [X1, #32]

0x41a540 FMLA	V16.2D, V3.2D, V18.2D

0x41a544 FMLA	V17.2D, V3.2D, V19.2D

0x41a548 FMLA	V21.2D, V3.2D, V20.2D

0x41a54c STP	Q16, Q17, [X1]

0x41a550 ADD	X1, X1, #48

0x41a554 STUR	Q21, [X1, #496]

0x41a558 LDP	Q24, Q25, [X2]

0x41a55c ADD	X2, X2, #48

0x41a560 LDP	Q22, Q23, [X1]

0x41a564 LDUR	Q26, [X2, #496]

0x41a568 LDR	Q27, [X1, #32]

0x41a56c FMLA	V22.2D, V3.2D, V24.2D

0x41a570 FMLA	V23.2D, V3.2D, V25.2D

0x41a574 FMLA	V27.2D, V3.2D, V26.2D

0x41a578 STP	Q22, Q23, [X1]

0x41a57c ADD	X1, X1, #48

0x41a580 STUR	Q27, [X1, #496]

0x41a584 CMP	X1, X4

0x41a588 B.EQ	41a634

  (105) 0x41a58c LDP	Q30, Q31, [X2]

  (105) 0x41a590 ADD	X15, X2, #144

  (105) 0x41a594 ADD	X16, X1, #144

  (105) 0x41a598 LDP	Q28, Q29, [X1]

  (105) 0x41a59c LDP	Q1, Q4, [X1, #32]

  (105) 0x41a5a0 LDR	Q2, [X2, #32]

  (105) 0x41a5a4 LDR	Q7, [X1, #64]

  (105) 0x41a5a8 LDR	Q17, [X1, #80]

  (105) 0x41a5ac FMLA	V28.2D, V3.2D, V30.2D

  (105) 0x41a5b0 LDP	Q18, Q19, [X1, #96]

  (105) 0x41a5b4 FMLA	V29.2D, V3.2D, V31.2D

  (105) 0x41a5b8 LDR	Q23, [X1, #128]

  (105) 0x41a5bc LDP	Q24, Q25, [X1, #144]

  (105) 0x41a5c0 FMLA	V1.2D, V3.2D, V2.2D

  (105) 0x41a5c4 STP	Q28, Q29, [X1]

  (105) 0x41a5c8 STR	Q1, [X1, #32]

  (105) 0x41a5cc LDP	Q16, Q6, [X2, #48]

  (105) 0x41a5d0 LDR	Q5, [X2, #80]

  (105) 0x41a5d4 FMLA	V17.2D, V3.2D, V5.2D

  (105) 0x41a5d8 FMLA	V4.2D, V3.2D, V16.2D

  (105) 0x41a5dc FMLA	V7.2D, V3.2D, V6.2D

  (105) 0x41a5e0 STR	Q17, [X1, #80]

  (105) 0x41a5e4 STP	Q4, Q7, [X1, #48]

  (105) 0x41a5e8 LDP	Q20, Q21, [X2, #96]

  (105) 0x41a5ec LDR	Q22, [X2, #128]

  (105) 0x41a5f0 FMLA	V23.2D, V3.2D, V22.2D

  (105) 0x41a5f4 FMLA	V18.2D, V3.2D, V20.2D

  (105) 0x41a5f8 FMLA	V19.2D, V3.2D, V21.2D

  (105) 0x41a5fc STR	Q23, [X1, #128]

  (105) 0x41a600 STP	Q18, Q19, [X1, #96]

  (105) 0x41a604 LDP	Q26, Q27, [X2, #144]

  (105) 0x41a608 ADD	X1, X1, #192

  (105) 0x41a60c ADD	X2, X2, #192

  (105) 0x41a610 LDR	Q28, [X15, #32]

  (105) 0x41a614 LDUR	Q29, [X1, #496]

  (105) 0x41a618 FMLA	V24.2D, V3.2D, V26.2D

  (105) 0x41a61c FMLA	V25.2D, V3.2D, V27.2D

  (105) 0x41a620 FMLA	V29.2D, V3.2D, V28.2D

  (105) 0x41a624 STUR	Q24, [X1, #464]

  (105) 0x41a628 STP	Q25, Q29, [X16, #16]

  (105) 0x41a62c CMP	X1, X4

  (105) 0x41a630 B.NE	41a58c

0x41a634 AND	W11, W6, #0xfffffffe

0x41a638 ADD	W20, W11, W20

0x41a63c CMP	W6, W11

0x41a640 B.EQ	41a67c

0x41a644 SMULL	X6, W20, W10

0x41a648 LDR	D30, [X19, X6]

0x41a64c ADD	X4, X21, X6

0x41a650 ADD	X19, X19, X6

0x41a654 LDR	D31, [X21, X6]

0x41a658 FMADD	D2, D0, D30, D31

0x41a65c STR	D2, [X21, X6]

0x41a660 LDP	D7, D1, [X4, #8]

0x41a664 LDR	D4, [X19, #8]

0x41a668 FMADD	D16, D0, D4, D7

0x41a66c STR	D16, [X4, #8]

0x41a670 LDR	D6, [X19, #16]

0x41a674 FMADD	D5, D0, D6, D1

0x41a678 STR	D5, [X4, #16]

0x41a67c ADD	X9, X9, #1

0x41a680 ADD	X8, X8, #1536

0x41a684 CMP	W30, W9

0x41a688 B.GT	41a470

0x41a69c SUB	W5, W6, #1

0x41a6a0 ADD	X21, X21, #24

0x41a6a4 ADD	X7, X5, X9,LSL #6

0x41a6a8 MOVZ	X17, #43691

0x41a6ac ORR	X0, XZR, X15

0x41a6b0 MOVK	X17, #43690

0x41a6b4 ORR	X1, XZR, X16

0x41a6b8 ADD	X18, X7, X7,LSL #1

0x41a6bc MOVK	X17, #43690

0x41a6c0 MOVK	X17, #2730

0x41a6c4 ADD	X3, X21, X18,LSL #3

0x41a6c8 SUB	X2, X3, X15

0x41a6cc SUB	X11, X2, #24

0x41a6d0 UBFM	X20, X11, #3, #63

0x41a6d4 MUL	X6, X20, X17

0x41a6d8 ADD	X19, X6, #1

0x41a6dc ANDS	X4, X19, #0x3

0x41a6e0 B.EQ	41a798

0x41a6e4 CMP	X4, #1

0x41a6e8 B.EQ	41a75c

0x41a6ec CMP	X4, #2

0x41a6f0 B.EQ	41a728

0x41a6f4 LDP	D17, D18, [X15]

0x41a6f8 ADD	X0, X15, #24

0x41a6fc ADD	X1, X16, #24

0x41a700 LDR	D20, [X16]

0x41a704 LDR	D19, [X15, #16]

0x41a708 FMADD	D21, D0, D20, D17

0x41a70c STR	D21, [X15]

0x41a710 LDR	D22, [X16, #8]

0x41a714 FMADD	D23, D0, D22, D18

0x41a718 STR	D23, [X15, #8]

0x41a71c LDR	D24, [X16, #16]

0x41a720 FMADD	D25, D24, D0, D19

0x41a724 STR	D25, [X15, #16]

0x41a728 LDP	D26, D27, [X0]

0x41a72c ADD	X1, X1, #24

0x41a730 ADD	X0, X0, #24

0x41a734 LDUR	D29, [X1, #488]

0x41a738 LDUR	D28, [X0, #504]

0x41a73c FMADD	D30, D0, D29, D26

0x41a740 STUR	D30, [X0, #488]

0x41a744 LDUR	D31, [X1, #496]

0x41a748 FMADD	D2, D0, D31, D27

0x41a74c STUR	D2, [X0, #496]

0x41a750 LDUR	D7, [X1, #504]

0x41a754 FMADD	D1, D7, D0, D28

0x41a758 STUR	D1, [X0, #504]

0x41a75c LDP	D4, D16, [X0]

0x41a760 ADD	X0, X0, #24

0x41a764 ADD	X1, X1, #24

0x41a768 LDUR	D5, [X1, #488]

0x41a76c LDUR	D6, [X0, #504]

0x41a770 FMADD	D17, D0, D5, D4

0x41a774 STUR	D17, [X0, #488]

0x41a778 LDUR	D18, [X1, #496]

0x41a77c FMADD	D19, D0, D18, D16

0x41a780 STUR	D19, [X0, #496]

0x41a784 LDUR	D20, [X1, #504]

0x41a788 FMADD	D21, D20, D0, D6

0x41a78c STUR	D21, [X0, #504]

0x41a790 CMP	X3, X0

0x41a794 B.EQ	41a67c

  (104) 0x41a798 LDR	D25, [X1]

  (104) 0x41a79c ADD	X16, X0, #72

  (104) 0x41a7a0 ADD	X15, X1, #72

  (104) 0x41a7a4 ADD	X1, X1, #96

  (104) 0x41a7a8 LDP	D22, D23, [X0]

  (104) 0x41a7ac ADD	X0, X0, #96

  (104) 0x41a7b0 LDUR	D24, [X0, #432]

  (104) 0x41a7b4 LDUR	D27, [X0, #440]

  (104) 0x41a7b8 FMADD	D26, D0, D25, D22

  (104) 0x41a7bc LDUR	D16, [X0, #448]

  (104) 0x41a7c0 LDUR	D1, [X0, #456]

  (104) 0x41a7c4 LDUR	D18, [X0, #464]

  (104) 0x41a7c8 LDUR	D21, [X0, #472]

  (104) 0x41a7cc LDUR	D22, [X0, #480]

  (104) 0x41a7d0 STUR	D26, [X0, #416]

  (104) 0x41a7d4 LDUR	D28, [X1, #424]

  (104) 0x41a7d8 FMADD	D29, D0, D28, D23

  (104) 0x41a7dc STUR	D29, [X0, #424]

  (104) 0x41a7e0 LDUR	D30, [X1, #432]

  (104) 0x41a7e4 FMADD	D31, D30, D0, D24

  (104) 0x41a7e8 STUR	D31, [X0, #432]

  (104) 0x41a7ec LDUR	D2, [X1, #440]

  (104) 0x41a7f0 FMADD	D7, D0, D2, D27

  (104) 0x41a7f4 LDUR	D27, [X0, #488]

  (104) 0x41a7f8 STUR	D7, [X0, #440]

  (104) 0x41a7fc LDUR	D4, [X1, #448]

  (104) 0x41a800 FMADD	D6, D0, D4, D16

  (104) 0x41a804 STUR	D6, [X0, #448]

  (104) 0x41a808 LDUR	D5, [X1, #456]

  (104) 0x41a80c FMADD	D17, D5, D0, D1

  (104) 0x41a810 STUR	D17, [X0, #456]

  (104) 0x41a814 LDUR	D19, [X1, #464]

  (104) 0x41a818 FMADD	D20, D0, D19, D18

  (104) 0x41a81c STUR	D20, [X0, #464]

  (104) 0x41a820 LDUR	D23, [X1, #472]

  (104) 0x41a824 FMADD	D24, D0, D23, D21

  (104) 0x41a828 STUR	D24, [X0, #472]

  (104) 0x41a82c LDUR	D25, [X1, #480]

  (104) 0x41a830 FMADD	D26, D25, D0, D22

  (104) 0x41a834 STUR	D26, [X0, #480]

  (104) 0x41a838 LDUR	D28, [X1, #488]

  (104) 0x41a83c FMADD	D29, D0, D28, D27

  (104) 0x41a840 STUR	D29, [X0, #488]

  (104) 0x41a844 LDR	D30, [X16, #8]

  (104) 0x41a848 LDR	D31, [X15, #8]

  (104) 0x41a84c FMADD	D2, D0, D31, D30

  (104) 0x41a850 STR	D2, [X16, #8]

  (104) 0x41a854 LDR	D7, [X16, #16]

  (104) 0x41a858 LDR	D16, [X15, #16]

  (104) 0x41a85c FMADD	D1, D16, D0, D7

  (104) 0x41a860 STR	D1, [X16, #16]

  (104) 0x41a864 CMP	X3, X0

  (104) 0x41a868 B.NE	41a798

0x41a86c B	41a67c

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Module
►98.31+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.18
CQA speedup if FP arith vectorized	1.32
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:71-71,timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.63
CQA cycles if no scalar integer	16.67
CQA cycles if FP arith vectorized	14.88
CQA cycles if fully vectorized	11.78
Front-end cycles	19.63
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	17.50
P3 cycles	17.50
P4 cycles	17.50
P5 cycles	17.50
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	9.75
P9 cycles	9.75
P10 cycles	17.67
P11 cycles	17.67
P12 cycles	17.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	157.00
Nb uops	157.00
Nb loads	NA
Nb stores	18.00
Nb stack references	0.00
FLOP/cycle	3.06
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	30.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.15
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	29.81
Vectorization ratio load	50.00
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	42.86
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.70
Vector-efficiency ratio load	46.88
Vector-efficiency ratio store	41.67
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	35.71
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.63

Metric	Value
CQA speedup if no scalar integer	1.18
CQA speedup if FP arith vectorized	1.32
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:71-71,timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.63
CQA cycles if no scalar integer	16.67
CQA cycles if FP arith vectorized	14.88
CQA cycles if fully vectorized	11.78
Front-end cycles	19.63
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	17.50
P3 cycles	17.50
P4 cycles	17.50
P5 cycles	17.50
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	9.75
P9 cycles	9.75
P10 cycles	17.67
P11 cycles	17.67
P12 cycles	17.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	157.00
Nb uops	157.00
Nb loads	NA
Nb stores	18.00
Nb stack references	0.00
FLOP/cycle	3.06
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	30.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.15
Bytes prefetched	0.00
Bytes loaded	3.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	29.81
Vectorization ratio load	50.00
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	42.86
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.70
Vector-efficiency ratio load	46.88
Vector-efficiency ratio store	41.67
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	35.71
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:71-78
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71,74-78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=22
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 22 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.63 to 16.67 cycles (1.18x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 19.63 to 11.78 cycles (1.67x speedup).

Details

29% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
42% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 30 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

30: addition or subtraction (all inside FMA instructions)
30: multiply (all inside FMA instructions)

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 20.00 FP operations per loaded or stored byte.

General properties

nb instructions	157
nb uops	157
loop length	628
used w registers	10
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	23
used q registers	18
used v registers	19
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.63 cycles
front end	19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	17.50	17.50	17.50	17.50	9.75	9.75	9.75	9.75	17.67	17.67	17.67	0.00	0.00
cycles	6.50	6.50	17.50	17.50	17.50	17.50	9.75	9.75	9.75	9.75	17.67	17.67	17.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.63
Dispatch	17.67
Overall L1	19.63

Vectorization ratios

INT

all	26%
load	50%
store	33%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	42%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	29%
load	50%
store	33%
mul	0%
add-sub	0%
fma	42%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	35%
load	46%
store	41%
mul	25%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	35%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	35%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	35%
load	46%
store	41%
mul	25%
add-sub	22%
fma	35%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.63 cycles. At this rate:

0% of peak load performance is reached (0.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.63 to 17.67 cycles (1.11x speedup).

ASM code

In the binary file, the address of the loop is: 41a470

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
UBFM W20, W9, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W6, [X12, X9,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 41a67c <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X13, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X5, X8, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X21, X19, [X4, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
ADD X7, X21, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X19, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X15, X17, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP W6, #1, #4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.EQ 41a69c <advanceVelocity._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W18, W6, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X11, X15, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W0, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X3, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UMADDL X4, W0, W14, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MOVK X3, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X3, #2730	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X4, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X7, X5, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X17, X7, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X18, X17, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X0, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X3, X0, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a58c <advanceVelocity._omp_fn.0+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a558 <advanceVelocity._omp_fn.0+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a52c <advanceVelocity._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q1, Q6, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR X1, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X16, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q4, Q2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR Q5, [X16, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q7, [X15, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V4.2D, V3.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V2.2D, V3.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V7.2D, V3.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q4, Q2, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q7, [X15, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDP Q18, Q19, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X2, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q16, Q17, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDUR Q20, [X2, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q21, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V16.2D, V3.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V17.2D, V3.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V21.2D, V3.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q16, Q17, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q21, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDP Q24, Q25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X2, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q22, Q23, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDUR Q26, [X2, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q27, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V22.2D, V3.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V23.2D, V3.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V27.2D, V3.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q22, Q23, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q27, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a634 <advanceVelocity._omp_fn.0+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W11, W6, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W20, W11, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W6, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 41a67c <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SMULL X6, W20, W10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR D30, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X4, X21, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X19, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X21, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D2, D0, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D2, [X21, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D7, D1, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR D4, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D16, D0, D4, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D16, [X4, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D6, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D5, D0, D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D5, [X4, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W30, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GT 41a470 <advanceVelocity._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X21, X21, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X5, X9,LSL #6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MOVZ X17, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X17, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X7, X7,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X17, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X17, #2730	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X21, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X3, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X20, X11, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X6, X20, X17	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X19, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X4, X19, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a798 <advanceVelocity._omp_fn.0+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a75c <advanceVelocity._omp_fn.0+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a728 <advanceVelocity._omp_fn.0+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D17, D18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X0, X15, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X16, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D21, D0, D20, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D21, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D22, [X16, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D23, D0, D22, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D23, [X15, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D24, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D25, D24, D0, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D25, [X15, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D26, D27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D29, [X1, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDUR D28, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D30, D0, D29, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D30, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D31, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D2, D0, D31, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D2, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D7, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D1, D7, D0, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D1, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D4, D16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D5, [X1, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDUR D6, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D17, D0, D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D17, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D18, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D19, D0, D18, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D19, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D20, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D21, D20, D0, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D21, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a67c <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41a67c <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:71-78
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=22
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

29% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
42% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 30 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

30: addition or subtraction (all inside FMA instructions)
30: multiply (all inside FMA instructions)

The binary loop is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 20.00 FP operations per loaded or stored byte.

General properties

nb instructions	157
nb uops	157
loop length	628
used w registers	10
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	23
used q registers	18
used v registers	19
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.63 cycles
front end	19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	17.50	17.50	17.50	17.50	9.75	9.75	9.75	9.75	17.67	17.67	17.67	0.00	0.00
cycles	6.50	6.50	17.50	17.50	17.50	17.50	9.75	9.75	9.75	9.75	17.67	17.67	17.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.63
Dispatch	17.67
Overall L1	19.63

Vectorization ratios

INT

all	26%
load	50%
store	33%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	42%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	42%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	29%
load	50%
store	33%
mul	0%
add-sub	0%
fma	42%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	35%
load	46%
store	41%
mul	25%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	35%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	35%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	35%
load	46%
store	41%
mul	25%
add-sub	22%
fma	35%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.63 cycles. At this rate:

0% of peak load performance is reached (0.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 41a470

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
UBFM W20, W9, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W6, [X12, X9,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 41a67c <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X13, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X5, X8, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X21, X19, [X4, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
ADD X7, X21, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X19, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X15, X17, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP W6, #1, #4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.EQ 41a69c <advanceVelocity._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W18, W6, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X11, X15, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB W0, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X3, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UMADDL X4, W0, W14, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
MOVK X3, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X3, #2730	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X4, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X7, X5, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X17, X7, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X18, X17, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X0, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X3, X0, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a58c <advanceVelocity._omp_fn.0+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a558 <advanceVelocity._omp_fn.0+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a52c <advanceVelocity._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q1, Q6, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR X1, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X16, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q4, Q2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR Q5, [X16, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q7, [X15, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V4.2D, V3.2D, V1.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V2.2D, V3.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V7.2D, V3.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q4, Q2, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q7, [X15, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDP Q18, Q19, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X2, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q16, Q17, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDUR Q20, [X2, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q21, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V16.2D, V3.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V17.2D, V3.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V21.2D, V3.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q16, Q17, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q21, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDP Q24, Q25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X2, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q22, Q23, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDUR Q26, [X2, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q27, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMLA V22.2D, V3.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V23.2D, V3.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
FMLA V27.2D, V3.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (50.0%)
STP Q22, Q23, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q27, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a634 <advanceVelocity._omp_fn.0+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W11, W6, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W20, W11, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W6, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 41a67c <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SMULL X6, W20, W10	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR D30, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X4, X21, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X19, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D31, [X21, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D2, D0, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D2, [X21, X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D7, D1, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR D4, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D16, D0, D4, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D16, [X4, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D6, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D5, D0, D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D5, [X4, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W30, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GT 41a470 <advanceVelocity._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X21, X21, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X5, X9,LSL #6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MOVZ X17, #43691	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X17, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X7, X7,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X17, #43690	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK X17, #2730	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X21, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X3, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X2, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X20, X11, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X6, X20, X17	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADD X19, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X4, X19, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a798 <advanceVelocity._omp_fn.0+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a75c <advanceVelocity._omp_fn.0+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a728 <advanceVelocity._omp_fn.0+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D17, D18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X0, X15, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X16, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D19, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D21, D0, D20, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D21, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D22, [X16, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D23, D0, D22, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D23, [X15, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR D24, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D25, D24, D0, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D25, [X15, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D26, D27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D29, [X1, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDUR D28, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D30, D0, D29, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D30, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D31, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D2, D0, D31, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D2, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D7, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D1, D7, D0, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D1, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDP D4, D16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D5, [X1, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDUR D6, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D17, D0, D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D17, [X0, #488]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D18, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D19, D0, D18, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D19, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDUR D20, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D21, D20, D0, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STUR D21, [X0, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 41a67c <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 41a67c <advanceVelocity._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code