OV - exec - Loop 107

	Loop Id: 107	Module: exec	Source: timestep.c:110-116	Coverage: 0.01%

0x41a8ec LDR	W5, [X13, X8,LSL #2]

0x41a8f0 CMP	W5, #0

0x41a8f4 B.LE	41aa98

0x41a8f8 LDP	X15, X7, [X19, #32]

0x41a8fc SUB	W6, W5, #1

0x41a900 UBFM	X9, X8, #56, #55

0x41a904 ADD	X14, X6, X8,LSL #6

0x41a908 LDR	X16, [X15, #16]

0x41a90c LDR	X17, [X15, #32]

0x41a910 ADD	X18, X16, #4

0x41a914 ADD	X2, X16, X9

0x41a918 ADD	X30, X18, X14,LSL #2

0x41a91c ADD	X1, X17, X11

0x41a920 SUB	X21, X30, X2

0x41a924 SUB	X0, X21, #4

0x41a928 UBFM	X12, X0, #2, #63

0x41a92c ADD	X3, X12, #1

0x41a930 ANDS	X4, X3, #0x3

0x41a934 B.EQ	41a9d8

0x41a938 CMP	X4, #1

0x41a93c B.EQ	41a9a4

0x41a940 CMP	X4, #2

0x41a944 B.EQ	41a978

0x41a948 LDRSW	X5, [X16, X9]

0x41a94c ADD	X2, X2, #4

0x41a950 LDP	D2, D3, [X1]

0x41a954 ADD	X1, X1, #24

0x41a958 LDUR	D0, [X1, #504]

0x41a95c ADD	X6, X7, X5,LSL #4

0x41a960 LDR	D4, [X6, #8]

0x41a964 FMUL	D5, D3, D3

0x41a968 FMADD	D6, D2, D2, D5

0x41a96c FDIV	D7, D17, D4

0x41a970 FMADD	D16, D0, D0, D6

0x41a974 FMADD	D1, D7, D16, D1

0x41a978 LDRSW	X9, [X2], #4

0x41a97c LDP	D19, D20, [X1]

0x41a980 ADD	X1, X1, #24

0x41a984 LDUR	D21, [X1, #504]

0x41a988 ADD	X14, X7, X9,LSL #4

0x41a98c LDR	D18, [X14, #8]

0x41a990 FMUL	D22, D20, D20

0x41a994 FMADD	D23, D19, D19, D22

0x41a998 FDIV	D24, D17, D18

0x41a99c FMADD	D25, D21, D21, D23

0x41a9a0 FMADD	D1, D24, D25, D1

0x41a9a4 LDRSW	X15, [X2], #4

0x41a9a8 LDP	D27, D28, [X1]

0x41a9ac ADD	X1, X1, #24

0x41a9b0 LDUR	D29, [X1, #504]

0x41a9b4 ADD	X16, X7, X15,LSL #4

0x41a9b8 LDR	D26, [X16, #8]

0x41a9bc FMUL	D30, D28, D28

0x41a9c0 FMADD	D31, D27, D27, D30

0x41a9c4 FDIV	D4, D17, D26

0x41a9c8 FMADD	D2, D29, D29, D31

0x41a9cc FMADD	D1, D4, D2, D1

0x41a9d0 CMP	X30, X2

0x41a9d4 B.EQ	41aa98

  (108) 0x41a9d8 LDP	D0, D3, [X1]

  (108) 0x41a9dc ORR	X17, XZR, X2

  (108) 0x41a9e0 ADD	X18, X1, #72

  (108) 0x41a9e4 ADD	X2, X2, #16

  (108) 0x41a9e8 LDRSW	X21, [X17], #4

  (108) 0x41a9ec LDR	D5, [X1, #16]

  (108) 0x41a9f0 FMUL	D6, D3, D3

  (108) 0x41a9f4 LDURSW	X12, [X2, #500]

  (108) 0x41a9f8 ADD	X0, X7, X21,LSL #4

  (108) 0x41a9fc LDRSW	X4, [X17, #4]

  (108) 0x41aa00 LDP	D18, D16, [X1, #24]

  (108) 0x41aa04 ADD	X1, X1, #96

  (108) 0x41aa08 FMADD	D7, D0, D0, D6

  (108) 0x41aa0c ADD	X3, X7, X12,LSL #4

  (108) 0x41aa10 LDURSW	X6, [X2, #508]

  (108) 0x41aa14 ADD	X5, X7, X4,LSL #4

  (108) 0x41aa18 LDR	D31, [X3, #8]

  (108) 0x41aa1c FMADD	D21, D5, D5, D7

  (108) 0x41aa20 LDR	D5, [X0, #8]

  (108) 0x41aa24 FMUL	D22, D16, D16

  (108) 0x41aa28 ADD	X9, X7, X6,LSL #4

  (108) 0x41aa2c LDR	D0, [X5, #8]

  (108) 0x41aa30 FDIV	D4, D17, D31

  (108) 0x41aa34 LDUR	D20, [X1, #472]

  (108) 0x41aa38 FMADD	D24, D18, D18, D22

  (108) 0x41aa3c LDUR	D19, [X1, #456]

  (108) 0x41aa40 LDR	D2, [X9, #8]

  (108) 0x41aa44 FDIV	D7, D17, D5

  (108) 0x41aa48 LDUR	D26, [X1, #464]

  (108) 0x41aa4c FMUL	D23, D20, D20

  (108) 0x41aa50 LDUR	D28, [X1, #496]

  (108) 0x41aa54 FMADD	D25, D19, D19, D24

  (108) 0x41aa58 LDUR	D27, [X1, #480]

  (108) 0x41aa5c FDIV	D3, D17, D0

  (108) 0x41aa60 LDUR	D19, [X1, #488]

  (108) 0x41aa64 FMADD	D29, D26, D26, D23

  (108) 0x41aa68 LDR	D22, [X18, #16]

  (108) 0x41aa6c FMADD	D30, D27, D27, D29

  (108) 0x41aa70 FDIV	D6, D17, D2

  (108) 0x41aa74 FMADD	D1, D7, D21, D1

  (108) 0x41aa78 FMUL	D21, D28, D28

  (108) 0x41aa7c FMADD	D18, D4, D25, D1

  (108) 0x41aa80 FMADD	D20, D19, D19, D21

  (108) 0x41aa84 FMADD	D16, D3, D30, D18

  (108) 0x41aa88 FMADD	D23, D22, D22, D20

  (108) 0x41aa8c FMADD	D1, D6, D23, D16

  (108) 0x41aa90 CMP	X30, X2

  (108) 0x41aa94 B.NE	41a9d8

0x41aa98 ADD	X8, X8, #1

0x41aa9c ADD	X11, X11, #1536

0x41aaa0 CMP	W10, W8

0x41aaa4 B.GT	41a8ec

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 116

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.63 - 3.50
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	3.00 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13 - 1.33
Bottlenecks	P6, P8,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.88 - 10.49
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	4.33 - 5.24
CQA cycles if fully vectorized	2.63 - 5.24
Front-end cycles	7.88
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	7.00
P6 cycles	3.75
P7 cycles	3.75
P8 cycles	3.75
P9 cycles	3.75
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	5.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	63.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.05 - 2.29
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.14 - 1.52
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	7.69
Vectorization ratio load	25.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.96
Vector-efficiency ratio load	29.17
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	22.92

Metric	Value
CQA speedup if no scalar integer	2.63 - 3.50
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	3.00 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13 - 1.33
Bottlenecks	P6, P8,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.88 - 10.49
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	4.33 - 5.24
CQA cycles if fully vectorized	2.63 - 5.24
Front-end cycles	7.88
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	7.00
P6 cycles	3.75
P7 cycles	3.75
P8 cycles	3.75
P9 cycles	3.75
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	5.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	63.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.05 - 2.29
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.14 - 1.52
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	7.69
Vectorization ratio load	25.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.96
Vector-efficiency ratio load	29.17
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	22.92

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.49 to 3.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 10.49 to 5.24 cycles (2.00x speedup).

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.49 to 7.50 cycles (1.40x speedup).

FMA

Detected 9 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
12: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 12 bytes.

Arithmetic intensity

Arithmetic intensity is 2.00 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	63
loop length	252
used w registers	4
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	24
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.00	7.00	7.00	7.00	3.75	3.75	3.75	3.75	5.33	5.33	5.33	0.00	0.00
cycles	3.00	3.00	7.00	7.00	7.00	7.00	3.75	3.75	3.75	3.75	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	7.88
Dispatch	7.00
DIV/SQRT	5.25-10.49
Overall L1	7.88-10.49

Vectorization ratios

INT

all	12%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	26%
load	29%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	25%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	29%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.49 cycles. At this rate:

1% of peak load performance is reached (1.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41a8ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR W5, [X13, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
CMP W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 41aa98 <kineticEnergy._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X7, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
SUB W6, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X9, X8, #56, #55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X6, X8,LSL #6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X16, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X17, [X15, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X18, X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X18, X14,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X17, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X21, X30, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X0, X21, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X12, X0, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X4, X3, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a9d8 <kineticEnergy._omp_fn.0+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a9a4 <kineticEnergy._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a978 <kineticEnergy._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X5, [X16, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
ADD X2, X2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP D2, D3, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D0, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X6, X7, X5,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D5, D3, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D6, D2, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D7, D17, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMADD D16, D0, D0, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D1, D7, D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDRSW X9, [X2], #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP D19, D20, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D21, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X14, X7, X9,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D22, D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D23, D19, D19, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D24, D17, D18	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMADD D25, D21, D21, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D1, D24, D25, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDRSW X15, [X2], #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP D27, D28, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D29, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X16, X7, X15,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X16, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D30, D28, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D31, D27, D27, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D4, D17, D26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMADD D2, D29, D29, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D1, D4, D2, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
CMP X30, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41aa98 <kineticEnergy._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 41a8ec <kineticEnergy._omp_fn.0+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.49 to 3.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.49 to 7.50 cycles (1.40x speedup).

FMA

Detected 9 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
12: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 12 bytes.

Arithmetic intensity

Arithmetic intensity is 2.00 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	63
loop length	252
used w registers	4
used x registers	21
used b registers	0
used h registers	0
used s registers	0
used d registers	24
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.88 cycles
front end	7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.00	7.00	7.00	7.00	3.75	3.75	3.75	3.75	5.33	5.33	5.33	0.00	0.00
cycles	3.00	3.00	7.00	7.00	7.00	7.00	3.75	3.75	3.75	3.75	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	7.88
Dispatch	7.00
DIV/SQRT	5.25-10.49
Overall L1	7.88-10.49

Vectorization ratios

INT

all	12%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	26%
load	29%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	25%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	29%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	25%
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.49 cycles. At this rate:

1% of peak load performance is reached (1.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 41a8ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR W5, [X13, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
CMP W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 41aa98 <kineticEnergy._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X7, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
SUB W6, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X9, X8, #56, #55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X6, X8,LSL #6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
LDR X16, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X17, [X15, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X18, X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X30, X18, X14,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X17, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X21, X30, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X0, X21, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X12, X0, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X4, X3, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a9d8 <kineticEnergy._omp_fn.0+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a9a4 <kineticEnergy._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41a978 <kineticEnergy._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X5, [X16, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (12.5%)
ADD X2, X2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP D2, D3, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D0, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X6, X7, X5,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D5, D3, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D6, D2, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D7, D17, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMADD D16, D0, D0, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D1, D7, D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDRSW X9, [X2], #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP D19, D20, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D21, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X14, X7, X9,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D22, D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D23, D19, D19, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D24, D17, D18	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMADD D25, D21, D21, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D1, D24, D25, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
LDRSW X15, [X2], #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP D27, D28, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X1, X1, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDUR D29, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X16, X7, X15,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D26, [X16, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D30, D28, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
FMADD D31, D27, D27, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FDIV D4, D17, D26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMADD D2, D29, D29, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
FMADD D1, D4, D2, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
CMP X30, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 41aa98 <kineticEnergy._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W10, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 41a8ec <kineticEnergy._omp_fn.0+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code