OV - exec - Loop 62

	Loop Id: 62	Module: exec	Source: haloExchange.c:623-630	Coverage: 1.34%

0x414ff0 LDR	Q1, [X25, X6]    [11]

0x414ff4 ADD	X17, X2, #48

0x414ff8 ADD	X15, X2, #104

0x414ffc ADD	X14, X2, #160

0x415000 ADD	X13, X2, #52

0x415004 LDR	Q0, [X0, X6]    [12]

0x415008 ADD	X7, X2, #108

0x41500c ADD	X26, X2, #164

0x415010 ADD	X24, X2, #56

0x415014 ADD	X30, X2, #72

0x415018 LDP	Q5, Q3, [X4]    [20]

0x41501c ADD	X18, X2, #168

0x415020 ADD	X6, X6, #16

0x415024 LDP	Q2, Q4, [X4, #32]    [20]

0x415028 STUR	S1, [X2, #504]    [17]

0x41502c ST1	{V1.S[1]}, [X17]    [15]

0x415030 ST1	{V1.S[2]}, [X15]    [10]

0x415034 ST1	{V1.S[3]}, [X14]    [8]

0x415038 LDP	Q6, Q7, [X4, #64]    [20]

0x41503c ADD	X17, X2, #184

0x415040 ADD	X15, X2, #80

0x415044 STUR	S0, [X2, #508]    [17]

0x415048 ADD	X14, X2, #96

0x41504c ADD	X4, X4, #96

0x415050 ST1	{V0.S[1]}, [X13]    [6]

0x415054 ST1	{V0.S[2]}, [X7]    [2]

0x415058 ST1	{V0.S[3]}, [X26]    [13]

0x41505c STR	Q5, [X2]    [17]

0x415060 ADD	X13, X2, #192

0x415064 ADD	X7, X2, #208

0x415068 STR	D3, [X2, #16]    [17]

0x41506c ADD	X2, X2, #224

0x415070 ST1	{V3.D[1]}, [X24]    [9]

0x415074 STUR	D2, [X2, #352]    [16]

0x415078 ST1	{V2.D[1]}, [X30]    [4]

0x41507c STUR	Q4, [X2, #400]    [16]

0x415080 STUR	D6, [X2, #416]    [16]

0x415084 ST1	{V6.D[1]}, [X18]    [18]

0x415088 STUR	D7, [X2, #464]    [16]

0x41508c ST1	{V7.D[1]}, [X17]    [14]

0x415090 LDP	Q16, Q17, [X3]    [19]

0x415094 LDP	Q18, Q19, [X3, #32]    [19]

0x415098 LDP	Q20, Q21, [X3, #64]    [19]

0x41509c ADD	X3, X3, #96

0x4150a0 STUR	Q16, [X2, #312]    [16]

0x4150a4 STUR	D17, [X2, #328]    [16]

0x4150a8 ST1	{V17.D[1]}, [X15]    [3]

0x4150ac STUR	D18, [X2, #376]    [16]

0x4150b0 ST1	{V18.D[1]}, [X14]    [7]

0x4150b4 STUR	Q19, [X2, #424]    [16]

0x4150b8 STUR	D20, [X2, #440]    [16]

0x4150bc ST1	{V20.D[1]}, [X13]    [5]

0x4150c0 STUR	D21, [X2, #488]    [16]

0x4150c4 ST1	{V21.D[1]}, [X7]    [1]

0x4150c8 CMP	X27, X6

0x4150cc B.NE	414ff0

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 623 - 630

--------------------------------------------------------------------------------

623:       tmp[iTmp].gid  = atoms->gid[ii];

624:       tmp[iTmp].type = atoms->iSpecies[ii];

625:       tmp[iTmp].rx =   atoms->r[ii][0];

626:       tmp[iTmp].ry =   atoms->r[ii][1];

627:       tmp[iTmp].rz =   atoms->r[ii][2];

628:       tmp[iTmp].px =   atoms->p[ii][0];

629:       tmp[iTmp].py =   atoms->p[ii][1];

630:       tmp[iTmp].pz =   atoms->p[ii][2];

Coverage (%)	Name	Source Location	Module
►12.90+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.90+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.53+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.48+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.48+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.38+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.96+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►10.59+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.90
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	P6, P7, P10, P11,
Function	sortAtomsInCell
Source	haloExchange.c:623-630
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	4.83
Front-end cycles	7.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	4.75
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	8.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	56.00
Nb loads	NA
Nb stores	28.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.43
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	230.00
Stride 0	0.00
Stride 1	0.00
Stride n	5.00
Stride unknown	14.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	100.00
Vectorization ratio store	14.29
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	38.89
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.90
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	P6, P7, P10, P11,
Function	sortAtomsInCell
Source	haloExchange.c:623-630
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	4.83
Front-end cycles	7.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	4.75
P6 cycles	14.00
P7 cycles	14.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	8.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	56.00
Nb loads	NA
Nb stores	28.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.43
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	230.00
Stride 0	0.00
Stride 1	0.00
Stride n	5.00
Stride unknown	14.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	100.00
Vectorization ratio store	14.29
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	38.89
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:623-630
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:623-630.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 38% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 14.00 to 4.83 cycles (2.90x speedup).

Details

33% of VPU instructions are used in vector version (process two or more data elements in vector registers):

14% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)
Constant non-unit stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 230 bytes.

General properties

nb instructions	56
nb uops	56
loop length	224
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	2
used d registers	8
used q registers	14
used v registers	10
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.75	4.75	4.75	4.75	14.00	14.00	0.00	0.00	14.00	14.00	8.00	0.00	0.00
cycles	0.50	0.50	4.75	4.75	4.75	4.75	14.00	14.00	0.00	0.00	14.00	14.00	8.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	14.00
Data deps.	1.00
Overall L1	14.00

Vectorization ratios

all	33%
load	100%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	38%
load	87%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

34% of peak store performance is reached (16.43 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 414ff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR Q1, [X25, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X17, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X15, X2, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X14, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X13, X2, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q0, [X0, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X7, X2, #108	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X26, X2, #164	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X24, X2, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X30, X2, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP Q5, Q3, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X18, X2, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X6, X6, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP Q2, Q4, [X4, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
STUR S1, [X2, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ST1 {V1.S[1]}, [X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
ST1 {V1.S[2]}, [X15]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
ST1 {V1.S[3]}, [X14]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
LDP Q6, Q7, [X4, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X17, X2, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X15, X2, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STUR S0, [X2, #508]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ADD X14, X2, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V0.S[1]}, [X13]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
ST1 {V0.S[2]}, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
ST1 {V0.S[3]}, [X26]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
STR Q5, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X13, X2, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X7, X2, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR D3, [X2, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X2, X2, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V3.D[1]}, [X24]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D2, [X2, #352]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V2.D[1]}, [X30]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR Q4, [X2, #400]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STUR D6, [X2, #416]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V6.D[1]}, [X18]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D7, [X2, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V7.D[1]}, [X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
LDP Q16, Q17, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q18, Q19, [X3, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q20, Q21, [X3, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X3, X3, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STUR Q16, [X2, #312]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STUR D17, [X2, #328]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V17.D[1]}, [X15]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D18, [X2, #376]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V18.D[1]}, [X14]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR Q19, [X2, #424]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STUR D20, [X2, #440]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V20.D[1]}, [X13]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D21, [X2, #488]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V21.D[1]}, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
CMP X27, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 414ff0 <sortAtomsInCell+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	sortAtomsInCell
Source file and lines	haloExchange.c:623-630
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:623-630.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

33% of VPU instructions are used in vector version (process two or more data elements in vector registers):

14% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)
Constant non-unit stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 230 bytes.

General properties

nb instructions	56
nb uops	56
loop length	224
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	2
used d registers	8
used q registers	14
used v registers	10
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.75	4.75	4.75	4.75	14.00	14.00	0.00	0.00	14.00	14.00	8.00	0.00	0.00
cycles	0.50	0.50	4.75	4.75	4.75	4.75	14.00	14.00	0.00	0.00	14.00	14.00	8.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	14.00
Data deps.	1.00
Overall L1	14.00

Vectorization ratios

all	33%
load	100%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	38%
load	87%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

34% of peak store performance is reached (16.43 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 414ff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR Q1, [X25, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X17, X2, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X15, X2, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X14, X2, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X13, X2, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q0, [X0, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X7, X2, #108	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X26, X2, #164	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X24, X2, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X30, X2, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP Q5, Q3, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X18, X2, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X6, X6, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP Q2, Q4, [X4, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
STUR S1, [X2, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ST1 {V1.S[1]}, [X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
ST1 {V1.S[2]}, [X15]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
ST1 {V1.S[3]}, [X14]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
LDP Q6, Q7, [X4, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X17, X2, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X15, X2, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STUR S0, [X2, #508]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (12.5%)
ADD X14, X2, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V0.S[1]}, [X13]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
ST1 {V0.S[2]}, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
ST1 {V0.S[3]}, [X26]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (12.5%)
STR Q5, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X13, X2, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X7, X2, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR D3, [X2, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X2, X2, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ST1 {V3.D[1]}, [X24]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D2, [X2, #352]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V2.D[1]}, [X30]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR Q4, [X2, #400]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STUR D6, [X2, #416]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V6.D[1]}, [X18]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D7, [X2, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V7.D[1]}, [X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
LDP Q16, Q17, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q18, Q19, [X3, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q20, Q21, [X3, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X3, X3, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STUR Q16, [X2, #312]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STUR D17, [X2, #328]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V17.D[1]}, [X15]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D18, [X2, #376]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V18.D[1]}, [X14]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR Q19, [X2, #424]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STUR D20, [X2, #440]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V20.D[1]}, [X13]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
STUR D21, [X2, #488]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ST1 {V21.D[1]}, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	4	0.50	scal (25.0%)
CMP X27, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 414ff0 <sortAtomsInCell+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code