OV - exec - Loop 89

	Loop Id: 89	Module: exec	Source: ljForce.c:161-161 [...]	Coverage: 1.88%

0x417cc0 ORR	X13, XZR, X1

0x417cc4 STR	Q0, [X0, #32]    [3]

0x417cc8 ADD	X15, X0, #336

0x417ccc STP	Q0, Q0, [X0]    [3]

0x417cd0 STR	Q0, [X13], #16    [1]

0x417cd4 ADD	X1, X1, #128

0x417cd8 STP	Q0, Q0, [X0, #48]    [3]

0x417cdc STR	Q0, [X0, #80]    [3]

0x417ce0 STUR	Q0, [X1, #400]    [5]

0x417ce4 STP	Q0, Q0, [X0, #96]    [3]

0x417ce8 STR	Q0, [X0, #128]    [3]

0x417cec STR	Q0, [X13, #16]    [1]

0x417cf0 STP	Q0, Q0, [X0, #144]    [3]

0x417cf4 STR	Q0, [X0, #176]    [3]

0x417cf8 STUR	Q0, [X1, #432]    [5]

0x417cfc STP	Q0, Q0, [X0, #192]    [3]

0x417d00 STR	Q0, [X0, #224]    [3]

0x417d04 STUR	Q0, [X1, #448]    [5]

0x417d08 STP	Q0, Q0, [X0, #240]    [3]

0x417d0c STR	Q0, [X0, #272]    [3]

0x417d10 STUR	Q0, [X1, #464]    [5]

0x417d14 STP	Q0, Q0, [X0, #288]    [3]

0x417d18 STR	Q0, [X0, #320]    [3]

0x417d1c ADD	X0, X0, #384

0x417d20 STUR	Q0, [X1, #480]    [5]

0x417d24 STUR	Q0, [X0, #464]    [2]

0x417d28 STP	Q0, Q0, [X15, #16]    [4]

0x417d2c STUR	Q0, [X1, #496]    [5]

0x417d30 CMP	X3, X0

0x417d34 B.NE	417cc0

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 22 - 24

--------------------------------------------------------------------------------

22:    a[0] = 0.0;

23:    a[1] = 0.0;

24:    a[2] = 0.0;

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 161 - 161

--------------------------------------------------------------------------------

161:       s->atoms->U[ii] = 0.;

Coverage (%)	Name	Source Location	Module
►98.39+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.61+	GOMP_parallel		libgomp.so.1.0.0
○	ljForce	ljForce.c:157	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.20
Bottlenecks	P6, P7, P10, P11,
Function	ljForce._omp_fn.0
Source	mytype.h:22-24,ljForce.c:161-161
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	8.00
Front-end cycles	3.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	12.00
P7 cycles	12.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	24.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	3.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	66.67
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.20
Bottlenecks	P6, P7, P10, P11,
Function	ljForce._omp_fn.0
Source	mytype.h:22-24,ljForce.c:161-161
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	8.00
Front-end cycles	3.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.25
P6 cycles	12.00
P7 cycles	12.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	24.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	3.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	66.67
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.0
Source file and lines	ljForce.c:161-161
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 66% register length (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.00 to 8.00 cycles (1.50x speedup).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	30
nb uops	30
loop length	120
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	1
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	12.00	12.00	0.00	0.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	12.00	12.00	0.00	0.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.75
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 417cc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
ORR X13, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STR Q0, [X0, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X15, X0, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X13], #16	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X1, X1, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X0, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #80]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STUR Q0, [X1, #400]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X0, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #128]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STR Q0, [X13, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X0, #144]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #176]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STUR Q0, [X1, #432]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X0, #192]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #224]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STUR Q0, [X1, #448]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X0, #240]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #272]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STUR Q0, [X1, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X0, #288]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #320]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X0, X0, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STUR Q0, [X1, #480]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STUR Q0, [X0, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X15, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q0, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
B.NE 417cc0 <ljForce._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ljForce._omp_fn.0
Source file and lines	ljForce.c:161-161
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	30
nb uops	30
loop length	120
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	1
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	12.00	12.00	0.00	0.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	12.00	12.00	0.00	0.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.75
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 417cc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
ORR X13, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STR Q0, [X0, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X15, X0, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X13], #16	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X1, X1, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X0, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #80]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STUR Q0, [X1, #400]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X0, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #128]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STR Q0, [X13, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X0, #144]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #176]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STUR Q0, [X1, #432]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X0, #192]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #224]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STUR Q0, [X1, #448]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X0, #240]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #272]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STUR Q0, [X1, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X0, #288]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X0, #320]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X0, X0, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STUR Q0, [X1, #480]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STUR Q0, [X0, #464]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
STP Q0, Q0, [X15, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q0, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
B.NE 417cc0 <ljForce._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code