OV - exec - Function initAtoms

	Function: initAtoms	Module: exec	Source: initAtoms.c:24-50 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 22 - 24

--------------------------------------------------------------------------------

22:    a[0] = 0.0;

23:    a[1] = 0.0;

24:    a[2] = 0.0;

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h: 13 - 13

--------------------------------------------------------------------------------

13:    return malloc(iSize);

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 24 - 50

--------------------------------------------------------------------------------

24: {

25:    Atoms* atoms = comdMalloc(sizeof(Atoms));

26:

27:    int maxTotalAtoms = MAXATOMS*boxes->nTotalBoxes;

28:

29:    atoms->gid =      (int*)   comdMalloc(maxTotalAtoms*sizeof(int));

30:    atoms->iSpecies = (int*)   comdMalloc(maxTotalAtoms*sizeof(int));

31:    atoms->r =        (real3*) comdMalloc(maxTotalAtoms*sizeof(real3));

32:    atoms->p =        (real3*) comdMalloc(maxTotalAtoms*sizeof(real3));

33:    atoms->f =        (real3*) comdMalloc(maxTotalAtoms*sizeof(real3));

34:    atoms->U =        (real_t*)comdMalloc(maxTotalAtoms*sizeof(real_t));

35:

36:    atoms->nLocal = 0;

37:    atoms->nGlobal = 0;

38:

39:    for (int iOff = 0; iOff < maxTotalAtoms; iOff++)

40:    {

41:       atoms->gid[iOff] = 0;

42:       atoms->iSpecies[iOff] = 0;

43:       zeroReal3(atoms->r[iOff]);

44:       zeroReal3(atoms->p[iOff]);

45:       zeroReal3(atoms->f[iOff]);

46:       atoms->U[iOff] = 0.;

47:    }

48:

49:    return atoms;

50: }

0x415fc0 STP	X29, X30, [SP, #944]!

0x415fc4 ADD	X29, SP, #0

0x415fc8 STP	X19, X20, [SP, #16]

0x415fcc ORR	X19, XZR, X0

0x415fd0 MOVZ	X0, #56

0x415fd4 MOVZ	W20, #24

0x415fd8 STP	X21, X22, [SP, #32]

0x415fdc STP	X23, X24, [SP, #48]

0x415fe0 STR	X25, [SP, #64]

0x415fe4 BL	410230

0x415fe8 LDR	W23, [X19, #20]

0x415fec ORR	X22, XZR, X0

0x415ff0 UBFM	W23, W23, #26, #25

0x415ff4 SBFM	X24, X23, #62, #31

0x415ff8 SBFM	X21, X23, #0, #31

0x415ffc ORR	X0, XZR, X24

0x416000 SMULL	X20, W23, W20

0x416004 BL	410230

0x416008 ORR	X25, XZR, X0

0x41600c ORR	X0, XZR, X24

0x416010 STR	X25, [X22, #8]

0x416014 BL	410230

0x416018 ORR	X24, XZR, X0

0x41601c STR	X0, [X22, #16]

0x416020 ORR	X0, XZR, X20

0x416024 BL	410230

0x416028 ORR	X19, XZR, X0

0x41602c ORR	X0, XZR, X20

0x416030 STR	X19, [X22, #24]

0x416034 BL	410230

0x416038 ORR	X2, XZR, X0

0x41603c ORR	X0, XZR, X20

0x416040 ORR	X20, XZR, X2

0x416044 STR	X2, [X22, #32]

0x416048 BL	410230

0x41604c ORR	X3, XZR, X0

0x416050 UBFM	X0, X21, #61, #60

0x416054 ORR	X21, XZR, X3

0x416058 STR	X3, [X22, #40]

0x41605c BL	410230

0x416060 STR	XZR, [X22]

0x416064 STR	X0, [X22, #48]

0x416068 CMP	W23, #0

0x41606c B.LE	416128

0x416070 MOVI	V1.4S, #0

0x416074 MOVI	V0.2D, #0

0x416078 UBFM	W8, W23, #2, #31

0x41607c ORR	X7, XZR, X0

0x416080 ORR	X13, XZR, X21

0x416084 UBFM	X11, X8, #60, #59

0x416088 ORR	X12, XZR, X20

0x41608c ORR	X1, XZR, X19

0x416090 MOVZ	X9, #0

(74) 0x416094 ADD	X0, X9, #16

(74) 0x416098 ADD	X6, X1, #96

(74) 0x41609c STR	Q1, [X25, X9]

(74) 0x4160a0 ADD	X5, X12, #96

(74) 0x4160a4 STR	Q1, [X24, X9]

(74) 0x4160a8 ADD	X4, X13, #96

(74) 0x4160ac STP	Q0, Q0, [X1]

(74) 0x4160b0 STP	Q0, Q0, [X1, #32]

(74) 0x4160b4 STP	Q0, Q0, [X1, #64]

(74) 0x4160b8 STP	Q0, Q0, [X1, #96]

(74) 0x4160bc ADD	X10, X7, #32

(74) 0x4160c0 STR	Q1, [X25, X0]

(74) 0x4160c4 ADD	X9, X9, #32

(74) 0x4160c8 STP	Q0, Q0, [X12]

(74) 0x4160cc STP	Q0, Q0, [X13]

(74) 0x4160d0 STP	Q0, Q0, [X7]

(74) 0x4160d4 STR	Q1, [X24, X0]

(74) 0x4160d8 ADD	X1, X1, #192

(74) 0x4160dc ADD	X7, X7, #64

(74) 0x4160e0 STP	Q0, Q0, [X12, #32]

(74) 0x4160e4 STP	Q0, Q0, [X13, #32]

(74) 0x4160e8 STP	Q0, Q0, [X6, #32]

(74) 0x4160ec STP	Q0, Q0, [X12, #64]

(74) 0x4160f0 STP	Q0, Q0, [X13, #64]

(74) 0x4160f4 STP	Q0, Q0, [X6, #64]

(74) 0x4160f8 STP	Q0, Q0, [X12, #96]

(74) 0x4160fc STP	Q0, Q0, [X5, #32]

(74) 0x416100 STUR	Q0, [X7, #480]

(74) 0x416104 ADD	X12, X12, #192

(74) 0x416108 STP	Q0, Q0, [X13, #96]

(74) 0x41610c STR	Q0, [X10, #16]

(74) 0x416110 ADD	X13, X13, #192

(74) 0x416114 STP	Q0, Q0, [X4, #32]

(74) 0x416118 STP	Q0, Q0, [X5, #64]

(74) 0x41611c STP	Q0, Q0, [X4, #64]

(74) 0x416120 CMP	X9, X11

(74) 0x416124 B.NE	416094

0x416128 ORR	X0, XZR, X22

0x41612c LDP	X19, X20, [SP, #16]

0x416130 LDP	X21, X22, [SP, #32]

0x416134 LDP	X23, X24, [SP, #48]

0x416138 LDR	X25, [SP, #64]

0x41613c LDP	X29, X30, [SP], #80

0x416140 RET

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	initAtoms.c:24-50
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:24-50

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.75 to 0.63 cycles (15.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 9.75 to 5.62 cycles (1.73x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 7 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	60
nb uops	60
loop length	240
used w registers	3
used x registers	20
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	2
used z registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	9.75	9.75	9.75	9.75	0.50	0.50	0.50	0.50	6.00	6.00	6.00	6.00	6.00
cycles	4.50	4.50	9.75	9.75	9.75	9.75	0.50	0.50	0.50	0.50	6.00	6.00	6.00	6.00	6.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	9.75
Overall L1	9.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	37%
store	33%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.75 cycles. At this rate:

0% of peak load performance is reached (0.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 415fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W20, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W23, [X19, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM W23, W23, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X24, X23, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SBFM X21, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SMULL X20, W23, W20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X25, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X0, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X19, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X22, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X0, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X3, [X22, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 416128 <initAtoms+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V1.4S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
UBFM W8, W23, #2, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X7, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X13, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X11, X8, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X12, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	initAtoms.c:24-50
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:24-50

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.75 to 0.63 cycles (15.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 7 occurrences►
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
- /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	60
nb uops	60
loop length	240
used w registers	3
used x registers	20
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	2
used z registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	9.75	9.75	9.75	9.75	0.50	0.50	0.50	0.50	6.00	6.00	6.00	6.00	6.00
cycles	4.50	4.50	9.75	9.75	9.75	9.75	0.50	0.50	0.50	0.50	6.00	6.00	6.00	6.00	6.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	9.75
Overall L1	9.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	37%
store	33%
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.75 cycles. At this rate:

0% of peak load performance is reached (0.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 415fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W20, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W23, [X19, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM W23, W23, #26, #25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X24, X23, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SBFM X21, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SMULL X20, W23, W20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X25, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X0, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X19, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [X22, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X0, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X3, [X22, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410230 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 416128 <initAtoms+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V1.4S, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
UBFM W8, W23, #2, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X7, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X13, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X11, X8, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X12, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	1.06	0	1.12	0	2.52	0	1.09	0	1.24	0	1.96	0	0.78	0	1.61	0	0.88	0	1.7	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.079999998211861	0.012268559075892
1x2	1	1.06	2.12	2	0.074999995529652	0.011482581496239
1x4	1	1.12	4.47	4	0.070000000298023	0.01070396322757
1x8	1	2.52	20.17	8	0.029999999329448	0.004547500051558
1x16	1	1.09	17.52	16	0.064999997615814	0.00977898016572
1x24	1	1.24	29.87	24	0.054999999701977	0.0082005858421326
1x32	1	1.96	62.81	32	0.035000000149012	0.0051882304251194
1x40	1	0.78	31.14	40	0.08500000834465	0.012424087151885
1x48	1	1.61	77.19	48	0.03999999910593	0.0057946196757257
1x56	1	0.88	49.49	56	0.070000000298023	0.010103042237461
1x64	1	1.7	108.81	64	0.035000000149012	0.00501504028216

Name	Coverage (%)	Time (s)
▼initAtoms–	0.01	0.08
○Loop 74 - initAtoms.c:39-46 - exec	0.01	0.08

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency