OV - exec - Loop 74

	Loop Id: 74	Module: exec	Source: initAtoms.c:39-46 [...]	Coverage: 0.01%

0x416094 ADD	X0, X9, #16

0x416098 ADD	X6, X1, #96

0x41609c STR	Q1, [X25, X9]    [10]

0x4160a0 ADD	X5, X12, #96

0x4160a4 STR	Q1, [X24, X9]    [9]

0x4160a8 ADD	X4, X13, #96

0x4160ac STP	Q0, Q0, [X1]    [11]

0x4160b0 STP	Q0, Q0, [X1, #32]    [11]

0x4160b4 STP	Q0, Q0, [X1, #64]    [11]

0x4160b8 STP	Q0, Q0, [X1, #96]    [11]

0x4160bc ADD	X10, X7, #32

0x4160c0 STR	Q1, [X25, X0]    [10]

0x4160c4 ADD	X9, X9, #32

0x4160c8 STP	Q0, Q0, [X12]    [7]

0x4160cc STP	Q0, Q0, [X13]    [8]

0x4160d0 STP	Q0, Q0, [X7]    [5]

0x4160d4 STR	Q1, [X24, X0]    [9]

0x4160d8 ADD	X1, X1, #192

0x4160dc ADD	X7, X7, #64

0x4160e0 STP	Q0, Q0, [X12, #32]    [7]

0x4160e4 STP	Q0, Q0, [X13, #32]    [8]

0x4160e8 STP	Q0, Q0, [X6, #32]    [3]

0x4160ec STP	Q0, Q0, [X12, #64]    [7]

0x4160f0 STP	Q0, Q0, [X13, #64]    [8]

0x4160f4 STP	Q0, Q0, [X6, #64]    [3]

0x4160f8 STP	Q0, Q0, [X12, #96]    [7]

0x4160fc STP	Q0, Q0, [X5, #32]    [2]

0x416100 STUR	Q0, [X7, #480]    [4]

0x416104 ADD	X12, X12, #192

0x416108 STP	Q0, Q0, [X13, #96]    [8]

0x41610c STR	Q0, [X10, #16]    [6]

0x416110 ADD	X13, X13, #192

0x416114 STP	Q0, Q0, [X4, #32]    [1]

0x416118 STP	Q0, Q0, [X5, #64]    [2]

0x41611c STP	Q0, Q0, [X4, #64]    [1]

0x416120 CMP	X9, X11

0x416124 B.NE	416094

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 22 - 24

--------------------------------------------------------------------------------

22:    a[0] = 0.0;

23:    a[1] = 0.0;

24:    a[2] = 0.0;

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 39 - 46

--------------------------------------------------------------------------------

39:    for (int iOff = 0; iOff < maxTotalAtoms; iOff++)

40:    {

41:       atoms->gid[iOff] = 0;

42:       atoms->iSpecies[iOff] = 0;

43:       zeroReal3(atoms->r[iOff]);

44:       zeroReal3(atoms->p[iOff]);

45:       zeroReal3(atoms->f[iOff]);

46:       atoms->U[iOff] = 0.;

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

Coverage (%)	Name	Source Location	Module
►100.00+	main	CoMD.c:195	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.70
Bottlenecks	P6, P7, P10, P11,
Function	initAtoms
Source	mytype.h:22-24,initAtoms.c:39-46
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	12.50
CQA cycles if fully vectorized	11.00
Front-end cycles	4.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	12.50
P7 cycles	12.50
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.50
P11 cycles	12.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	25.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	7.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	88.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	88.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.70
Bottlenecks	P6, P7, P10, P11,
Function	initAtoms
Source	mytype.h:22-24,initAtoms.c:39-46
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	12.50
CQA cycles if fully vectorized	11.00
Front-end cycles	4.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	12.50
P7 cycles	12.50
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.50
P11 cycles	12.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	25.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	7.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	88.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	88.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	initAtoms
Source file and lines	initAtoms.c:39-46
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:39-46

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 88% register length (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.50 to 11.00 cycles (1.14x speedup).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Constant non-unit stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	37
nb uops	37
loop length	148
used w registers	0
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	2
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.75	2.75	2.75	2.75	12.50	12.50	0.00	0.00	12.50	12.50	0.00	0.00	0.00
cycles	0.50	0.50	2.75	2.75	2.75	2.75	12.50	12.50	0.00	0.00	12.50	12.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Dispatch	12.50
Data deps.	1.00
Overall L1	12.50

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	88%
load	NA (no load vectorizable/vectorized instructions)
store	88%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 416094

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
ADD X0, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X6, X1, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STR Q1, [X25, X9]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X5, X12, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STR Q1, [X24, X9]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X4, X13, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X1]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X1, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X1, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X1, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X10, X7, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STR Q1, [X25, X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X9, X9, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X12]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X13]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q1, [X24, X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X1, X1, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X7, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X12, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X13, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X6, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X12, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X13, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X6, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X12, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X5, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q0, [X7, #480]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X12, X12, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X13, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X10, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X13, X13, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X4, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X5, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X4, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
B.NE 416094 <initAtoms+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	initAtoms
Source file and lines	initAtoms.c:39-46
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:39-46

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Constant non-unit stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	37
nb uops	37
loop length	148
used w registers	0
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	2
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.75	2.75	2.75	2.75	12.50	12.50	0.00	0.00	12.50	12.50	0.00	0.00	0.00
cycles	0.50	0.50	2.75	2.75	2.75	2.75	12.50	12.50	0.00	0.00	12.50	12.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Dispatch	12.50
Data deps.	1.00
Overall L1	12.50

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	88%
load	NA (no load vectorizable/vectorized instructions)
store	88%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 416094

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
ADD X0, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X6, X1, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STR Q1, [X25, X9]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X5, X12, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STR Q1, [X24, X9]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X4, X13, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X1]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X1, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X1, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X1, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X10, X7, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STR Q1, [X25, X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X9, X9, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X12]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X13]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q1, [X24, X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X1, X1, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD X7, X7, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X12, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X13, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X6, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X12, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X13, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X6, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X12, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X5, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q0, [X7, #480]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X12, X12, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X13, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STR Q0, [X10, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (50.0%)
ADD X13, X13, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STP Q0, Q0, [X4, #32]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X5, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q0, Q0, [X4, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
B.NE 416094 <initAtoms+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -x 100 -y 100 -z 100MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-176-0594/intel/CoMD/run/oneview_runs/multicore/gcc/oneview_run_1781767694OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	1.06	0	1.12	0	2.52	0	1.09	0	1.24	0	1.96	0	0.78	0	1.61	0	0.88	0	1.7	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.079999998211861	0.012268559075892
1x2	1	1.06	2.12	2	0.074999995529652	0.011482581496239
1x4	1	1.12	4.47	4	0.070000000298023	0.01070396322757
1x8	1	2.52	20.17	8	0.029999999329448	0.004547500051558
1x16	1	1.09	17.52	16	0.064999997615814	0.00977898016572
1x24	1	1.24	29.87	24	0.054999999701977	0.0082005858421326
1x32	1	1.96	62.81	32	0.035000000149012	0.0051882304251194
1x40	1	0.78	31.14	40	0.08500000834465	0.012424087151885
1x48	1	1.61	77.19	48	0.03999999910593	0.0057946196757257
1x56	1	0.88	49.49	56	0.070000000298023	0.010103042237461
1x64	1	1.7	108.81	64	0.035000000149012	0.00501504028216

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency