OV - exec - Function Step10

	Function: Step10_orig	Module: exec	Source: Step10_orig.c:19-41	Coverage (incl. loops): 97.61% \| (excl. loops): 0.03%

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 41

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

36:     }

37:

38:     *dxi = xi;

39:     *dyi = yi;

40:     *dzi = zi;

41: }

0x410800 CMP	W0, #1

0x410804 B.LT	41084c

0x410808 STP	D15, D14, [SP, #944]!

0x41080c STP	D13, D12, [SP, #16]

0x410810 STP	D11, D10, [SP, #32]

0x410814 STP	D9, D8, [SP, #48]

0x410818 STR	X29, [SP, #64]

0x41081c ADDVL	SP, SP, #58

0x410820 CNTD	X9, ALL

0x410824 FMOV	S11, S1

0x410828 FMOV	S12, S0

0x41082c ORR	W8, WZR, W0

0x410830 CMP	X9, X8

0x410834 B.LS	410868

0x410838 ORR	X10, XZR, XZR

0x41083c MOVI	D5, #0

0x410840 MOVI	D6, #0

0x410844 MOVI	D7, #0

0x410848 B	410c7c

0x41084c MOVI	D7, #0

0x410850 MOVI	D6, #0

0x410854 MOVI	D5, #0

0x410858 STR	S7, [X5]

0x41085c STR	S6, [X6]

0x410860 STR	S5, [X7]

0x410864 RET

0x410868 CNTH	X11, ALL

0x41086c CMP	X11, X8

0x410870 B.LS	410888

0x410874 ORR	X10, XZR, XZR

0x410878 MOVI	D5, #0

0x41087c MOVI	D6, #0

0x410880 MOVI	D7, #0

0x410884 B	410b08

0x410888 MOVZ	W14, #63002

0x41088c MOVZ	W13, #35234

0x410890 MOVZ	W15, #58683

0x410894 MOVN	W10, #32768

0x410898 DUP	Z0.S, Z12.S[0]

0x41089c DUP	Z6.S, Z11.S[0]

0x4108a0 DUP	Z7.S, Z2.S[0]

0x4108a4 PTRUE	P1.B, ALL

0x4108a8 MOVK	W14, #14461

0x4108ac MOVK	W13, #13765

0x4108b0 MOVK	W15, #16009

0x4108b4 DUP	Z16.S, Z3.S[0]

0x4108b8 DUP	Z17.S, Z4.S[0]

0x4108bc ADD	W10, W11, W10

0x4108c0 PTRUE	P0.S, ALL

0x4108c4 PTRUE	P2.D, ALL

0x4108c8 FDUP	Z19.D, #112

0x4108cc MOVI	V26.2D, #0

0x4108d0 MOVI	V30.2D, #0

0x4108d4 MOVI	V27.2D, #0

0x4108d8 MOVI	V29.2D, #0

0x4108dc MOVI	V25.2D, #0

0x4108e0 MOVI	V28.2D, #0

0x4108e4 ORR	X12, XZR, XZR

0x4108e8 DUP	Z21.S, W14

0x4108ec MOVZ	W14, #18267

0x4108f0 MOVK	W14, #47759

0x4108f4 STR	Z12, [SP, MUL VL]

0x4108f8 STR	Z0, [SP, #5, MUL VL]

0x4108fc DUP	Z1.S, W13

0x410900 AND	X13, X10, X8

0x410904 SUB	X10, X8, X13

0x410908 STR	Z11, [SP, #1, MUL VL]

0x41090c STR	Z2, [SP, #2, MUL VL]

0x410910 STR	Z3, [SP, #3, MUL VL]

0x410914 DUP	Z22.S, W14

0x410918 MOVZ	W14, #6647

0x41091c MOVK	W14, #15420

0x410920 STR	Z4, [SP, #4, MUL VL]

0x410924 DUP	Z31.S, W15

0x410928 RDVL	X15, #2

0x41092c DUP	Z23.S, W14

0x410930 MOVZ	W14, #52448

0x410934 MOVK	W14, #48537

0x410938 DUP	Z24.S, W14

0x41093c SUB	X14, X8, X13

(5) 0x410940 LD1B	{Z8.B}, P1/Z, [X1, X12]

(5) 0x410944 LDR	Z0, [SP, #5, MUL VL]

(5) 0x410948 ADD	X16, X1, X12

(5) 0x41094c SUBS	X14, X14, X11

(5) 0x410950 FSUB	Z8.S, Z8.S, Z0.S

(5) 0x410954 LD1B	{Z9.B}, P1/Z, [X2, X12]

(5) 0x410958 LD1B	{Z10.B}, P1/Z, [X3, X12]

(5) 0x41095c FSUB	Z9.S, Z9.S, Z6.S

(5) 0x410960 FSUB	Z10.S, Z10.S, Z7.S

(5) 0x410964 LDR	Z18, [X16, #1, MUL VL]

(5) 0x410968 ADD	X16, X2, X12

(5) 0x41096c LDR	Z4, [X16, #1, MUL VL]

(5) 0x410970 ADD	X16, X3, X12

(5) 0x410974 LDR	Z14, [X16, #1, MUL VL]

(5) 0x410978 ADD	X16, X4, X12

(5) 0x41097c ADD	X12, X12, X15

(5) 0x410980 FSUB	Z18.S, Z18.S, Z0.S

(5) 0x410984 FMUL	Z11.S, Z8.S, Z8.S

(5) 0x410988 FSUB	Z4.S, Z4.S, Z6.S

(5) 0x41098c FMUL	Z15.S, Z18.S, Z18.S

(5) 0x410990 FSUB	Z14.S, Z14.S, Z7.S

(5) 0x410994 FMLA	Z11.S, P0/M, Z9.S, Z9.S

(5) 0x410998 FMLA	Z15.S, P0/M, Z4.S, Z4.S

(5) 0x41099c FMLA	Z15.S, P0/M, Z14.S, Z14.S

(5) 0x4109a0 MOVPRFX	Z12, Z11

(5) 0x4109a4 FMLA	Z12.S, P0/M, Z10.S, Z10.S

(5) 0x4109a8 FADD	Z3.S, Z15.S, Z17.S

(5) 0x4109ac FADD	Z13.S, Z12.S, Z17.S

(5) 0x4109b0 MOVPRFX	Z20, Z21

(5) 0x4109b4 FMLS	Z20.S, P0/M, Z12.S, Z1.S

(5) 0x4109b8 FCMGT	P3.S, P0/Z, Z16.S, Z12.S

(5) 0x4109bc UUNPKLO	Z2.D, Z3.S

(5) 0x4109c0 UUNPKHI	Z3.D, Z3.S

(5) 0x4109c4 UUNPKLO	Z11.D, Z13.S

(5) 0x4109c8 FMAD	Z20.S, P0/M, Z12.S, Z22.S

(5) 0x4109cc UUNPKHI	Z13.D, Z13.S

(5) 0x4109d0 FCVT	Z2.D, P2/M, Z2.S

(5) 0x4109d4 FCVT	Z3.D, P2/M, Z3.S

(5) 0x4109d8 FCVT	Z11.D, P2/M, Z11.S

(5) 0x4109dc FMAD	Z20.S, P0/M, Z12.S, Z23.S

(5) 0x4109e0 FCVT	Z13.D, P2/M, Z13.S

(5) 0x4109e4 FMAD	Z20.S, P0/M, Z12.S, Z24.S

(5) 0x4109e8 MOVPRFX	Z5, Z11

(5) 0x4109ec FSQRT	Z5.D, P2/M, Z11.D

(5) 0x4109f0 FMUL	Z11.D, Z11.D, Z11.D

(5) 0x4109f4 FMAD	Z20.S, P0/M, Z12.S, Z31.S

(5) 0x4109f8 FDIVR	Z11.D, P2/M, Z11.D, Z19.D

(5) 0x4109fc UUNPKLO	Z0.D, Z20.S

(5) 0x410a00 UUNPKHI	Z20.D, Z20.S

(5) 0x410a04 FCVT	Z0.D, P2/M, Z0.S

(5) 0x410a08 FCVT	Z20.D, P2/M, Z20.S

(5) 0x410a0c FNMLS	Z0.D, P2/M, Z11.D, Z5.D

(5) 0x410a10 MOVPRFX	Z5, Z13

(5) 0x410a14 FSQRT	Z5.D, P2/M, Z13.D

(5) 0x410a18 FMUL	Z13.D, Z13.D, Z13.D

(5) 0x410a1c MOVPRFX	Z11, Z2

(5) 0x410a20 FSQRT	Z11.D, P2/M, Z2.D

(5) 0x410a24 FMUL	Z2.D, Z2.D, Z2.D

(5) 0x410a28 FDIVR	Z13.D, P2/M, Z13.D, Z19.D

(5) 0x410a2c FDIVR	Z2.D, P2/M, Z2.D, Z19.D

(5) 0x410a30 FCVT	Z0.S, P2/M, Z0.D

(5) 0x410a34 FNMSB	Z5.D, P2/M, Z13.D, Z20.D

(5) 0x410a38 MOVPRFX	Z20, Z21

(5) 0x410a3c FMLS	Z20.S, P0/M, Z15.S, Z1.S

(5) 0x410a40 FMAD	Z20.S, P0/M, Z15.S, Z22.S

(5) 0x410a44 FMAD	Z20.S, P0/M, Z15.S, Z23.S

(5) 0x410a48 FCVT	Z5.S, P2/M, Z5.D

(5) 0x410a4c FMAD	Z20.S, P0/M, Z15.S, Z24.S

(5) 0x410a50 UZP1	Z0.S, Z0.S, Z5.S

(5) 0x410a54 LD1W	{Z5.S}, P3/Z, [X16, MUL VL]

(5) 0x410a58 FCMGT	P3.S, P0/Z, Z12.S, #0.0000000

(5) 0x410a5c FMAD	Z20.S, P0/M, Z15.S, Z31.S

(5) 0x410a60 UUNPKLO	Z13.D, Z20.S

(5) 0x410a64 UUNPKHI	Z20.D, Z20.S

(5) 0x410a68 FMUL	Z0.S, Z5.S, Z0.S

(5) 0x410a6c MOVI	V5.2D, #0

(5) 0x410a70 FCVT	Z13.D, P2/M, Z13.S

(5) 0x410a74 FCVT	Z20.D, P2/M, Z20.S

(5) 0x410a78 SEL	Z0.S, P3, Z0.S, Z5.S

(5) 0x410a7c FCMGT	P3.S, P0/Z, Z16.S, Z15.S

(5) 0x410a80 FNMSB	Z2.D, P2/M, Z11.D, Z13.D

(5) 0x410a84 MOVPRFX	Z11, Z3

(5) 0x410a88 FSQRT	Z11.D, P2/M, Z3.D

(5) 0x410a8c FMUL	Z3.D, Z3.D, Z3.D

(5) 0x410a90 FMLA	Z25.S, P0/M, Z0.S, Z8.S

(5) 0x410a94 FMLA	Z27.S, P0/M, Z0.S, Z9.S

(5) 0x410a98 FMLA	Z26.S, P0/M, Z0.S, Z10.S

(5) 0x410a9c FDIVR	Z3.D, P2/M, Z3.D, Z19.D

(5) 0x410aa0 FCVT	Z2.S, P2/M, Z2.D

(5) 0x410aa4 FNMSB	Z3.D, P2/M, Z11.D, Z20.D

(5) 0x410aa8 FCVT	Z3.S, P2/M, Z3.D

(5) 0x410aac UZP1	Z0.S, Z2.S, Z3.S

(5) 0x410ab0 LD1W	{Z2.S}, P3/Z, [X16, #1, MUL VL]

(5) 0x410ab4 FCMGT	P3.S, P0/Z, Z15.S, #0.0000000

(5) 0x410ab8 FMUL	Z0.S, Z2.S, Z0.S

(5) 0x410abc SEL	Z0.S, P3, Z0.S, Z5.S

(5) 0x410ac0 FMLA	Z28.S, P0/M, Z0.S, Z18.S

(5) 0x410ac4 FMLA	Z29.S, P0/M, Z0.S, Z4.S

(5) 0x410ac8 FMLA	Z30.S, P0/M, Z0.S, Z14.S

(5) 0x410acc B.NE	410940

0x410ad0 FADD	Z0.S, Z30.S, Z26.S

0x410ad4 FADDV	S5, P0, Z0.S

0x410ad8 FADD	Z0.S, Z29.S, Z27.S

0x410adc FADDV	S6, P0, Z0.S

0x410ae0 FADD	Z0.S, Z28.S, Z25.S

0x410ae4 FADDV	S7, P0, Z0.S

0x410ae8 CBZ	X13, 410c54

0x410aec LDR	Z4, [SP, #4, MUL VL]

0x410af0 LDR	Z3, [SP, #3, MUL VL]

0x410af4 CMP	X13, X9

0x410af8 LDR	Z2, [SP, #2, MUL VL]

0x410afc LDR	Z11, [SP, #1, MUL VL]

0x410b00 LDR	Z12, [SP, MUL VL]

0x410b04 B.CC	410c7c

0x410b08 INDEX	Z0.D, #0, #1

0x410b0c ORR	X11, XZR, XZR

0x410b10 DUP	Z1.D, X11

0x410b14 PTRUE	P0.D, ALL

0x410b18 MOVI	V18.2D, #0

0x410b1c MOVZ	W12, #35234

0x410b20 MOVI	V19.2D, #0

0x410b24 MOVK	W12, #13765

0x410b28 MOVI	V16.2D, #0

0x410b2c ORR	X11, XZR, X10

0x410b30 SUB	X10, XZR, X9

0x410b34 MOVI	V17.2D, #0

0x410b38 DUP	Z20.S, Z12.S[0]

0x410b3c DUP	Z21.S, Z11.S[0]

0x410b40 DUP	Z23.S, Z4.S[0]

0x410b44 FDUP	Z24.D, #112

0x410b48 AND	X10, X10, X8

0x410b4c CMPEQ	P1.D, P0/Z, Z0.D, Z1.D

0x410b50 CPY	Z18.S, P1/M, S5

0x410b54 DUP	Z5.S, W12

0x410b58 MOVZ	W12, #63002

0x410b5c CPY	Z19.S, P1/M, S6

0x410b60 CPY	Z16.S, P1/M, S7

0x410b64 DUP	Z6.S, Z2.S[0]

0x410b68 DUP	Z7.S, Z3.S[0]

0x410b6c MOVK	W12, #14461

0x410b70 DUP	Z22.S, W12

0x410b74 MOVZ	W12, #18267

0x410b78 MOVK	W12, #47759

0x410b7c DUP	Z25.S, W12

0x410b80 MOVZ	W12, #6647

0x410b84 MOVK	W12, #15420

0x410b88 DUP	Z26.S, W12

0x410b8c MOVZ	W12, #52448

0x410b90 MOVK	W12, #48537

0x410b94 DUP	Z27.S, W12

0x410b98 MOVZ	W12, #58683

0x410b9c MOVK	W12, #16009

0x410ba0 DUP	Z28.S, W12

(6) 0x410ba4 LD1W	{Z0.D}, P0/Z, [X1, X11,LSL #2]

(6) 0x410ba8 LD1W	{Z29.D}, P0/Z, [X3, X11,LSL #2]

(6) 0x410bac FSUB	Z0.S, P0/M, Z0.S, Z20.S

(6) 0x410bb0 LD1W	{Z1.D}, P0/Z, [X2, X11,LSL #2]

(6) 0x410bb4 MOVPRFX	Z10, Z29

(6) 0x410bb8 FSUB	Z10.S, P0/M, Z10.S, Z6.S

(6) 0x410bbc FSUB	Z1.S, P0/M, Z1.S, Z21.S

(6) 0x410bc0 MOVPRFX	Z29, Z0

(6) 0x410bc4 FMUL	Z29.S, P0/M, Z29.S, Z0.S

(6) 0x410bc8 FMLA	Z29.S, P0/M, Z1.S, Z1.S

(6) 0x410bcc MOVPRFX	Z9, Z29

(6) 0x410bd0 FMLA	Z9.S, P0/M, Z10.S, Z10.S

(6) 0x410bd4 MOVPRFX	Z29, Z9

(6) 0x410bd8 FADD	Z29.S, P0/M, Z29.S, Z23.S

(6) 0x410bdc MOVPRFX	Z31, Z22

(6) 0x410be0 FMLS	Z31.S, P0/M, Z9.S, Z5.S

(6) 0x410be4 FCMGT	P1.S, P0/Z, Z7.S, Z9.S

(6) 0x410be8 FCVT	Z29.D, P0/M, Z29.S

(6) 0x410bec FMAD	Z31.S, P0/M, Z9.S, Z25.S

(6) 0x410bf0 LD1W	{Z8.D}, P1/Z, [X4, X11,LSL #2]

(6) 0x410bf4 FCMGT	P1.S, P0/Z, Z9.S, #0.0000000

(6) 0x410bf8 ADD	X11, X11, X9

(6) 0x410bfc CMP	X10, X11

(6) 0x410c00 FMAD	Z31.S, P0/M, Z9.S, Z26.S

(6) 0x410c04 MOVPRFX	Z30, Z29

(6) 0x410c08 FSQRT	Z30.D, P0/M, Z29.D

(6) 0x410c0c FMUL	Z29.D, Z29.D, Z29.D

(6) 0x410c10 FMAD	Z31.S, P0/M, Z9.S, Z27.S

(6) 0x410c14 FDIVR	Z29.D, P0/M, Z29.D, Z24.D

(6) 0x410c18 FMAD	Z31.S, P0/M, Z9.S, Z28.S

(6) 0x410c1c FCVT	Z31.D, P0/M, Z31.S

(6) 0x410c20 FNMSB	Z29.D, P0/M, Z30.D, Z31.D

(6) 0x410c24 FCVT	Z29.S, P0/M, Z29.D

(6) 0x410c28 FMUL	Z29.S, P0/M, Z29.S, Z8.S

(6) 0x410c2c SEL	Z29.D, P1, Z29.D, Z17.D

(6) 0x410c30 FMLA	Z16.S, P0/M, Z29.S, Z0.S

(6) 0x410c34 FMLA	Z19.S, P0/M, Z29.S, Z1.S

(6) 0x410c38 FMLA	Z18.S, P0/M, Z29.S, Z10.S

(6) 0x410c3c B.NE	410ba4

0x410c40 FADDV	S5, P0, Z18.S

0x410c44 CMP	X10, X8

0x410c48 FADDV	S6, P0, Z19.S

0x410c4c FADDV	S7, P0, Z16.S

0x410c50 B.NE	410c7c

0x410c54 ADDVL	SP, SP, #6

0x410c58 LDP	D9, D8, [SP, #48]

0x410c5c LDP	D11, D10, [SP, #32]

0x410c60 LDP	D13, D12, [SP, #16]

0x410c64 LDR	X29, [SP, #64]

0x410c68 LDP	D15, D14, [SP], #80

0x410c6c STR	S7, [X5]

0x410c70 STR	S6, [X6]

0x410c74 STR	S5, [X7]

0x410c78 RET

0x410c7c ADD	X9, X4, X10,LSL #2

0x410c80 ADD	X11, X3, X10,LSL #2

0x410c84 ADD	X12, X2, X10,LSL #2

0x410c88 ADD	X13, X1, X10,LSL #2

0x410c8c FMOV	D21, #1.0000000

0x410c90 SUB	X8, X8, X10

0x410c94 MOVZ	W10, #35234

0x410c98 MOVK	W10, #13765

0x410c9c FMOV	S16, W10

0x410ca0 MOVZ	W10, #63002

0x410ca4 MOVK	W10, #47229

0x410ca8 FMOV	S17, W10

0x410cac MOVZ	W10, #18267

0x410cb0 MOVK	W10, #14991

0x410cb4 FMOV	S18, W10

0x410cb8 MOVZ	W10, #6647

0x410cbc MOVK	W10, #48188

0x410cc0 FMOV	S19, W10

0x410cc4 MOVZ	W10, #52448

0x410cc8 MOVK	W10, #15769

0x410ccc FMOV	S20, W10

0x410cd0 MOVZ	W10, #58683

0x410cd4 MOVK	W10, #48777

0x410cd8 FMOV	S22, W10

0x410cdc B	410cf8

  (4) 0x410ce0 FMADD	S7, S27, S23, S7

  (4) 0x410ce4 FMADD	S6, S27, S24, S6

  (4) 0x410ce8 FMADD	S5, S27, S25, S5

  (4) 0x410cec ADD	X9, X9, #4

  (4) 0x410cf0 SUBS	X8, X8, #1

  (4) 0x410cf4 B.EQ	410c54

  (4) 0x410cf8 LDR	S0, [X13], #4

  (4) 0x410cfc LDR	S1, [X11], #4

  (4) 0x410d00 MOVI	D27, #0

  (4) 0x410d04 MOVI	D26, #0

  (4) 0x410d08 FSUB	S23, S0, S12

  (4) 0x410d0c FSUB	S25, S1, S2

  (4) 0x410d10 LDR	S0, [X12], #4

  (4) 0x410d14 FSUB	S24, S0, S11

  (4) 0x410d18 FMUL	S0, S23, S23

  (4) 0x410d1c FMADD	S0, S24, S24, S0

  (4) 0x410d20 FMADD	S28, S25, S25, S0

  (4) 0x410d24 FCMP	S28, S3

  (4) 0x410d28 B.LT	410d40

  (4) 0x410d2c FCMP	S28, #0

  (4) 0x410d30 B.LE	410ce0

  (4) 0x410d34 B	410d4c

0x410d38 HINT	#0

0x410d3c HINT	#0

(3) 0x410d40 LDR	S26, [X9]

(3) 0x410d44 FCMP	S28, #0

(3) 0x410d48 B.LE	410ce0

  (4) 0x410d4c FADD	S0, S28, S4

  (4) 0x410d50 FMADD	S1, S28, S16, S17

  (4) 0x410d54 FCVT	D0, S0

  (4) 0x410d58 FMADD	S1, S1, S28, S18

  (4) 0x410d5c FSQRT	D27, D0

  (4) 0x410d60 FMUL	D0, D0, D0

  (4) 0x410d64 FMADD	S1, S1, S28, S19

  (4) 0x410d68 FDIV	D0, D21, D0

  (4) 0x410d6c FMADD	S1, S1, S28, S20

  (4) 0x410d70 FMADD	S1, S1, S28, S22

  (4) 0x410d74 FCVT	D1, S1

  (4) 0x410d78 FMADD	D0, D0, D27, D1

  (4) 0x410d7c FCVT	S0, D0

  (4) 0x410d80 FMUL	S27, S26, S0

  (4) 0x410d84 B	410ce0

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	main.c:155	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run orig_0

Source file and lines	Step10_orig.c:19-41
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-41.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.00 to 18.00 cycles (1.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 40% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.00 to 16.75 cycles (1.37x speedup).

Details

28% of VPU instructions are used in vector version (process two or more data elements in vector registers):

90% of VPU loads are used in vector version.
58% of VPU stores are used in vector version.
64% of VPU addition or subtraction instructions are used in vector version.
11% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 72 FP arithmetical operations:

72: addition or subtraction

The binary function is loading 160 bytes. The binary function is storing 210 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	175
nb uops	173
loop length	700
used w registers	9
used x registers	17
used b registers	0
used h registers	0
used s registers	14
used d registers	12
used q registers	0
used v registers	10
used z registers	26
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.63 cycles
front end	21.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	20.50	20.25	23.00	20.25	19.00	19.00	19.00	19.00	11.00	11.00	5.00	0.50	0.50
cycles	5.50	5.50	20.50	20.25	23.00	20.25	19.00	19.00	19.00	19.00	11.00	11.00	5.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.63
Dispatch	23.00
Overall L1	23.00

Vectorization ratios

INT

all	25%
load	90%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	45%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	28%
load	90%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	64%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	38%
load	72%
store	52%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	51%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

INT+FP

all	40%
load	72%
store	52%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	73%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.00 cycles. At this rate:

7% of peak load performance is reached (6.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 41084c <Step10_orig+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D15, D14, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADDVL SP, SP, #58	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV S11, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMOV S12, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 410868 <Step10_orig+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D5, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 410c7c <Step10_orig+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D5, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR S7, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S6, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S5, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTH X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 410888 <Step10_orig+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D5, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 410b08 <Step10_orig+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W14, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W13, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W15, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN W10, #32768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z0.S, Z12.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z6.S, Z11.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z7.S, Z2.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVK W14, #14461	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W13, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #16009	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z16.S, Z3.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z17.S, Z4.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD W10, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FDUP Z19.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V26.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V30.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V27.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V29.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V25.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V28.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z21.S, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W14, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W14, #47759	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR Z12, [SP, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z0, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.S, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
AND X13, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z11, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z2, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z3, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z22.S, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W14, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W14, #15420	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR Z4, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z31.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
RDVL X15, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
DUP Z23.S, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W14, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W14, #48537	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z24.S, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
SUB X14, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FADD Z0.S, Z30.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S5, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADD Z0.S, Z29.S, Z27.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S6, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADD Z0.S, Z28.S, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S7, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
CBZ X13, 410c54 <Step10_orig+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Z4, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z3, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
CMP X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR Z2, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z11, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z12, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
B.CC 410c7c <Step10_orig+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z0.D, #0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z1.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI V18.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ W12, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVI V19.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVK W12, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVI V16.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X11, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V17.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP Z20.S, Z12.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z21.S, Z11.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z23.S, Z4.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FDUP Z24.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
AND X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMPEQ P1.D, P0/Z, Z0.D, Z1.D	1	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
CPY Z18.S, P1/M, S5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
DUP Z5.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W12, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CPY Z19.S, P1/M, S6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
CPY Z16.S, P1/M, S7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
DUP Z6.S, Z2.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z7.S, Z3.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
MOVK W12, #14461	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z22.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W12, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W12, #47759	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z25.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W12, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W12, #15420	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z26.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W12, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W12, #48537	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z27.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W12, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W12, #16009	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z28.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
FADDV S5, P0, Z18.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FADDV S6, P0, Z19.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADDV S7, P0, Z16.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
B.NE 410c7c <Step10_orig+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP D15, D14, [SP], #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
STR S7, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S6, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S5, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X4, X10,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X3, X10,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X2, X10,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X1, X10,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D21, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X8, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S16, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W10, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #47229	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S17, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W10, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #14991	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S18, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W10, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #48188	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S19, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W10, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #15769	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S20, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W10, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #48777	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S22, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
B 410cf8 <Step10_orig+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run orig_0

Source file and lines	Step10_orig.c:19-41
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-41.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

28% of VPU instructions are used in vector version (process two or more data elements in vector registers):

90% of VPU loads are used in vector version.
58% of VPU stores are used in vector version.
64% of VPU addition or subtraction instructions are used in vector version.
11% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 72 FP arithmetical operations:

72: addition or subtraction

The binary function is loading 160 bytes. The binary function is storing 210 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	175
nb uops	173
loop length	700
used w registers	9
used x registers	17
used b registers	0
used h registers	0
used s registers	14
used d registers	12
used q registers	0
used v registers	10
used z registers	26
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.63 cycles
front end	21.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	20.50	20.25	23.00	20.25	19.00	19.00	19.00	19.00	11.00	11.00	5.00	0.50	0.50
cycles	5.50	5.50	20.50	20.25	23.00	20.25	19.00	19.00	19.00	19.00	11.00	11.00	5.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.63
Dispatch	23.00
Overall L1	23.00

Vectorization ratios

INT

all	25%
load	90%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	45%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	28%
load	90%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	64%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	38%
load	72%
store	52%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	51%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

INT+FP

all	40%
load	72%
store	52%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	73%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.00 cycles. At this rate:

7% of peak load performance is reached (6.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 41084c <Step10_orig+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D15, D14, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADDVL SP, SP, #58	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV S11, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMOV S12, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 410868 <Step10_orig+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D5, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 410c7c <Step10_orig+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D5, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR S7, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S6, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S5, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTH X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 410888 <Step10_orig+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D5, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 410b08 <Step10_orig+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W14, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W13, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W15, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN W10, #32768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z0.S, Z12.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z6.S, Z11.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z7.S, Z2.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVK W14, #14461	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W13, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #16009	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z16.S, Z3.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z17.S, Z4.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD W10, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FDUP Z19.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V26.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V30.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V27.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V29.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V25.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V28.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z21.S, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W14, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W14, #47759	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR Z12, [SP, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z0, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.S, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
AND X13, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z11, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z2, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z3, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z22.S, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W14, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W14, #15420	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR Z4, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z31.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
RDVL X15, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
DUP Z23.S, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W14, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W14, #48537	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z24.S, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
SUB X14, X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FADD Z0.S, Z30.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S5, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADD Z0.S, Z29.S, Z27.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S6, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADD Z0.S, Z28.S, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S7, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
CBZ X13, 410c54 <Step10_orig+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Z4, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z3, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
CMP X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR Z2, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z11, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z12, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
B.CC 410c7c <Step10_orig+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z0.D, #0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z1.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI V18.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ W12, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVI V19.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVK W12, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVI V16.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X11, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X10, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V17.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP Z20.S, Z12.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z21.S, Z11.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z23.S, Z4.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FDUP Z24.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
AND X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMPEQ P1.D, P0/Z, Z0.D, Z1.D	1	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	4	1	vect (100.0%)
CPY Z18.S, P1/M, S5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
DUP Z5.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W12, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CPY Z19.S, P1/M, S6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
CPY Z16.S, P1/M, S7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
DUP Z6.S, Z2.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z7.S, Z3.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
MOVK W12, #14461	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z22.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W12, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W12, #47759	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z25.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W12, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W12, #15420	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z26.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W12, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W12, #48537	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z27.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W12, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W12, #16009	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z28.S, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
FADDV S5, P0, Z18.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FADDV S6, P0, Z19.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADDV S7, P0, Z16.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
B.NE 410c7c <Step10_orig+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP D15, D14, [SP], #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
STR S7, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S6, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S5, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X4, X10,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X3, X10,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X2, X10,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X1, X10,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D21, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X8, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S16, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W10, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #47229	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S17, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W10, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #14991	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S18, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W10, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #48188	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S19, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W10, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #15769	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S20, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W10, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W10, #48777	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S22, W10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
B 410cf8 <Step10_orig+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼Step10_orig–	97.61	27.30
○Loop 5 - Step10_orig.c:19-35 - exec	97.56	27.17
○Loop 6 - Step10_orig.c:19-35 - exec	0.02	0.01
▼Loop 3 - Step10_orig.c:19-35 - exec–	0.00	0.00
○Loop 4 - Step10_orig.c:19-35 - exec	0.00	0.00

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Vectorization

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Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code