OV - exec - Function main

	Function: main	Module: exec	Source: main.c:50-194 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c: 50 - 194

--------------------------------------------------------------------------------

50: {

[...]

65:   rank = 0;

[...]

73:       printf( "count is set %d\n", count );

74:       printf( "Total MPI ranks %d\n", nprocs );

75:   }

76:

77:   if (argc == 2 && strncmp(argv[1], "-s", 2) == 0)

78:       NN = 15000;

79:

80:   if (argc == 2 && strncmp(argv[1], "-l", 2) == 0)

81:   	  count = 6000;

82:

83:   printf( "N is set %ld\n", NN );

84:

85: #pragma omp parallel

[...]

100:   for ( n = 400; n < NN; n = n + 20 )

101:   {

102:       /* Initial data preparation */

103:       fcoeff = 0.23f;

104:       fsrrmax2 = 0.5f;

105:       mp_rsm2 = 0.03f;

106:       dx1 = 1.0f/(float)n;

107:       dy1 = 2.0f/(float)n;

108:       dz1 = 3.0f/(float)n;

109:       xx[0] = 0.f;

110:       yy[0] = 0.f;

111:       zz[0] = 0.f;

112:       mass[0] = 2.f;

113:

114:       for ( i = 1; i < n; i++ )

115:       {

116:           xx[i] = xx[i-1] + dx1;

117:           yy[i] = yy[i-1] + dy1;

118:           zz[i] = zz[i-1] + dz1;

119:           mass[i] = (float)i * 0.01f + xx[i];

120:       }

121:

122:       for ( i = 0; i < n; i++ )

123:       {

124:           vx1[i] = 0.f;

125:           vy1[i] = 0.f;

126:           vz1[i] = 0.f;

[...]

139:       t1 = mysecond();

140: #endif

141:

142:     #pragma omp parallel for private( dx1, dy1, dz1 )

[...]

155:       t2 = mysecond();

[...]

169:       t3 = (t2 - t1) * 1e6;

170: #endif

171:

172:       elapsed = elapsed + t3;

[...]

186:   if ( rank == 0 )

187:   {

188:       printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 );

[...]

194:   return 0;

0x410260 STP	D13, D12, [SP, #880]!

0x410264 STP	D11, D10, [SP, #16]

0x410268 STP	D9, D8, [SP, #32]

0x41026c STP	X29, X30, [SP, #48]

0x410270 STP	X28, X27, [SP, #64]

0x410274 STP	X26, X25, [SP, #80]

0x410278 STP	X24, X23, [SP, #96]

0x41027c STP	X22, X21, [SP, #112]

0x410280 STP	X20, X19, [SP, #128]

0x410284 ADD	X29, SP, #48

0x410288 SUB	SP, SP, #32

0x41028c ADDVL	SP, SP, #60

0x410290 ORR	X20, XZR, X1

0x410294 ORR	W21, WZR, W0

0x410298 MOVZ	W19, #34464

0x41029c MOVZ	W8, #3000

0x4102a0 ADRP	X0,

0x4102a4 ADD	X0, X0, #24

0x4102a8 STP	WZR, W8, [SP, #8]

0x4102ac MOVZ	W1, #3000

0x4102b0 MOVK	W19, #1

0x4102b4 BL	4100c0

0x4102b8 ADRP	X0,

0x4102bc ADD	X0, X0, #41

0x4102c0 MOVZ	W1, #1

0x4102c4 BL	4100c0

0x4102c8 CMP	W21, #2

0x4102cc B.NE	410300

0x4102d0 LDR	X8, [X20, #8]

0x4102d4 LDRB	W9, [X8]

0x4102d8 CMP	W9, #45

0x4102dc B.NE	410300

0x4102e0 LDRB	W8, [X8, #1]

0x4102e4 MOVZ	W9, #15000

0x4102e8 CMP	W8, #115

0x4102ec CSEL	X19, X9, X19, #0

0x4102f0 CMP	W8, #108

0x4102f4 B.NE	410300

0x4102f8 MOVZ	W8, #6000

0x4102fc STR	W8, [SP, #12]

0x410300 ADRP	X0,

0x410304 ADD	X0, X0, #61

0x410308 ORR	X1, XZR, X19

0x41030c BL	4100c0

0x410310 ADRP	X0,

0x410314 ADD	X0, X0, #3432

0x410318 ADRP	X2, 410318

0x41031c ADD	X2, X2, #1472

0x410320 ADD	X3, SP, #8

0x410324 MOVZ	W1, #1

0x410328 BL	410080

0x41032c INDEX	Z0.S, #0, #1

0x410330 PTRUE	P1.S, ALL

0x410334 SUB	X9, X29, #48

0x410338 CNTW	X26, ALL

0x41033c MOVI	D9, #0

0x410340 FMOV	S11, #1.0000000

0x410344 FMOV	S12, #3.0000000

0x410348 MOVZ	W8, #400

0x41034c ADRP	X21,

0x410350 ADD	X21, X21, #96

0x410354 MOVZ	X22, #1

0x410358 ADRP	X27,

0x41035c ADD	X27, X27, #2784

0x410360 STR	W8, [SP, #16]

0x410364 MOVPRFX	Z1, Z0

0x410368 UCVTF	Z1.S, P1/M, Z0.S

0x41036c ADD	Z0.S, Z0.S, #1

0x410370 UCVTF	S10, X26

0x410374 DUP	Z20.S, W26

0x410378 ADRP	X28,

0x41037c ADD	X28, X28, #1376

0x410380 ADRP	X20,

0x410384 ADD	X20, X20, #4064

0x410388 ADRP	X23,

0x41038c ADD	X23, X23, #3504

0x410390 ADRP	X24, 410390

0x410394 ADD	X24, X24, #1536

0x410398 STR	Z0, [X9, #509, MUL VL]

0x41039c STR	Z1, [X9, #508, MUL VL]

0x4103a0 MOVZ	W9, #55050

0x4103a4 MOVK	W9, #15395

0x4103a8 DUP	Z21.S, W9

0x4103ac MOVZ	X9, #33920

0x4103b0 MOVK	X9, #16686

0x4103b4 FMOV	D13, X9

0x4103b8 SUB	X9, X29, #48

0x4103bc STR	Z20, [X9, #511, MUL VL]

0x4103c0 STR	Z21, [X9, #510, MUL VL]

0x4103c4 B	410464

(0) 0x4103c8 UBFM	X25, X8, #62, #31

(0) 0x4103cc ADRP	X0,

(0) 0x4103d0 ADD	X0, X0, #2656

(0) 0x4103d4 ORR	W1, WZR, WZR

(0) 0x4103d8 ORR	X2, XZR, X25

(0) 0x4103dc BL	4100e0

(0) 0x4103e0 ADRP	X0,

(0) 0x4103e4 ADD	X0, X0, #1248

(0) 0x4103e8 ORR	W1, WZR, WZR

(0) 0x4103ec ORR	X2, XZR, X25

(0) 0x4103f0 BL	4100e0

(0) 0x4103f4 ADRP	X0,

(0) 0x4103f8 ADD	X0, X0, #3936

(0) 0x4103fc ORR	W1, WZR, WZR

(0) 0x410400 ORR	X2, XZR, X25

(0) 0x410404 BL	4100e0

(0) 0x410408 BL	410780

(0) 0x41040c ADD	X3, SP, #12

(0) 0x410410 ADD	X4, SP, #16

(0) 0x410414 ADD	X5, SP, #28

(0) 0x410418 ADD	X6, SP, #24

(0) 0x41041c FMOV	D8, D0

(0) 0x410420 ORR	X0, XZR, X23

(0) 0x410424 ORR	X2, XZR, X24

(0) 0x410428 ADD	X7, SP, #20

(0) 0x41042c MOVZ	W1, #5

(0) 0x410430 BL	410080

(0) 0x410434 BL	410780

(0) 0x410438 SUB	X8, X29, #48

(0) 0x41043c FSUB	D0, D0, S8

(0) 0x410440 PTRUE	P1.S, ALL

(0) 0x410444 LDR	Z21, [X8, #510, MUL VL]

(0) 0x410448 LDR	Z20, [X8, #511, MUL VL]

(0) 0x41044c LDRSW	X8, [SP, #16]

(0) 0x410450 FMADD	D9, D0, D13, D9

(0) 0x410454 ADD	X8, X8, #20

(0) 0x410458 CMP	X19, X8

(0) 0x41045c STR	W8, [SP, #16]

(0) 0x410460 B.LE	41056c

(0) 0x410464 MOVZ	W9, #34079

(0) 0x410468 MOVZ	W10, #16128

(0) 0x41046c CMP	W8, #2

(0) 0x410470 MOVK	W9, #15979

(0) 0x410474 STR	W9, [SP, #20]

(0) 0x410478 MOVZ	W9, #49807

(0) 0x41047c MOVK	W9, #15605

(0) 0x410480 STP	W9, W10, [SP, #24]

(0) 0x410484 ADRP	X9,

(0) 0x410488 MOVZ	W10, #16384

(0) 0x41048c STR	WZR, [X9, #96]

(0) 0x410490 ADRP	X9,

(0) 0x410494 STR	WZR, [X9, #2784]

(0) 0x410498 ADRP	X9,

(0) 0x41049c STR	WZR, [X9, #1376]

(0) 0x4104a0 ADRP	X9,

(0) 0x4104a4 STR	W10, [X9, #4064]

(0) 0x4104a8 B.LT	410560

(0) 0x4104ac SCVTF	S0, W8

(0) 0x4104b0 SUB	X11, X29, #48

(0) 0x4104b4 ORR	W10, WZR, W8

(0) 0x4104b8 SUB	X10, X10, #1

(0) 0x4104bc ORR	X9, XZR, XZR

(0) 0x4104c0 LDR	Z7, [X11, #508, MUL VL]

(0) 0x4104c4 LDR	Z17, [X11, #509, MUL VL]

(0) 0x4104c8 FDIV	S16, S11, S0

(0) 0x4104cc WHILELO	P0.S, XZR, X10

(0) 0x4104d0 FMUL	S4, S16, S12

(0) 0x4104d4 FADD	S6, S16, S16

(0) 0x4104d8 DUP	Z0.S, Z16.S[0]

(0) 0x4104dc FMUL	S16, S16, S10

(0) 0x4104e0 DUP	Z1.S, Z6.S[0]

(0) 0x4104e4 FMUL	S6, S6, S10

(0) 0x4104e8 DUP	Z2.S, Z4.S[0]

(0) 0x4104ec FMUL	S4, S4, S10

(0) 0x4104f0 DUP	Z16.S, Z16.S[0]

(0) 0x4104f4 FMUL	Z5.S, Z1.S, Z7.S

(0) 0x4104f8 FMUL	Z3.S, Z2.S, Z7.S

(0) 0x4104fc FMUL	Z7.S, Z0.S, Z7.S

(0) 0x410500 DUP	Z6.S, Z6.S[0]

(0) 0x410504 DUP	Z4.S, Z4.S[0]

  (1) 0x410508 FADD	Z18.S, Z7.S, Z0.S

  (1) 0x41050c ADD	X11, X21, X9,LSL #2

  (1) 0x410510 FADD	Z19.S, Z5.S, Z1.S

  (1) 0x410514 ST1W	{Z18.S}, P0, [X11, X22,LSL #2]

  (1) 0x410518 ADD	X11, X27, X9,LSL #2

  (1) 0x41051c FADD	Z5.S, Z5.S, Z6.S

  (1) 0x410520 FADD	Z7.S, Z7.S, Z16.S

  (1) 0x410524 ST1W	{Z19.S}, P0, [X11, X22,LSL #2]

  (1) 0x410528 FADD	Z19.S, Z3.S, Z2.S

  (1) 0x41052c ADD	X11, X28, X9,LSL #2

  (1) 0x410530 FADD	Z3.S, Z3.S, Z4.S

  (1) 0x410534 ST1W	{Z19.S}, P0, [X11, X22,LSL #2]

  (1) 0x410538 MOVPRFX	Z19, Z17

  (1) 0x41053c UCVTF	Z19.S, P1/M, Z17.S

  (1) 0x410540 ADD	X11, X20, X9,LSL #2

  (1) 0x410544 ADD	X9, X9, X26

  (1) 0x410548 ADD	Z17.S, Z17.S, Z20.S

  (1) 0x41054c FMLA	Z18.S, P1/M, Z19.S, Z21.S

  (1) 0x410550 ST1W	{Z18.S}, P0, [X11, X22,LSL #2]

  (1) 0x410554 WHILELO	P0.S, X9, X10

  (1) 0x410558 B.MI	410508

(0) 0x41055c B	4103c8

(0) 0x410560 CMP	W8, #1

(0) 0x410564 B.EQ	4103c8

(0) 0x410568 B	410408

0x41056c LDR	W8, [SP, #8]

0x410570 CBNZ	W8, 41058c

0x410574 ADRP	X8,

0x410578 ADRP	X0,

0x41057c ADD	X0, X0, #102

0x410580 LDR	D0, [X8, #16]

0x410584 FMUL	D0, D9, D0

0x410588 BL	4100c0

0x41058c ORR	W0, WZR, WZR

0x410590 ADDVL	SP, SP, #4

0x410594 ADD	SP, SP, #32

0x410598 LDP	D9, D8, [SP, #32]

0x41059c LDP	D11, D10, [SP, #16]

0x4105a0 LDP	X20, X19, [SP, #128]

0x4105a4 LDP	X22, X21, [SP, #112]

0x4105a8 LDP	X24, X23, [SP, #96]

0x4105ac LDP	X26, X25, [SP, #80]

0x4105b0 LDP	X28, X27, [SP, #64]

0x4105b4 LDP	X29, X30, [SP, #48]

0x4105b8 LDP	D13, D12, [SP], #144

0x4105bc RET

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	main.c:50-194
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:50,65,73-85,100-126,139-142,155,169-172,186-188,194.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.00 to 5.00 cycles (3.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 17.00 to 9.75 cycles (1.74x speedup).

Details

15% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
43% of VPU stores are used in vector version.
4% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:83
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:85
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:188

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:100
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:100

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 5 bytes. The binary function is storing 134 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	111
nb uops	111
loop length	444
used w registers	8
used x registers	19
used b registers	0
used h registers	0
used s registers	4
used d registers	7
used q registers	0
used v registers	0
used z registers	4
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.88 cycles
front end	13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	17.00	17.00	17.00	17.00	4.00	4.00	4.00	4.00	10.00	10.00	10.00	4.50	4.50
cycles	5.50	5.50	17.00	17.00	17.00	17.00	4.00	4.00	4.00	4.00	10.00	10.00	10.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Dispatch	17.00
Overall L1	17.00

Vectorization ratios

INT

all	16%
load	33%
store	43%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	4%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	15%
load	33%
store	43%
mul	0%
add-sub	4%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	36%
load	47%
store	56%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	28%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	35%
load	47%
store	56%
mul	25%
add-sub	28%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.00 cycles. At this rate:

0% of peak load performance is reached (0.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.88 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D13, D12, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB SP, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #60	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W19, #34464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W8, #3000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4202a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP WZR, W8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W1, #3000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4202b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #41	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410300 <main+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRB W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W9, #45	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410300 <main+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRB W8, [X8, #1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W9, #15000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W8, #115	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X19, X9, X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W8, #108	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410300 <main+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #6000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADRP X0, <420300>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <43f310>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, 410318 <main+0xb8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X2, #1472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z0.S, #0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1	N/A
PTRUE P1.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X9, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTW X26, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVI D9, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S11, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMOV S12, #3.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W8, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X21, <44034c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X21, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X27, <4a1358>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X27, X27, #2784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVPRFX Z1, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
UCVTF Z1.S, P1/M, Z0.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	2	vect (100.0%)
ADD Z0.S, Z0.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
UCVTF S10, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.S, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADRP X28, <503378>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X28, X28, #1376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X20, <564380>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X20, #4064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X23, <43f388>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X23, #3504	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X24, 410390 <main+0x130>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X24, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR Z0, [X9, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z1, [X9, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVZ W9, #55050	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #15395	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z21.S, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ X9, #33920	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X9, #16686	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D13, X9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X9, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z20, [X9, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z21, [X9, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 410464 <main+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ W8, 41058c <main+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <420574>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <420578>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #102	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D0, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D0, D9, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W0, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADDVL SP, SP, #4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D13, D12, [SP], #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	main.c:50-194
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:50,65,73-85,100-126,139-142,155,169-172,186-188,194.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.00 to 5.00 cycles (3.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

15% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
43% of VPU stores are used in vector version.
4% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:73
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:74
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:83
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:85
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:188

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:100
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:100

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 5 bytes. The binary function is storing 134 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	111
nb uops	111
loop length	444
used w registers	8
used x registers	19
used b registers	0
used h registers	0
used s registers	4
used d registers	7
used q registers	0
used v registers	0
used z registers	4
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.88 cycles
front end	13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	17.00	17.00	17.00	17.00	4.00	4.00	4.00	4.00	10.00	10.00	10.00	4.50	4.50
cycles	5.50	5.50	17.00	17.00	17.00	17.00	4.00	4.00	4.00	4.00	10.00	10.00	10.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Dispatch	17.00
Overall L1	17.00

Vectorization ratios

INT

all	16%
load	33%
store	43%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	4%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	15%
load	33%
store	43%
mul	0%
add-sub	4%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	36%
load	47%
store	56%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	28%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	35%
load	47%
store	56%
mul	25%
add-sub	28%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.00 cycles. At this rate:

0% of peak load performance is reached (0.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.88 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D13, D12, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB SP, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #60	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W19, #34464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W8, #3000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4202a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP WZR, W8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W1, #3000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4202b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #41	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410300 <main+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRB W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W9, #45	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410300 <main+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRB W8, [X8, #1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W9, #15000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W8, #115	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X19, X9, X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W8, #108	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 410300 <main+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #6000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W8, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADRP X0, <420300>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <43f310>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X2, 410318 <main+0xb8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X2, #1472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410080 <@plt_start@+0x60>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z0.S, #0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1	N/A
PTRUE P1.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X9, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTW X26, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVI D9, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV S11, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMOV S12, #3.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W8, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X21, <44034c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X21, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X27, <4a1358>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X27, X27, #2784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR W8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVPRFX Z1, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
UCVTF Z1.S, P1/M, Z0.S	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	2	vect (100.0%)
ADD Z0.S, Z0.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
UCVTF S10, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.S, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADRP X28, <503378>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X28, X28, #1376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X20, <564380>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X20, #4064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X23, <43f388>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X23, #3504	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X24, 410390 <main+0x130>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X24, #1536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR Z0, [X9, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z1, [X9, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVZ W9, #55050	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #15395	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z21.S, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ X9, #33920	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X9, #16686	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D13, X9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X9, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z20, [X9, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z21, [X9, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 410464 <main+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ W8, 41058c <main+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <420574>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <420578>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #102	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D0, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D0, D9, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
BL 4100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W0, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADDVL SP, SP, #4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D13, D12, [SP], #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼main–	0.03	0.01
▼Loop 0 - main.c:100-172 - exec–	0.00	0.00
○Loop 1 - main.c:116-119 - exec	0.03	0.50

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ASM code

Code clean check

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CALL instructions

Details

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code