OV - exec - Loop 1

	Loop Id: 1	Module: exec	Source: main.c:116-119	Coverage: 0.03%

0x410508 FADD	Z18.S, Z7.S, Z0.S

0x41050c ADD	X11, X21, X9,LSL #2

0x410510 FADD	Z19.S, Z5.S, Z1.S

0x410514 ST1W	{Z18.S}, P0, [X11, X22,LSL #2]    [4]

0x410518 ADD	X11, X27, X9,LSL #2

0x41051c FADD	Z5.S, Z5.S, Z6.S

0x410520 FADD	Z7.S, Z7.S, Z16.S

0x410524 ST1W	{Z19.S}, P0, [X11, X22,LSL #2]    [3]

0x410528 FADD	Z19.S, Z3.S, Z2.S

0x41052c ADD	X11, X28, X9,LSL #2

0x410530 FADD	Z3.S, Z3.S, Z4.S

0x410534 ST1W	{Z19.S}, P0, [X11, X22,LSL #2]    [2]

0x410538 MOVPRFX	Z19, Z17

0x41053c UCVTF	Z19.S, P1/M, Z17.S

0x410540 ADD	X11, X20, X9,LSL #2

0x410544 ADD	X9, X9, X26

0x410548 ADD	Z17.S, Z17.S, Z20.S

0x41054c FMLA	Z18.S, P1/M, Z19.S, Z21.S

0x410550 ST1W	{Z18.S}, P0, [X11, X22,LSL #2]    [1]

0x410554 WHILELO	P0.S, X9, X10

0x410558 B.MI	410508

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c: 116 - 119

--------------------------------------------------------------------------------

116:           xx[i] = xx[i-1] + dx1;

117:           yy[i] = yy[i-1] + dy1;

118:           zz[i] = zz[i-1] + dz1;

119:           mass[i] = (float)i * 0.01f + xx[i];

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P6, P7,
Function	main
Source	main.c:116-119
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	2.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	12.80
Nb FLOP add-sub	48.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.60
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	92.86
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P6, P7,
Function	main
Source	main.c:116-119
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	2.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	12.80
Nb FLOP add-sub	48.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.60
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	92.86
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	main.c:116-119
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:116-119.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 8 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:119

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	21
nb uops	21
loop length	84
used w registers	0
used x registers	9
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	14
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	1.50	1.50	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	1.50	1.50	1.50	1.50	5.00	5.00	3.50	3.50	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.63
Dispatch	5.00
Data deps.	2.00
Overall L1	5.00

Vectorization ratios

INT

all	85%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

53% of peak store performance is reached (25.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410508

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
FADD Z18.S, Z7.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD X11, X21, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD Z19.S, Z5.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1W {Z18.S}, P0, [X11, X22,LSL #2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X11, X27, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD Z5.S, Z5.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z7.S, Z7.S, Z16.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1W {Z19.S}, P0, [X11, X22,LSL #2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FADD Z19.S, Z3.S, Z2.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD X11, X28, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD Z3.S, Z3.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1W {Z19.S}, P0, [X11, X22,LSL #2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
UCVTF Z19.S, P1/M, Z17.S	1	0	0	0	0	0	0	1	0	0	0	0	0	4	2	vect (100.0%)
ADD X11, X20, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD Z17.S, Z17.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z18.S, P1/M, Z19.S, Z21.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1W {Z18.S}, P0, [X11, X22,LSL #2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P0.S, X9, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 410508 <main+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	main.c:116-119
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:116-119.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 8 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:119

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	21
nb uops	21
loop length	84
used w registers	0
used x registers	9
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	14
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	1.50	1.50	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	1.50	1.50	1.50	1.50	5.00	5.00	3.50	3.50	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.63
Dispatch	5.00
Data deps.	2.00
Overall L1	5.00

Vectorization ratios

INT

all	85%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

53% of peak store performance is reached (25.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410508

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
FADD Z18.S, Z7.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD X11, X21, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD Z19.S, Z5.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1W {Z18.S}, P0, [X11, X22,LSL #2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X11, X27, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD Z5.S, Z5.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z7.S, Z7.S, Z16.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1W {Z19.S}, P0, [X11, X22,LSL #2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
FADD Z19.S, Z3.S, Z2.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD X11, X28, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD Z3.S, Z3.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ST1W {Z19.S}, P0, [X11, X22,LSL #2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
UCVTF Z19.S, P1/M, Z17.S	1	0	0	0	0	0	0	1	0	0	0	0	0	4	2	vect (100.0%)
ADD X11, X20, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD Z17.S, Z17.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z18.S, P1/M, Z19.S, Z21.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1W {Z18.S}, P0, [X11, X22,LSL #2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
WHILELO P0.S, X9, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 410508 <main+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code