OV - exec - Loop 5

	Loop Id: 5	Module: exec	Source: Step10_orig.c:19-35	Coverage: 97.56%

0x410940 LD1B	{Z8.B}, P1/Z, [X1, X12]    [6]

0x410944 LDR	Z0, [SP, #5, MUL VL]    [1]

0x410948 ADD	X16, X1, X12

0x41094c SUBS	X14, X14, X11

0x410950 FSUB	Z8.S, Z8.S, Z0.S

0x410954 LD1B	{Z9.B}, P1/Z, [X2, X12]    [7]

0x410958 LD1B	{Z10.B}, P1/Z, [X3, X12]    [8]

0x41095c FSUB	Z9.S, Z9.S, Z6.S

0x410960 FSUB	Z10.S, Z10.S, Z7.S

0x410964 LDR	Z18, [X16, #1, MUL VL]    [5]

0x410968 ADD	X16, X2, X12

0x41096c LDR	Z4, [X16, #1, MUL VL]    [4]

0x410970 ADD	X16, X3, X12

0x410974 LDR	Z14, [X16, #1, MUL VL]    [3]

0x410978 ADD	X16, X4, X12

0x41097c ADD	X12, X12, X15

0x410980 FSUB	Z18.S, Z18.S, Z0.S

0x410984 FMUL	Z11.S, Z8.S, Z8.S

0x410988 FSUB	Z4.S, Z4.S, Z6.S

0x41098c FMUL	Z15.S, Z18.S, Z18.S

0x410990 FSUB	Z14.S, Z14.S, Z7.S

0x410994 FMLA	Z11.S, P0/M, Z9.S, Z9.S

0x410998 FMLA	Z15.S, P0/M, Z4.S, Z4.S

0x41099c FMLA	Z15.S, P0/M, Z14.S, Z14.S

0x4109a0 MOVPRFX	Z12, Z11

0x4109a4 FMLA	Z12.S, P0/M, Z10.S, Z10.S

0x4109a8 FADD	Z3.S, Z15.S, Z17.S

0x4109ac FADD	Z13.S, Z12.S, Z17.S

0x4109b0 MOVPRFX	Z20, Z21

0x4109b4 FMLS	Z20.S, P0/M, Z12.S, Z1.S

0x4109b8 FCMGT	P3.S, P0/Z, Z16.S, Z12.S

0x4109bc UUNPKLO	Z2.D, Z3.S

0x4109c0 UUNPKHI	Z3.D, Z3.S

0x4109c4 UUNPKLO	Z11.D, Z13.S

0x4109c8 FMAD	Z20.S, P0/M, Z12.S, Z22.S

0x4109cc UUNPKHI	Z13.D, Z13.S

0x4109d0 FCVT	Z2.D, P2/M, Z2.S

0x4109d4 FCVT	Z3.D, P2/M, Z3.S

0x4109d8 FCVT	Z11.D, P2/M, Z11.S

0x4109dc FMAD	Z20.S, P0/M, Z12.S, Z23.S

0x4109e0 FCVT	Z13.D, P2/M, Z13.S

0x4109e4 FMAD	Z20.S, P0/M, Z12.S, Z24.S

0x4109e8 MOVPRFX	Z5, Z11

0x4109ec FSQRT	Z5.D, P2/M, Z11.D

0x4109f0 FMUL	Z11.D, Z11.D, Z11.D

0x4109f4 FMAD	Z20.S, P0/M, Z12.S, Z31.S

0x4109f8 FDIVR	Z11.D, P2/M, Z11.D, Z19.D

0x4109fc UUNPKLO	Z0.D, Z20.S

0x410a00 UUNPKHI	Z20.D, Z20.S

0x410a04 FCVT	Z0.D, P2/M, Z0.S

0x410a08 FCVT	Z20.D, P2/M, Z20.S

0x410a0c FNMLS	Z0.D, P2/M, Z11.D, Z5.D

0x410a10 MOVPRFX	Z5, Z13

0x410a14 FSQRT	Z5.D, P2/M, Z13.D

0x410a18 FMUL	Z13.D, Z13.D, Z13.D

0x410a1c MOVPRFX	Z11, Z2

0x410a20 FSQRT	Z11.D, P2/M, Z2.D

0x410a24 FMUL	Z2.D, Z2.D, Z2.D

0x410a28 FDIVR	Z13.D, P2/M, Z13.D, Z19.D

0x410a2c FDIVR	Z2.D, P2/M, Z2.D, Z19.D

0x410a30 FCVT	Z0.S, P2/M, Z0.D

0x410a34 FNMSB	Z5.D, P2/M, Z13.D, Z20.D

0x410a38 MOVPRFX	Z20, Z21

0x410a3c FMLS	Z20.S, P0/M, Z15.S, Z1.S

0x410a40 FMAD	Z20.S, P0/M, Z15.S, Z22.S

0x410a44 FMAD	Z20.S, P0/M, Z15.S, Z23.S

0x410a48 FCVT	Z5.S, P2/M, Z5.D

0x410a4c FMAD	Z20.S, P0/M, Z15.S, Z24.S

0x410a50 UZP1	Z0.S, Z0.S, Z5.S

0x410a54 LD1W	{Z5.S}, P3/Z, [X16, MUL VL]    [2]

0x410a58 FCMGT	P3.S, P0/Z, Z12.S, #0.0000000

0x410a5c FMAD	Z20.S, P0/M, Z15.S, Z31.S

0x410a60 UUNPKLO	Z13.D, Z20.S

0x410a64 UUNPKHI	Z20.D, Z20.S

0x410a68 FMUL	Z0.S, Z5.S, Z0.S

0x410a6c MOVI	V5.2D, #0

0x410a70 FCVT	Z13.D, P2/M, Z13.S

0x410a74 FCVT	Z20.D, P2/M, Z20.S

0x410a78 SEL	Z0.S, P3, Z0.S, Z5.S

0x410a7c FCMGT	P3.S, P0/Z, Z16.S, Z15.S

0x410a80 FNMSB	Z2.D, P2/M, Z11.D, Z13.D

0x410a84 MOVPRFX	Z11, Z3

0x410a88 FSQRT	Z11.D, P2/M, Z3.D

0x410a8c FMUL	Z3.D, Z3.D, Z3.D

0x410a90 FMLA	Z25.S, P0/M, Z0.S, Z8.S

0x410a94 FMLA	Z27.S, P0/M, Z0.S, Z9.S

0x410a98 FMLA	Z26.S, P0/M, Z0.S, Z10.S

0x410a9c FDIVR	Z3.D, P2/M, Z3.D, Z19.D

0x410aa0 FCVT	Z2.S, P2/M, Z2.D

0x410aa4 FNMSB	Z3.D, P2/M, Z11.D, Z20.D

0x410aa8 FCVT	Z3.S, P2/M, Z3.D

0x410aac UZP1	Z0.S, Z2.S, Z3.S

0x410ab0 LD1W	{Z2.S}, P3/Z, [X16, #1, MUL VL]    [2]

0x410ab4 FCMGT	P3.S, P0/Z, Z15.S, #0.0000000

0x410ab8 FMUL	Z0.S, Z2.S, Z0.S

0x410abc SEL	Z0.S, P3, Z0.S, Z5.S

0x410ac0 FMLA	Z28.S, P0/M, Z0.S, Z18.S

0x410ac4 FMLA	Z29.S, P0/M, Z0.S, Z4.S

0x410ac8 FMLA	Z30.S, P0/M, Z0.S, Z14.S

0x410acc B.NE	410940

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	main.c:155	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35 - 2.72
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	55.94 - 112.68
CQA cycles if no scalar integer	55.94 - 112.68
CQA cycles if FP arith vectorized	55.94 - 112.68
CQA cycles if fully vectorized	55.94 - 112.68
Front-end cycles	12.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	41.50
P7 cycles	41.50
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	55.94 - 112.68
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	100.00
Nb loads	NA
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	8.87 - 4.40
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	176.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.56 - 5.15
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	0.00
Vectorization ratio all	90.43
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	77.78
Vector-efficiency ratio all	98.40
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	91.67
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	97.92

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35 - 2.72
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	55.94 - 112.68
CQA cycles if no scalar integer	55.94 - 112.68
CQA cycles if FP arith vectorized	55.94 - 112.68
CQA cycles if fully vectorized	55.94 - 112.68
Front-end cycles	12.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	41.50
P7 cycles	41.50
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	55.94 - 112.68
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	100.00
Nb loads	NA
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	8.87 - 4.40
Nb FLOP add-sub	64.00
Nb FLOP mul	48.00
Nb FLOP fma	176.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	16.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.56 - 5.15
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.00
Stride indirect	0.00
Vectorization ratio all	90.43
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	77.78
Vector-efficiency ratio all	98.40
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	91.67
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	97.92

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU addition or subtraction instructions are used in vector version.
77% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 112.68 to 37.50 cycles (3.00x speedup).

FMA

Detected 176 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 12 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

240: addition or subtraction (176 inside FMA instructions)
224: multiply (176 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 288 bytes.

Arithmetic intensity

Arithmetic intensity is 1.72 FP operations per loaded or stored byte.

General properties

nb instructions	100
nb uops	100
loop length	400
used w registers	0
used x registers	9
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	1
used z registers	32
nb stack references	1
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	1.50	1.50	41.50	41.50	0.50	0.50	4.50	4.50	0.00	0.00	0.00
cycles	0.50	0.50	1.50	1.50	1.50	1.50	41.50	41.50	20.00	20.00	4.50	4.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	55.94-112.68
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	12.50
Dispatch	41.50
DIV/SQRT	55.94-112.68
Data deps.	2.00
Overall L1	55.94-112.68

Vectorization ratios

INT

all	70%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	90%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	88%
fma	100%
div/sqrt	100%
other	77%

Vector efficiency ratios

INT

all	95%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	96%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	98%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	91%
fma	100%
div/sqrt	100%
other	97%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 112.68 cycles. At this rate:

2% of peak load performance is reached (2.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1B {Z8.B}, P1/Z, [X1, X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z0, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X16, X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUBS X14, X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
FSUB Z8.S, Z8.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1B {Z9.B}, P1/Z, [X2, X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1B {Z10.B}, P1/Z, [X3, X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z9.S, Z9.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z10.S, Z10.S, Z7.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LDR Z18, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X16, X2, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z4, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X16, X3, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z14, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X16, X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FSUB Z18.S, Z18.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z11.S, Z8.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z4.S, Z4.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z15.S, Z18.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z14.S, Z14.S, Z7.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z11.S, P0/M, Z9.S, Z9.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z15.S, P0/M, Z4.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z15.S, P0/M, Z14.S, Z14.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z12, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z12.S, P0/M, Z10.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z3.S, Z15.S, Z17.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z13.S, Z12.S, Z17.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z20, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLS Z20.S, P0/M, Z12.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z16.S, Z12.S	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
UUNPKLO Z2.D, Z3.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
UUNPKHI Z3.D, Z3.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
UUNPKLO Z11.D, Z13.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z20.S, P0/M, Z12.S, Z22.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
UUNPKHI Z13.D, Z13.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCVT Z2.D, P2/M, Z2.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FCVT Z3.D, P2/M, Z3.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FCVT Z11.D, P2/M, Z11.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FMAD Z20.S, P0/M, Z12.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCVT Z13.D, P2/M, Z13.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FMAD Z20.S, P0/M, Z12.S, Z24.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z5, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSQRT Z5.D, P2/M, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z11.D, Z11.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z20.S, P0/M, Z12.S, Z31.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIVR Z11.D, P2/M, Z11.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
UUNPKLO Z0.D, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
UUNPKHI Z20.D, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCVT Z0.D, P2/M, Z0.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FCVT Z20.D, P2/M, Z20.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FNMLS Z0.D, P2/M, Z11.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z5, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSQRT Z5.D, P2/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z13.D, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z11, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSQRT Z11.D, P2/M, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z2.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z13.D, P2/M, Z13.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z2.D, P2/M, Z2.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCVT Z0.S, P2/M, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FNMSB Z5.D, P2/M, Z13.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z20, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLS Z20.S, P0/M, Z15.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z20.S, P0/M, Z15.S, Z22.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z20.S, P0/M, Z15.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCVT Z5.S, P2/M, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FMAD Z20.S, P0/M, Z15.S, Z24.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
UZP1 Z0.S, Z0.S, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1W {Z5.S}, P3/Z, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z12.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMAD Z20.S, P0/M, Z15.S, Z31.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
UUNPKLO Z13.D, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
UUNPKHI Z20.D, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.S, Z5.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVI V5.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (25.0%)
FCVT Z13.D, P2/M, Z13.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FCVT Z20.D, P2/M, Z20.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
SEL Z0.S, P3, Z0.S, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z16.S, Z15.S	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FNMSB Z2.D, P2/M, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSQRT Z11.D, P2/M, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z3.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z25.S, P0/M, Z0.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z27.S, P0/M, Z0.S, Z9.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z26.S, P0/M, Z0.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIVR Z3.D, P2/M, Z3.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCVT Z2.S, P2/M, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FNMSB Z3.D, P2/M, Z11.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCVT Z3.S, P2/M, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
UZP1 Z0.S, Z2.S, Z3.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1W {Z2.S}, P3/Z, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z15.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z0.S, Z2.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
SEL Z0.S, P3, Z0.S, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z28.S, P0/M, Z0.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z29.S, P0/M, Z0.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z30.S, P0/M, Z0.S, Z14.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
B.NE 410940 <Step10_orig+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU addition or subtraction instructions are used in vector version.
77% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 112.68 to 37.50 cycles (3.00x speedup).

FMA

Detected 176 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 12 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 496 FP arithmetical operations:

240: addition or subtraction (176 inside FMA instructions)
224: multiply (176 inside FMA instructions)
16: divide
16: square root

The binary loop is loading 288 bytes.

Arithmetic intensity

Arithmetic intensity is 1.72 FP operations per loaded or stored byte.

General properties

nb instructions	100
nb uops	100
loop length	400
used w registers	0
used x registers	9
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	1
used z registers	32
nb stack references	1
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	1.50	1.50	41.50	41.50	0.50	0.50	4.50	4.50	0.00	0.00	0.00
cycles	0.50	0.50	1.50	1.50	1.50	1.50	41.50	41.50	20.00	20.00	4.50	4.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	55.94-112.68
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	12.50
Dispatch	41.50
DIV/SQRT	55.94-112.68
Data deps.	2.00
Overall L1	55.94-112.68

Vectorization ratios

INT

all	70%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	90%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	88%
fma	100%
div/sqrt	100%
other	77%

Vector efficiency ratios

INT

all	95%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	96%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	98%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	91%
fma	100%
div/sqrt	100%
other	97%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 112.68 cycles. At this rate:

2% of peak load performance is reached (2.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1B {Z8.B}, P1/Z, [X1, X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LDR Z0, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X16, X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUBS X14, X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (25.0%)
FSUB Z8.S, Z8.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1B {Z9.B}, P1/Z, [X2, X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1B {Z10.B}, P1/Z, [X3, X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z9.S, Z9.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z10.S, Z10.S, Z7.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LDR Z18, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X16, X2, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z4, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X16, X3, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LDR Z14, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
ADD X16, X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FSUB Z18.S, Z18.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z11.S, Z8.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z4.S, Z4.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z15.S, Z18.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z14.S, Z14.S, Z7.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z11.S, P0/M, Z9.S, Z9.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z15.S, P0/M, Z4.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z15.S, P0/M, Z14.S, Z14.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z12, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z12.S, P0/M, Z10.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z3.S, Z15.S, Z17.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z13.S, Z12.S, Z17.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z20, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLS Z20.S, P0/M, Z12.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z16.S, Z12.S	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
UUNPKLO Z2.D, Z3.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
UUNPKHI Z3.D, Z3.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
UUNPKLO Z11.D, Z13.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z20.S, P0/M, Z12.S, Z22.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
UUNPKHI Z13.D, Z13.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCVT Z2.D, P2/M, Z2.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FCVT Z3.D, P2/M, Z3.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FCVT Z11.D, P2/M, Z11.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FMAD Z20.S, P0/M, Z12.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCVT Z13.D, P2/M, Z13.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FMAD Z20.S, P0/M, Z12.S, Z24.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z5, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSQRT Z5.D, P2/M, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z11.D, Z11.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z20.S, P0/M, Z12.S, Z31.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIVR Z11.D, P2/M, Z11.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
UUNPKLO Z0.D, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
UUNPKHI Z20.D, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCVT Z0.D, P2/M, Z0.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FCVT Z20.D, P2/M, Z20.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FNMLS Z0.D, P2/M, Z11.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z5, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSQRT Z5.D, P2/M, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z13.D, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z11, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSQRT Z11.D, P2/M, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z2.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z13.D, P2/M, Z13.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z2.D, P2/M, Z2.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCVT Z0.S, P2/M, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FNMSB Z5.D, P2/M, Z13.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z20, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMLS Z20.S, P0/M, Z15.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z20.S, P0/M, Z15.S, Z22.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z20.S, P0/M, Z15.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCVT Z5.S, P2/M, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FMAD Z20.S, P0/M, Z15.S, Z24.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
UZP1 Z0.S, Z0.S, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1W {Z5.S}, P3/Z, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z12.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMAD Z20.S, P0/M, Z15.S, Z31.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
UUNPKLO Z13.D, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
UUNPKHI Z20.D, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.S, Z5.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVI V5.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (25.0%)
FCVT Z13.D, P2/M, Z13.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FCVT Z20.D, P2/M, Z20.S	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
SEL Z0.S, P3, Z0.S, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z16.S, Z15.S	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FNMSB Z2.D, P2/M, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSQRT Z11.D, P2/M, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z3.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z25.S, P0/M, Z0.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z27.S, P0/M, Z0.S, Z9.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z26.S, P0/M, Z0.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIVR Z3.D, P2/M, Z3.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCVT Z2.S, P2/M, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
FNMSB Z3.D, P2/M, Z11.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FCVT Z3.S, P2/M, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	3	1	vect (100.0%)
UZP1 Z0.S, Z2.S, Z3.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1W {Z2.S}, P3/Z, [X16, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P3.S, P0/Z, Z15.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z0.S, Z2.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
SEL Z0.S, P3, Z0.S, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z28.S, P0/M, Z0.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z29.S, P0/M, Z0.S, Z4.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z30.S, P0/M, Z0.S, Z14.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
B.NE 410940 <Step10_orig+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code