OV - exec - Loop 6

	Loop Id: 6	Module: exec	Source: Step10_orig.c:19-35	Coverage: 0.02%

0x410ba4 LD1W	{Z0.D}, P0/Z, [X1, X11,LSL #2]    [2]

0x410ba8 LD1W	{Z29.D}, P0/Z, [X3, X11,LSL #2]    [4]

0x410bac FSUB	Z0.S, P0/M, Z0.S, Z20.S

0x410bb0 LD1W	{Z1.D}, P0/Z, [X2, X11,LSL #2]    [3]

0x410bb4 MOVPRFX	Z10, Z29

0x410bb8 FSUB	Z10.S, P0/M, Z10.S, Z6.S

0x410bbc FSUB	Z1.S, P0/M, Z1.S, Z21.S

0x410bc0 MOVPRFX	Z29, Z0

0x410bc4 FMUL	Z29.S, P0/M, Z29.S, Z0.S

0x410bc8 FMLA	Z29.S, P0/M, Z1.S, Z1.S

0x410bcc MOVPRFX	Z9, Z29

0x410bd0 FMLA	Z9.S, P0/M, Z10.S, Z10.S

0x410bd4 MOVPRFX	Z29, Z9

0x410bd8 FADD	Z29.S, P0/M, Z29.S, Z23.S

0x410bdc MOVPRFX	Z31, Z22

0x410be0 FMLS	Z31.S, P0/M, Z9.S, Z5.S

0x410be4 FCMGT	P1.S, P0/Z, Z7.S, Z9.S

0x410be8 FCVT	Z29.D, P0/M, Z29.S

0x410bec FMAD	Z31.S, P0/M, Z9.S, Z25.S

0x410bf0 LD1W	{Z8.D}, P1/Z, [X4, X11,LSL #2]    [1]

0x410bf4 FCMGT	P1.S, P0/Z, Z9.S, #0.0000000

0x410bf8 ADD	X11, X11, X9

0x410bfc CMP	X10, X11

0x410c00 FMAD	Z31.S, P0/M, Z9.S, Z26.S

0x410c04 MOVPRFX	Z30, Z29

0x410c08 FSQRT	Z30.D, P0/M, Z29.D

0x410c0c FMUL	Z29.D, Z29.D, Z29.D

0x410c10 FMAD	Z31.S, P0/M, Z9.S, Z27.S

0x410c14 FDIVR	Z29.D, P0/M, Z29.D, Z24.D

0x410c18 FMAD	Z31.S, P0/M, Z9.S, Z28.S

0x410c1c FCVT	Z31.D, P0/M, Z31.S

0x410c20 FNMSB	Z29.D, P0/M, Z30.D, Z31.D

0x410c24 FCVT	Z29.S, P0/M, Z29.D

0x410c28 FMUL	Z29.S, P0/M, Z29.S, Z8.S

0x410c2c SEL	Z29.D, P1, Z29.D, Z17.D

0x410c30 FMLA	Z16.S, P0/M, Z29.S, Z0.S

0x410c34 FMLA	Z19.S, P0/M, Z29.S, Z1.S

0x410c38 FMLA	Z18.S, P0/M, Z29.S, Z10.S

0x410c3c B.NE	410ba4

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

Coverage (%)	Name	Module
►100.00+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.76
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	6.06
CQA cycles	16.00 - 28.17
CQA cycles if no scalar integer	16.00 - 28.17
CQA cycles if FP arith vectorized	16.00 - 28.17
CQA cycles if fully vectorized	16.00 - 28.17
Front-end cycles	4.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	16.00
P7 cycles	16.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	14.25 - 8.09
Nb FLOP add-sub	32.00
Nb FLOP mul	20.00
Nb FLOP fma	84.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.54 - 8.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	83.33
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.76
Bottlenecks	P6, P8,
Function	Step10_orig
Source	Step10_orig.c:19-35
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	6.06
CQA cycles	16.00 - 28.17
CQA cycles if no scalar integer	16.00 - 28.17
CQA cycles if FP arith vectorized	16.00 - 28.17
CQA cycles if fully vectorized	16.00 - 28.17
Front-end cycles	4.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	16.00
P7 cycles	16.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	13.99 - 28.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	14.25 - 8.09
Nb FLOP add-sub	32.00
Nb FLOP mul	20.00
Nb FLOP fma	84.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.54 - 8.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	83.33
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

83% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 15.00 cycles (1.88x speedup).

FMA

Detected 84 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 228 FP arithmetical operations:

116: addition or subtraction (84 inside FMA instructions)
104: multiply (84 inside FMA instructions)
4: divide
4: square root

The binary loop is loading 128 bytes.

Arithmetic intensity

Arithmetic intensity is 1.78 FP operations per loaded or stored byte.

General properties

nb instructions	39
nb uops	39
loop length	156
used w registers	0
used x registers	7
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	16.00	16.00	0.00	0.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	16.00	16.00	9.00	9.00	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.88
Dispatch	16.00
DIV/SQRT	13.99-28.17
Data deps.	2.00
Overall L1	16.00-28.17

Vectorization ratios

INT

all	45%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	83%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.17 cycles. At this rate:

4% of peak load performance is reached (4.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410ba4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD1W {Z0.D}, P0/Z, [X1, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1W {Z29.D}, P0/Z, [X3, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z0.S, P0/M, Z0.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1W {Z1.D}, P0/Z, [X2, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z10, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSUB Z10.S, P0/M, Z10.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z1.S, P0/M, Z1.S, Z21.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z29.S, P0/M, Z29.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z29.S, P0/M, Z1.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z9, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z9.S, P0/M, Z10.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z29, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FADD Z29.S, P0/M, Z29.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z31, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLS Z31.S, P0/M, Z9.S, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCMGT P1.S, P0/Z, Z7.S, Z9.S	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
FCVT Z29.D, P0/M, Z29.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMAD Z31.S, P0/M, Z9.S, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1W {Z8.D}, P1/Z, [X4, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P1.S, P0/Z, Z9.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
ADD X11, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
FMAD Z31.S, P0/M, Z9.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z30.D, P0/M, Z29.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z29.D, Z29.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z31.S, P0/M, Z9.S, Z27.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FDIVR Z29.D, P0/M, Z29.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMAD Z31.S, P0/M, Z9.S, Z28.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z31.D, P0/M, Z31.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FNMSB Z29.D, P0/M, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z29.S, P0/M, Z29.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMUL Z29.S, P0/M, Z29.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
SEL Z29.D, P1, Z29.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z16.S, P0/M, Z29.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z19.S, P0/M, Z29.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z18.S, P0/M, Z29.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
B.NE 410ba4 <Step10_orig+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	Step10_orig
Source file and lines	Step10_orig.c:19-35
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-35.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

83% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 15.00 cycles (1.88x speedup).

FMA

Detected 84 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:29

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 228 FP arithmetical operations:

116: addition or subtraction (84 inside FMA instructions)
104: multiply (84 inside FMA instructions)
4: divide
4: square root

The binary loop is loading 128 bytes.

Arithmetic intensity

Arithmetic intensity is 1.78 FP operations per loaded or stored byte.

General properties

nb instructions	39
nb uops	39
loop length	156
used w registers	0
used x registers	7
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	16.00	16.00	0.00	0.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	16.00	16.00	9.00	9.00	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-28.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.88
Dispatch	16.00
DIV/SQRT	13.99-28.17
Data deps.	2.00
Overall L1	16.00-28.17

Vectorization ratios

INT

all	45%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	83%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.17 cycles. At this rate:

4% of peak load performance is reached (4.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410ba4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput	Vectorization
LD1W {Z0.D}, P0/Z, [X1, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1W {Z29.D}, P0/Z, [X3, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FSUB Z0.S, P0/M, Z0.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
LD1W {Z1.D}, P0/Z, [X2, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z10, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSUB Z10.S, P0/M, Z10.S, Z6.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FSUB Z1.S, P0/M, Z1.S, Z21.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMUL Z29.S, P0/M, Z29.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMLA Z29.S, P0/M, Z1.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z9, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLA Z9.S, P0/M, Z10.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z29, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FADD Z29.S, P0/M, Z29.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOVPRFX Z31, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FMLS Z31.S, P0/M, Z9.S, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCMGT P1.S, P0/Z, Z7.S, Z9.S	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
FCVT Z29.D, P0/M, Z29.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMAD Z31.S, P0/M, Z9.S, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
LD1W {Z8.D}, P1/Z, [X4, X11,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P1.S, P0/Z, Z9.S, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	2	1	vect (100.0%)
ADD X11, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
FMAD Z31.S, P0/M, Z9.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (100.0%)
FSQRT Z30.D, P0/M, Z29.D	1	0	0	0	0	0	0	1	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z29.D, Z29.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
FMAD Z31.S, P0/M, Z9.S, Z27.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FDIVR Z29.D, P0/M, Z29.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMAD Z31.S, P0/M, Z9.S, Z28.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z31.D, P0/M, Z31.S	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FNMSB Z29.D, P0/M, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FCVT Z29.S, P0/M, Z29.D	1	0	0	0	0	0	0	1	0	0	0	3	1	vect (100.0%)
FMUL Z29.S, P0/M, Z29.S, Z8.S	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (100.0%)
SEL Z29.D, P1, Z29.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
FMLA Z16.S, P0/M, Z29.S, Z0.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z19.S, P0/M, Z29.S, Z1.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
FMLA Z18.S, P0/M, Z29.S, Z10.S	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	vect (100.0%)
B.NE 410ba4 <Step10_orig+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code