OV - exec - Function main._omp

	Function: main._omp_fn.1	Module: exec	Source: main.c:142-149	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c: 142 - 149

--------------------------------------------------------------------------------

142:     #pragma omp parallel for private( dx1, dy1, dz1 )

143:       for ( i = 0; i < count; ++i)

144:       {

145:         Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 );

146:

147:         vx1[i] = vx1[i] + dx1 * fcoeff;

148:         vy1[i] = vy1[i] + dy1 * fcoeff;

149:         vz1[i] = vz1[i] + dz1 * fcoeff;

0x410660 STP	X29, X30, [SP, #848]!

0x410664 ADD	X29, SP, #0

0x410668 STP	X19, X20, [SP, #16]

0x41066c STP	X21, X22, [SP, #32]

0x410670 ORR	X21, XZR, X0

0x410674 STP	X27, X28, [SP, #80]

0x410678 LDR	W22, [X0, #16]

0x41067c BL	410090

0x410680 ORR	W20, WZR, W0

0x410684 BL	410050

0x410688 ORR	W19, WZR, W0

0x41068c SDIV	W27, W22, W20

0x410690 MSUB	W1, W27, W20, W22

0x410694 CMP	W0, W1

0x410698 B.LT	410924

0x41069c MADD	W0, W27, W19, W1

0x4106a0 ADD	W27, W27, W0

0x4106a4 CMP	W0, W27

0x4106a8 B.GE	410910

0x4106ac ADRP	X2,

0x4106b0 STP	X23, X24, [SP, #48]

0x4106b4 ADRP	X24,

0x4106b8 ADRP	X23,

0x4106bc SBFM	X10, X0, #62, #31

0x4106c0 ADD	X22, X2, #3936

0x4106c4 ADD	X4, X24, #4064

0x4106c8 STP	X25, X26, [SP, #64]

0x4106cc ADRP	X26,

0x4106d0 ADD	X23, X23, #1248

0x4106d4 ADD	X26, X26, #2656

0x4106d8 ORN	W5, WZR, W0

0x4106dc SBFM	X12, X0, #0, #31

0x4106e0 ADD	W11, W27, W5

0x4106e4 STP	D13, D14, [SP, #96]

0x4106e8 ORR	X3, XZR, X26

0x4106ec ADD	X7, SP, #172

0x4106f0 LDR	S2, [X26, X10]

0x4106f4 ADD	X6, SP, #168

0x4106f8 ADRP	X9,

0x4106fc ADRP	X8,

0x410700 ORR	X2, XZR, X23

0x410704 LDR	S1, [X23, X10]

0x410708 ORR	X1, XZR, X22

0x41070c ADD	X5, SP, #164

0x410710 ADD	X24, X9, #1376

0x410714 ADD	X25, X8, #2784

0x410718 LDR	S0, [X22, X10]

0x41071c AND	W20, W11, #0x1

0x410720 ADD	X19, X12, #1

0x410724 ADRP	X28,

0x410728 LDR	S14, [X21]

0x41072c ADD	X28, X28, #96

0x410730 LDR	S13, [X21, #8]

0x410734 LDR	W0, [X21, #12]

0x410738 STR	D15, [SP, #112]

0x41073c STP	X4, X10, [SP, #144]

0x410740 FMOV	S3, S14

0x410744 LDR	S15, [X21, #4]

0x410748 STR	W0, [SP, #140]

0x41074c FMOV	S4, S15

0x410750 BL	410a00

0x410754 LDR	X3, [SP, #152]

0x410758 LDR	S25, [SP, #172]

0x41075c LDP	S29, S27, [SP, #164]

0x410760 ADD	X6, X24, X3

0x410764 ADD	X7, X25, X3

0x410768 ADD	X13, X28, X3

0x41076c LDR	S26, [X7]

0x410770 LDR	S28, [X6]

0x410774 LDR	S24, [X13]

0x410778 FMADD	S0, S13, S27, S26

0x41077c FMADD	S1, S13, S29, S28

0x410780 FMADD	S2, S13, S25, S24

0x410784 STR	S0, [X7]

0x410788 STR	S1, [X6]

0x41078c STR	S2, [X13]

0x410790 CMP	W27, W19

0x410794 B.LE	410900

0x410798 CBZ	W20, 410820

0x41079c LDR	S2, [X26, X19,LSL #2]

0x4107a0 FMOV	S4, S15

0x4107a4 FMOV	S3, S14

0x4107a8 ADD	X7, SP, #172

0x4107ac ADD	X6, SP, #168

0x4107b0 LDR	S1, [X23, X19,LSL #2]

0x4107b4 ADD	X5, SP, #164

0x4107b8 ORR	X3, XZR, X26

0x4107bc ORR	X2, XZR, X23

0x4107c0 ORR	X1, XZR, X22

0x4107c4 LDR	S0, [X22, X19,LSL #2]

0x4107c8 UBFM	X21, X19, #62, #61

0x4107cc ADD	X19, X19, #1

0x4107d0 LDR	X4, [SP, #144]

0x4107d4 LDR	W0, [SP, #140]

0x4107d8 BL	410a00

0x4107dc ADD	X14, X24, X21

0x4107e0 ADD	X15, X25, X21

0x4107e4 LDR	S19, [SP, #172]

0x4107e8 ADD	X18, X28, X21

0x4107ec LDR	S20, [X15]

0x4107f0 LDR	S22, [X14]

0x4107f4 LDR	S18, [X18]

0x4107f8 LDP	S23, S21, [SP, #164]

0x4107fc FMADD	S5, S13, S19, S18

0x410800 FMADD	S3, S13, S23, S22

0x410804 FMADD	S4, S13, S21, S20

0x410808 STR	S5, [X18]

0x41080c STR	S4, [X15]

0x410810 STR	S3, [X14]

0x410814 CMP	W27, W19

0x410818 B.LE	410900

0x41081c HINT	#0

(2) 0x410820 UBFM	X21, X19, #62, #61

(2) 0x410824 LDR	X4, [SP, #144]

(2) 0x410828 ADD	X16, X19, #1

(2) 0x41082c FMOV	S4, S15

(2) 0x410830 FMOV	S3, S14

(2) 0x410834 ADD	X7, SP, #172

(2) 0x410838 LDR	S2, [X26, X21]

(2) 0x41083c ADD	X6, SP, #168

(2) 0x410840 ADD	X5, SP, #164

(2) 0x410844 ORR	X3, XZR, X26

(2) 0x410848 ORR	X2, XZR, X23

(2) 0x41084c LDR	S1, [X23, X21]

(2) 0x410850 ORR	X1, XZR, X22

(2) 0x410854 UBFM	X20, X16, #62, #61

(2) 0x410858 ADD	X19, X16, #1

(2) 0x41085c LDR	S0, [X22, X21]

(2) 0x410860 LDR	W0, [SP, #140]

(2) 0x410864 BL	410a00

(2) 0x410868 LDR	S30, [X28, X21]

(2) 0x41086c FMOV	S3, S14

(2) 0x410870 FMOV	S4, S15

(2) 0x410874 ADD	X7, SP, #172

(2) 0x410878 ADD	X6, SP, #168

(2) 0x41087c LDR	S16, [X24, X21]

(2) 0x410880 ADD	X5, SP, #164

(2) 0x410884 ORR	X3, XZR, X26

(2) 0x410888 ORR	X2, XZR, X23

(2) 0x41088c ORR	X1, XZR, X22

(2) 0x410890 LDR	S6, [X25, X21]

(2) 0x410894 LDR	S31, [SP, #172]

(2) 0x410898 LDP	S17, S7, [SP, #164]

(2) 0x41089c LDR	S2, [X26, X20]

(2) 0x4108a0 FMADD	S29, S13, S31, S30

(2) 0x4108a4 LDR	S1, [X23, X20]

(2) 0x4108a8 FMADD	S27, S13, S17, S16

(2) 0x4108ac FMADD	S25, S13, S7, S6

(2) 0x4108b0 LDR	S0, [X22, X20]

(2) 0x4108b4 LDR	X4, [SP, #144]

(2) 0x4108b8 LDR	W0, [SP, #140]

(2) 0x4108bc STR	S29, [X28, X21]

(2) 0x4108c0 STR	S27, [X24, X21]

(2) 0x4108c4 STR	S25, [X25, X21]

(2) 0x4108c8 BL	410a00

(2) 0x4108cc LDR	S26, [X24, X20]

(2) 0x4108d0 LDR	S0, [X25, X20]

(2) 0x4108d4 LDR	S28, [X28, X20]

(2) 0x4108d8 LDR	S20, [SP, #172]

(2) 0x4108dc LDP	S24, S1, [SP, #164]

(2) 0x4108e0 FMADD	S18, S13, S20, S28

(2) 0x4108e4 FMADD	S2, S13, S24, S26

(2) 0x4108e8 FMADD	S22, S13, S1, S0

(2) 0x4108ec STR	S18, [X28, X20]

(2) 0x4108f0 STR	S2, [X24, X20]

(2) 0x4108f4 STR	S22, [X25, X20]

(2) 0x4108f8 CMP	W27, W19

(2) 0x4108fc B.GT	410820

0x410900 LDR	D15, [SP, #112]

0x410904 LDP	X23, X24, [SP, #48]

0x410908 LDP	X25, X26, [SP, #64]

0x41090c LDP	D13, D14, [SP, #96]

0x410910 LDP	X19, X20, [SP, #16]

0x410914 LDP	X21, X22, [SP, #32]

0x410918 LDP	X27, X28, [SP, #80]

0x41091c LDP	X29, X30, [SP], #176

0x410920 RET

0x410924 ADD	W27, W27, #1

0x410928 MOVZ	W1, #0

0x41092c B	41069c

Coverage (%)	Name	Source Location	Module
►98.55+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.45+	GOMP_parallel		libgomp.so.1.0.0
○	main	main.c:155	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	main.c:69	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	main.c:142-149
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:142-149.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 12.50 cycles (1.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.00 to 12.50 cycles (1.28x speedup).

Details

5% of VPU instructions are used in vector version (process two or more data elements in vector registers):

12% of VPU loads are used in vector version.
6% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

Step10_orig: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:145
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:145
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:142
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:142

Matching between your function (in the source code) and the binary function

The binary function is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary function is loading 60 bytes. The binary function is storing 21 bytes.

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	124
nb uops	123
loop length	496
used w registers	9
used x registers	29
used b registers	0
used h registers	0
used s registers	22
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.38 cycles
front end	15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	14.75	14.75	14.75	14.75	4.50	4.50	4.50	4.50	16.00	16.00	16.00	4.00	4.00
cycles	5.50	5.50	14.75	14.75	14.75	14.75	4.50	4.50	4.50	4.50	16.00	16.00	16.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	15.38
Dispatch	16.00
DIV/SQRT	5.00-12.50
Overall L1	16.00

Vectorization ratios

INT

all	5%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	23%
load	18%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	12%
other	23%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	22%
load	18%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

3% of peak load performance is reached (3.75 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W22, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W27, W22, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W27, W20, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 410924 <main._omp_fn.1+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W0, W27, W19, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W27, W27, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 410910 <main._omp_fn.1+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X2, <6896ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X24, <5646b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X23, <6286b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X10, X0, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X22, X2, #3936	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X24, #4064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X26, <5c66cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X23, #1248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X26, X26, #2656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W5, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X12, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W11, W27, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ORR X3, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, SP, #172	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR S2, [X26, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
ADD X6, SP, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X9, <5036f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X8, <4a16fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR S1, [X23, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, SP, #164	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X9, #1376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X25, X8, #2784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR S0, [X22, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
AND W20, W11, #0x1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X19, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X28, <440724>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR S14, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
ADD X28, X28, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR S13, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR W0, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D15, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP X4, X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
FMOV S3, S14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
LDR S15, [X21, #4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
STR W0, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
FMOV S4, S15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
BL 410a00 <Step10_orig>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR S25, [SP, #172]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDP S29, S27, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (25.0%)
ADD X6, X24, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X28, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR S26, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S28, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S24, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
FMADD S0, S13, S27, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMADD S1, S13, S29, S28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMADD S2, S13, S25, S24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
STR S0, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S1, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S2, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
CMP W27, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 410900 <main._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W20, 410820 <main._omp_fn.1+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR S2, [X26, X19,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
FMOV S4, S15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMOV S3, S14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ADD X7, SP, #172	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR S1, [X23, X19,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
ADD X5, SP, #164	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X3, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR S0, [X22, X19,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
UBFM X21, X19, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410a00 <Step10_orig>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X24, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X25, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR S19, [SP, #172]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
ADD X18, X28, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR S20, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S22, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDP S23, S21, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (25.0%)
FMADD S5, S13, S19, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMADD S3, S13, S23, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMADD S4, S13, S21, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
STR S5, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S4, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S3, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
CMP W27, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 410900 <main._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
LDR D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W27, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 41069c <main._omp_fn.1+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	main.c:142-149
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:142-149.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

5% of VPU instructions are used in vector version (process two or more data elements in vector registers):

12% of VPU loads are used in vector version.
6% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Step10_orig: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:145
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:145
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:142
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:142

Matching between your function (in the source code) and the binary function

The binary function is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary function is loading 60 bytes. The binary function is storing 21 bytes.

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	124
nb uops	123
loop length	496
used w registers	9
used x registers	29
used b registers	0
used h registers	0
used s registers	22
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.38 cycles
front end	15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	14.75	14.75	14.75	14.75	4.50	4.50	4.50	4.50	16.00	16.00	16.00	4.00	4.00
cycles	5.50	5.50	14.75	14.75	14.75	14.75	4.50	4.50	4.50	4.50	16.00	16.00	16.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	15.38
Dispatch	16.00
DIV/SQRT	5.00-12.50
Overall L1	16.00

Vectorization ratios

INT

all	5%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	23%
load	18%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	12%
other	23%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	22%
load	18%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	24%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

3% of peak load performance is reached (3.75 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W22, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410090 <@plt_start@+0x70>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV W27, W22, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W27, W20, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 410924 <main._omp_fn.1+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W0, W27, W19, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W27, W27, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W0, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 410910 <main._omp_fn.1+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X2, <6896ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X24, <5646b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X23, <6286b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X10, X0, #62, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X22, X2, #3936	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X24, #4064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X26, <5c66cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X23, #1248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X26, X26, #2656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORN W5, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X12, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W11, W27, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
ORR X3, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, SP, #172	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR S2, [X26, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
ADD X6, SP, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X9, <5036f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X8, <4a16fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR S1, [X23, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, SP, #164	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X9, #1376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X25, X8, #2784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR S0, [X22, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
AND W20, W11, #0x1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X19, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X28, <440724>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR S14, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
ADD X28, X28, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR S13, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR W0, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D15, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP X4, X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
FMOV S3, S14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
LDR S15, [X21, #4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
STR W0, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
FMOV S4, S15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
BL 410a00 <Step10_orig>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR S25, [SP, #172]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDP S29, S27, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (25.0%)
ADD X6, X24, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X28, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR S26, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S28, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S24, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
FMADD S0, S13, S27, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMADD S1, S13, S29, S28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMADD S2, S13, S25, S24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
STR S0, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S1, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S2, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
CMP W27, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 410900 <main._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W20, 410820 <main._omp_fn.1+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR S2, [X26, X19,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
FMOV S4, S15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FMOV S3, S14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
ADD X7, SP, #172	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR S1, [X23, X19,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
ADD X5, SP, #164	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X3, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR S0, [X22, X19,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
UBFM X21, X19, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410a00 <Step10_orig>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X24, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X25, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR S19, [SP, #172]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
ADD X18, X28, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR S20, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S22, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDR S18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (12.5%)
LDP S23, S21, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (25.0%)
FMADD S5, S13, S19, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMADD S3, S13, S23, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
FMADD S4, S13, S21, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (12.5%)
STR S5, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S4, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S3, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
CMP W27, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 410900 <main._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
LDR D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W27, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 41069c <main._omp_fn.1+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.1–	0.04	0.01
○Loop 2 - main.c:145-149 - exec	0.04	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code