OV - exec - Loop 1

	Loop Id: 1	Module: exec	Source: main.c:114-119	Coverage: 0.04%

0x410310 FADD	S10, S5, S0

0x410314 FADD	S16, S28, S26

0x410318 ADD	X6, X5, #1

0x41031c FADD	S17, S29, S1

0x410320 ADD	X8, X5, #2

0x410324 SCVTF	S21, W5

0x410328 ADD	X9, X5, #3

0x41032c SCVTF	S23, W6

0x410330 UBFM	X7, X5, #62, #61

0x410334 SCVTF	S18, W8

0x410338 UBFM	X10, X6, #62, #61

0x41033c UBFM	X11, X8, #62, #61

0x410340 SCVTF	S30, W9

0x410344 UBFM	X12, X9, #62, #61

0x410348 ADD	X5, X5, #4

0x41034c FADD	S22, S10, S0

0x410350 FADD	S19, S16, S26

0x410354 STR	S10, [X23, X7]    [2]

0x410358 FADD	S20, S17, S1

0x41035c FMADD	S31, S21, S13, S10

0x410360 STR	S16, [X22, X7]    [1]

0x410364 STR	S17, [X28, X7]    [4]

0x410368 FADD	S27, S22, S0

0x41036c FADD	S2, S19, S26

0x410370 STR	S22, [X23, X10]    [2]

0x410374 FADD	S3, S20, S1

0x410378 FMADD	S25, S23, S13, S22

0x41037c STR	S19, [X22, X10]    [1]

0x410380 STR	S20, [X28, X10]    [4]

0x410384 STR	S31, [X27, X7]    [3]

0x410388 FADD	S5, S27, S0

0x41038c FMADD	S24, S18, S13, S27

0x410390 STR	S27, [X23, X11]    [2]

0x410394 FADD	S28, S2, S26

0x410398 FADD	S29, S3, S1

0x41039c STR	S2, [X22, X11]    [1]

0x4103a0 STR	S3, [X28, X11]    [4]

0x4103a4 STR	S25, [X27, X10]    [3]

0x4103a8 FMADD	S4, S30, S13, S5

0x4103ac STR	S5, [X23, X12]    [2]

0x4103b0 STR	S28, [X22, X12]    [1]

0x4103b4 STR	S29, [X28, X12]    [4]

0x4103b8 STR	S24, [X27, X11]    [3]

0x4103bc STR	S4, [X27, X12]    [3]

0x4103c0 CMP	W20, W5

0x4103c4 B.GT	410310

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c: 114 - 119

--------------------------------------------------------------------------------

114:       for ( i = 1; i < n; i++ )

115:       {

116:           xx[i] = xx[i-1] + dx1;

117:           yy[i] = yy[i-1] + dy1;

118:           zz[i] = zz[i-1] + dz1;

119:           mass[i] = (float)i * 0.01f + xx[i];

Coverage (%)	Name	Source Location	Module
►100.00+	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	main.c:69	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.51
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P6, P7, P8, P9, P10, P11,
Function	main
Source	main.c:114-119
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.07
Front-end cycles	5.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	4.00
P5 cycles	3.00
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	46.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	12.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	48.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	13.46
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	15.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.51
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P6, P7, P8, P9, P10, P11,
Function	main
Source	main.c:114-119
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.07
Front-end cycles	5.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	4.00
P5 cycles	3.00
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	46.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	12.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	48.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	13.46
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	15.00
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	main.c:114-119
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:114-119.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.07 cycles (7.51x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 4 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:119
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:119
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:119
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:119

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

16: addition or subtraction (4 inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.42 FP operations per loaded or stored byte.

General properties

nb instructions	46
nb uops	46
loop length	184
used w registers	5
used x registers	12
used b registers	0
used h registers	0
used s registers	24
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.00	3.00	4.00	3.00	8.00	8.00	8.00	8.00	8.00	8.00	0.00	0.00	0.00
cycles	0.50	0.50	3.00	3.00	4.00	3.00	8.00	8.00	8.00	8.00	8.00	8.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.75
Dispatch	8.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410310

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
FADD S10, S5, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FADD S16, S28, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
ADD X6, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
FADD S17, S29, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
ADD X8, X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
SCVTF S21, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD X9, X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
SCVTF S23, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
UBFM X7, X5, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SCVTF S18, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
UBFM X10, X6, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
UBFM X11, X8, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SCVTF S30, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
UBFM X12, X9, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD S22, S10, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FADD S19, S16, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
STR S10, [X23, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FADD S20, S17, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FMADD S31, S21, S13, S10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	scal (12.5%)
STR S16, [X22, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S17, [X28, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FADD S27, S22, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FADD S2, S19, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
STR S22, [X23, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FADD S3, S20, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FMADD S25, S23, S13, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	scal (12.5%)
STR S19, [X22, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S20, [X28, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S31, [X27, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FADD S5, S27, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FMADD S24, S18, S13, S27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	scal (12.5%)
STR S27, [X23, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FADD S28, S2, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FADD S29, S3, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
STR S2, [X22, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S3, [X28, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S25, [X27, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FMADD S4, S30, S13, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	scal (12.5%)
STR S5, [X23, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S28, [X22, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S29, [X28, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S24, [X27, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S4, [X27, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
CMP W20, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.GT 410310 <main+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	main.c:114-119
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:114-119.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 4 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:119
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:119
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:119
- /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/main.c:119

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

16: addition or subtraction (4 inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.42 FP operations per loaded or stored byte.

General properties

nb instructions	46
nb uops	46
loop length	184
used w registers	5
used x registers	12
used b registers	0
used h registers	0
used s registers	24
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.00	3.00	4.00	3.00	8.00	8.00	8.00	8.00	8.00	8.00	0.00	0.00	0.00
cycles	0.50	0.50	3.00	3.00	4.00	3.00	8.00	8.00	8.00	8.00	8.00	8.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.75
Dispatch	8.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	15%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410310

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
FADD S10, S5, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FADD S16, S28, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
ADD X6, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
FADD S17, S29, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
ADD X8, X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
SCVTF S21, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD X9, X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (25.0%)
SCVTF S23, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
UBFM X7, X5, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SCVTF S18, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
UBFM X10, X6, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
UBFM X11, X8, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SCVTF S30, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	3	1	scal (12.5%)
UBFM X12, X9, #62, #61	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
FADD S22, S10, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FADD S19, S16, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
STR S10, [X23, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FADD S20, S17, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FMADD S31, S21, S13, S10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	scal (12.5%)
STR S16, [X22, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S17, [X28, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FADD S27, S22, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FADD S2, S19, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
STR S22, [X23, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FADD S3, S20, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FMADD S25, S23, S13, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	scal (12.5%)
STR S19, [X22, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S20, [X28, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S31, [X27, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FADD S5, S27, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FMADD S24, S18, S13, S27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	scal (12.5%)
STR S27, [X23, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FADD S28, S2, S26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
FADD S29, S3, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (12.5%)
STR S2, [X22, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S3, [X28, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S25, [X27, X10]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
FMADD S4, S30, S13, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	scal (12.5%)
STR S5, [X23, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S28, [X22, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S29, [X28, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S24, [X27, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
STR S4, [X27, X12]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	2	0.50	scal (12.5%)
CMP W20, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.GT 410310 <main+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code