OV - exec - Function Step10

	Function: Step10_orig	Module: exec	Source: Step10_orig.c:19-41	Coverage (incl. loops): 97.69% \| (excl. loops): 0.05%

/home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 41

--------------------------------------------------------------------------------

19:     for ( j = 0; j < count1; j++ )

20:     {

21:         dxc = xx1[j] - xxi;

22:         dyc = yy1[j] - yyi;

23:         dzc = zz1[j] - zzi;

24:

25:         r2 = dxc * dxc + dyc * dyc + dzc * dzc;

26:

27:         m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f;

28:

29:         f =  pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5)))));

30:

31:         f = ( r2 > 0.0f ) ? m * f : 0.0f;

32:

33:         xi = xi + f * dxc;

34:         yi = yi + f * dyc;

35:         zi = zi + f * dzc;

36:     }

37:

38:     *dxi = xi;

39:     *dyi = yi;

40:     *dzi = zi;

41: }

0x410840 CMP	W0, #1

0x410844 B.LT	410888

0x410848 STP	D15, D14, [SP, #944]!

0x41084c STP	D13, D12, [SP, #16]

0x410850 STP	D11, D10, [SP, #32]

0x410854 STP	D9, D8, [SP, #48]

0x410858 STR	X29, [SP, #64]

0x41085c ADDVL	SP, SP, #58

0x410860 FMOV	S12, S0

0x410864 MOVI	D13, #0

0x410868 CMP	W0, #4

0x41086c ORR	W8, WZR, W0

0x410870 B.CS	410898

0x410874 ORR	X9, XZR, XZR

0x410878 MOVI	D6, #0

0x41087c MOVI	D7, #0

0x410880 MOVI	D16, #0

0x410884 B	410cf4

0x410888 MOVI	D16, #0

0x41088c MOVI	D7, #0

0x410890 MOVI	D6, #0

0x410894 B	410ce4

0x410898 CMP	W0, #16

0x41089c B.CS	4108b4

0x4108a0 ORR	X9, XZR, XZR

0x4108a4 MOVI	D6, #0

0x4108a8 MOVI	D7, #0

0x4108ac MOVI	D16, #0

0x4108b0 B	410b68

0x4108b4 MOVZ	W15, #63002

0x4108b8 MOVZ	W13, #35234

0x4108bc STR	Z1, [SP, #1, MUL VL]

0x4108c0 DUP	Z7.S, Z1.S[0]

0x4108c4 DUP	Z0.S, Z12.S[0]

0x4108c8 PTRUE	P0.S, ALL

0x4108cc MOVI	V19.2D, #0

0x4108d0 MOVK	W15, #14461

0x4108d4 MOVK	W13, #13765

0x4108d8 DUP	Z16.S, Z2.S[0]

0x4108dc DUP	Z17.S, Z3.S[0]

0x4108e0 PTRUE	P1.D, ALL

0x4108e4 MOVI	V31.2D, #0

0x4108e8 MOVI	V28.2D, #0

0x4108ec MOVI	V30.2D, #0

0x4108f0 DUP	Z22.S, W15

0x4108f4 MOVZ	W15, #18267

0x4108f8 DUP	Z20.S, Z4.S[0]

0x4108fc FDUP	Z21.D, #112

0x410900 MOVI	V27.2D, #0

0x410904 MOVI	V29.2D, #0

0x410908 DUP	Z1.S, W13

0x41090c AND	X10, X8, #0x0

0x410910 MOVK	W15, #47759

0x410914 AND	X9, X8, #0x0

0x410918 ADD	X11, X1, #32

0x41091c ADD	X12, X4, #32

0x410920 ADD	X13, X2, #32

0x410924 ADD	X14, X3, #32

0x410928 STR	Z12, [SP, MUL VL]

0x41092c DUP	Z23.S, W15

0x410930 MOVZ	W15, #6647

0x410934 STR	Z0, [SP, #5, MUL VL]

0x410938 STR	Z2, [SP, #2, MUL VL]

0x41093c STR	Z3, [SP, #3, MUL VL]

0x410940 MOVK	W15, #15420

0x410944 PTRUE	P2.S, VL4

0x410948 STR	Z4, [SP, #4, MUL VL]

0x41094c DUP	Z24.S, W15

0x410950 MOVZ	W15, #52448

0x410954 MOVK	W15, #48537

0x410958 DUP	Z25.S, W15

0x41095c MOVZ	W15, #58683

0x410960 MOVK	W15, #16009

0x410964 DUP	Z26.S, W15

0x410968 AND	X15, X8, #0x0

(5) 0x41096c LDR	Z8, [X11, #511, MUL VL]

(5) 0x410970 LDR	Z0, [SP, #5, MUL VL]

(5) 0x410974 SUBS	X15, X15, #16

(5) 0x410978 FSUB	Z8.S, Z8.S, Z0.S

(5) 0x41097c LDR	Z9, [X13, #511, MUL VL]

(5) 0x410980 LDR	Z10, [X14, #511, MUL VL]

(5) 0x410984 FSUB	Z9.S, Z9.S, Z7.S

(5) 0x410988 FSUB	Z10.S, Z10.S, Z16.S

(5) 0x41098c LDR	Z6, [X11, MUL VL]

(5) 0x410990 LDR	Z13, [X14, MUL VL]

(5) 0x410994 FSUB	Z13.S, Z13.S, Z16.S

(5) 0x410998 ADD	X11, X11, #64

(5) 0x41099c ADD	X14, X14, #64

(5) 0x4109a0 FMUL	Z11.S, Z8.S, Z8.S

(5) 0x4109a4 FMLA	Z11.S, P0/M, Z9.S, Z9.S

(5) 0x4109a8 MOVPRFX	Z14, Z11

(5) 0x4109ac FMLA	Z14.S, P0/M, Z10.S, Z10.S

(5) 0x4109b0 FADD	Z11.S, Z14.S, Z20.S

(5) 0x4109b4 MOVPRFX	Z18, Z22

(5) 0x4109b8 FMLS	Z18.S, P0/M, Z14.S, Z1.S

(5) 0x4109bc FCMGT	P3.S, P0/Z, Z17.S, Z14.S

(5) 0x4109c0 FCMGT	P4.S, P0/Z, Z14.S, #0.0000000

(5) 0x4109c4 MOVPRFX	Z12, Z11

(5) 0x4109c8 EXT	Z12.B, Z12.B, Z11.B, #16

(5) 0x4109cc FMAD	Z18.S, P0/M, Z14.S, Z23.S

(5) 0x4109d0 UUNPKLO	Z5.D, Z11.S

(5) 0x4109d4 FSUB	Z11.S, Z6.S, Z0.S

(5) 0x4109d8 LDR	Z6, [X13, MUL VL]

(5) 0x4109dc ADD	X13, X13, #64

(5) 0x4109e0 UUNPKLO	Z12.D, Z12.S

(5) 0x4109e4 FMAD	Z18.S, P0/M, Z14.S, Z24.S

(5) 0x4109e8 FCVT	Z5.D, P1/M, Z5.S

(5) 0x4109ec FMUL	Z15.S, Z11.S, Z11.S

(5) 0x4109f0 FCVT	Z12.D, P1/M, Z12.S

(5) 0x4109f4 FMAD	Z18.S, P0/M, Z14.S, Z25.S

(5) 0x4109f8 FMAD	Z18.S, P0/M, Z14.S, Z26.S

(5) 0x4109fc FSUB	Z6.S, Z6.S, Z7.S

(5) 0x410a00 MOVPRFX	Z4, Z12

(5) 0x410a04 FSQRT	Z4.D, P1/M, Z12.D

(5) 0x410a08 FMUL	Z12.D, Z12.D, Z12.D

(5) 0x410a0c FMLA	Z15.S, P0/M, Z6.S, Z6.S

(5) 0x410a10 FDIVR	Z12.D, P1/M, Z12.D, Z21.D

(5) 0x410a14 MOVPRFX	Z0, Z18

(5) 0x410a18 EXT	Z0.B, Z0.B, Z18.B, #16

(5) 0x410a1c FMLA	Z15.S, P0/M, Z13.S, Z13.S

(5) 0x410a20 UUNPKLO	Z18.D, Z18.S

(5) 0x410a24 UUNPKLO	Z0.D, Z0.S

(5) 0x410a28 FCVT	Z18.D, P1/M, Z18.S

(5) 0x410a2c FCVT	Z0.D, P1/M, Z0.S

(5) 0x410a30 FADD	Z3.S, Z15.S, Z20.S

(5) 0x410a34 MOVPRFX	Z2, Z3

(5) 0x410a38 EXT	Z2.B, Z2.B, Z3.B, #16

(5) 0x410a3c UUNPKLO	Z3.D, Z3.S

(5) 0x410a40 UUNPKLO	Z2.D, Z2.S

(5) 0x410a44 FCVT	Z3.D, P1/M, Z3.S

(5) 0x410a48 FCVT	Z2.D, P1/M, Z2.S

(5) 0x410a4c FNMLS	Z0.D, P1/M, Z12.D, Z4.D

(5) 0x410a50 MOVPRFX	Z4, Z5

(5) 0x410a54 FSQRT	Z4.D, P1/M, Z5.D

(5) 0x410a58 FMUL	Z5.D, Z5.D, Z5.D

(5) 0x410a5c MOVPRFX	Z12, Z2

(5) 0x410a60 FSQRT	Z12.D, P1/M, Z2.D

(5) 0x410a64 FMUL	Z2.D, Z2.D, Z2.D

(5) 0x410a68 FDIVR	Z5.D, P1/M, Z5.D, Z21.D

(5) 0x410a6c FDIVR	Z2.D, P1/M, Z2.D, Z21.D

(5) 0x410a70 FCVT	Z0.S, P1/M, Z0.D

(5) 0x410a74 UZP1	Z0.S, Z0.S, Z0.S

(5) 0x410a78 FNMSB	Z4.D, P1/M, Z5.D, Z18.D

(5) 0x410a7c MOVPRFX	Z5, Z22

(5) 0x410a80 FMLS	Z5.S, P0/M, Z15.S, Z1.S

(5) 0x410a84 FMAD	Z5.S, P0/M, Z15.S, Z23.S

(5) 0x410a88 FMAD	Z5.S, P0/M, Z15.S, Z24.S

(5) 0x410a8c FCVT	Z4.S, P1/M, Z4.D

(5) 0x410a90 FMAD	Z5.S, P0/M, Z15.S, Z25.S

(5) 0x410a94 UZP1	Z4.S, Z4.S, Z4.S

(5) 0x410a98 FMAD	Z5.S, P0/M, Z15.S, Z26.S

(5) 0x410a9c SPLICE	Z4.S, P2, Z4.S, Z0.S

(5) 0x410aa0 LD1W	{Z0.S}, P3/Z, [X12, #15, MUL VL]

(5) 0x410aa4 FCMGT	P3.S, P0/Z, Z17.S, Z15.S

(5) 0x410aa8 MOVPRFX	Z18, Z5

(5) 0x410aac EXT	Z18.B, Z18.B, Z5.B, #16

(5) 0x410ab0 UUNPKLO	Z5.D, Z5.S

(5) 0x410ab4 UUNPKLO	Z18.D, Z18.S

(5) 0x410ab8 FCVT	Z5.D, P1/M, Z5.S

(5) 0x410abc FMUL	Z0.S, Z0.S, Z4.S

(5) 0x410ac0 CPY	Z4.S, P4/Z, #255

(5) 0x410ac4 FCVT	Z18.D, P1/M, Z18.S

(5) 0x410ac8 AND	Z0.D, Z4.D, Z0.D

(5) 0x410acc FNMSB	Z2.D, P1/M, Z12.D, Z18.D

(5) 0x410ad0 MOVPRFX	Z18, Z3

(5) 0x410ad4 FSQRT	Z18.D, P1/M, Z3.D

(5) 0x410ad8 FMUL	Z3.D, Z3.D, Z3.D

(5) 0x410adc FMLA	Z27.S, P0/M, Z0.S, Z8.S

(5) 0x410ae0 FMLA	Z28.S, P0/M, Z0.S, Z9.S

(5) 0x410ae4 FMLA	Z19.S, P0/M, Z0.S, Z10.S

(5) 0x410ae8 FDIVR	Z3.D, P1/M, Z3.D, Z21.D

(5) 0x410aec FCVT	Z2.S, P1/M, Z2.D

(5) 0x410af0 UZP1	Z2.S, Z2.S, Z2.S

(5) 0x410af4 FNMSB	Z3.D, P1/M, Z18.D, Z5.D

(5) 0x410af8 FCVT	Z3.S, P1/M, Z3.D

(5) 0x410afc UZP1	Z0.S, Z3.S, Z3.S

(5) 0x410b00 SPLICE	Z0.S, P2, Z0.S, Z2.S

(5) 0x410b04 LD1W	{Z2.S}, P3/Z, [X12, MUL VL]

(5) 0x410b08 FCMGT	P3.S, P0/Z, Z15.S, #0.0000000

(5) 0x410b0c ADD	X12, X12, #64

(5) 0x410b10 FMUL	Z0.S, Z2.S, Z0.S

(5) 0x410b14 CPY	Z2.S, P3/Z, #255

(5) 0x410b18 AND	Z0.D, Z2.D, Z0.D

(5) 0x410b1c FMLA	Z29.S, P0/M, Z0.S, Z11.S

(5) 0x410b20 FMLA	Z30.S, P0/M, Z0.S, Z6.S

(5) 0x410b24 FMLA	Z31.S, P0/M, Z0.S, Z13.S

(5) 0x410b28 B.NE	41096c

0x410b2c FADD	Z0.S, Z31.S, Z19.S

0x410b30 CMP	X9, X8

0x410b34 FADDV	S6, P0, Z0.S

0x410b38 FADD	Z0.S, Z30.S, Z28.S

0x410b3c FADDV	S7, P0, Z0.S

0x410b40 FADD	Z0.S, Z29.S, Z27.S

0x410b44 FADDV	S16, P0, Z0.S

0x410b48 B.EQ	410ccc

0x410b4c LDR	Z4, [SP, #4, MUL VL]

0x410b50 LDR	Z3, [SP, #3, MUL VL]

0x410b54 MOVI	D13, #0

0x410b58 LDR	Z2, [SP, #2, MUL VL]

0x410b5c LDR	Z1, [SP, #1, MUL VL]

0x410b60 LDR	Z12, [SP, MUL VL]

0x410b64 CBZ	X10, 410cf4

0x410b68 MOVI	V19.2D, #0

0x410b6c MOVZ	W15, #35234

0x410b70 MOVI	V17.2D, #0

0x410b74 MOVI	V18.2D, #0

0x410b78 ORR	X14, XZR, X9

0x410b7c AND	X9, X8, #0x0

0x410b80 DUP	V20.4S, V12.S[0]

0x410b84 PTRUE	P0.S, VL4

0x410b88 MOVK	W15, #13765

0x410b8c DUP	V21.4S, V1.S[0]

0x410b90 DUP	V22.4S, V2.S[0]

0x410b94 DUP	V23.4S, V3.S[0]

0x410b98 ORR	Z8.D, Z4.D, Z4.D

0x410b9c PTRUE	P1.D, ALL

0x410ba0 SUB	X10, X14, X9

0x410ba4 ADD	X11, X4, X14,LSL #2

0x410ba8 MOV	V19.S[0], V7.S[0]

0x410bac DUP	V7.4S, W15

0x410bb0 MOVZ	W15, #63002

0x410bb4 MOV	V17.S[0], V16.S[0]

0x410bb8 DUP	V24.4S, V4.S[0]

0x410bbc MOV	V18.S[0], V6.S[0]

0x410bc0 FDUP	Z6.D, #112

0x410bc4 ADD	X12, X3, X14,LSL #2

0x410bc8 MOVK	W15, #47229

0x410bcc ADD	X13, X2, X14,LSL #2

0x410bd0 ADD	X14, X1, X14,LSL #2

0x410bd4 DUP	V16.4S, W15

0x410bd8 MOVZ	W15, #18267

0x410bdc MOVK	W15, #14991

0x410be0 DUP	V25.4S, W15

0x410be4 MOVZ	W15, #6647

0x410be8 MOVK	W15, #48188

0x410bec DUP	V26.4S, W15

0x410bf0 MOVZ	W15, #52448

0x410bf4 MOVK	W15, #15769

0x410bf8 DUP	V27.4S, W15

0x410bfc MOVZ	W15, #58683

0x410c00 MOVK	W15, #48777

0x410c04 DUP	V28.4S, W15

(6) 0x410c08 LDR	Q4, [X13], #16

(6) 0x410c0c LDR	Q0, [X14], #16

(6) 0x410c10 ORR	V29.16B, V16.16B, V16.16B

(6) 0x410c14 ORR	V30.16B, V25.16B, V25.16B

(6) 0x410c18 FSUB	V11.4S, V4.4S, V21.4S

(6) 0x410c1c FSUB	V0.4S, V0.4S, V20.4S

(6) 0x410c20 LDR	Q4, [X12], #16

(6) 0x410c24 FMUL	V9.4S, V0.4S, V0.4S

(6) 0x410c28 FMLA	V9.4S, V11.4S, V11.4S

(6) 0x410c2c FSUB	V10.4S, V4.4S, V22.4S

(6) 0x410c30 FMLA	V9.4S, V10.4S, V10.4S

(6) 0x410c34 FCMGT	V4.4S, V23.4S, V9.4S

(6) 0x410c38 FMLA	V29.4S, V7.4S, V9.4S

(6) 0x410c3c CMPNE	P2.S, P0/Z, Z4.S, #0

(6) 0x410c40 FADD	V4.4S, V9.4S, V24.4S

(6) 0x410c44 ADDS	X10, X10, #4

(6) 0x410c48 UUNPKLO	Z4.D, Z4.S

(6) 0x410c4c FMLA	V30.4S, V9.4S, V29.4S

(6) 0x410c50 ORR	V29.16B, V26.16B, V26.16B

(6) 0x410c54 FCVT	Z4.D, P1/M, Z4.S

(6) 0x410c58 LD1W	{Z31.S}, P2/Z, [X11, MUL VL]

(6) 0x410c5c ADD	X11, X11, #16

(6) 0x410c60 FMLA	V29.4S, V9.4S, V30.4S

(6) 0x410c64 ORR	V30.16B, V27.16B, V27.16B

(6) 0x410c68 MOVPRFX	Z5, Z4

(6) 0x410c6c FSQRT	Z5.D, P1/M, Z4.D

(6) 0x410c70 FMUL	Z4.D, Z4.D, Z4.D

(6) 0x410c74 FDIVR	Z4.D, P1/M, Z4.D, Z6.D

(6) 0x410c78 FMLA	V30.4S, V9.4S, V29.4S

(6) 0x410c7c ORR	V29.16B, V28.16B, V28.16B

(6) 0x410c80 FMLA	V29.4S, V9.4S, V30.4S

(6) 0x410c84 UUNPKLO	Z29.D, Z29.S

(6) 0x410c88 FCVT	Z29.D, P1/M, Z29.S

(6) 0x410c8c FMAD	Z4.D, P1/M, Z5.D, Z29.D

(6) 0x410c90 FCMGT	V5.4S, V9.4S, #0.0000000

(6) 0x410c94 FCVT	Z4.S, P1/M, Z4.D

(6) 0x410c98 UZP1	Z4.S, Z4.S, Z4.S

(6) 0x410c9c FMUL	V4.4S, V31.4S, V4.4S

(6) 0x410ca0 AND	V4.16B, V5.16B, V4.16B

(6) 0x410ca4 FMLA	V17.4S, V0.4S, V4.4S

(6) 0x410ca8 FMLA	V19.4S, V11.4S, V4.4S

(6) 0x410cac FMLA	V18.4S, V10.4S, V4.4S

(6) 0x410cb0 B.NE	410c08

0x410cb4 FADDV	S6, P0, Z18.S

0x410cb8 CMP	X9, X8

0x410cbc ORR	Z4.D, Z8.D, Z8.D

0x410cc0 FADDV	S7, P0, Z19.S

0x410cc4 FADDV	S16, P0, Z17.S

0x410cc8 B.NE	410cf4

0x410ccc ADDVL	SP, SP, #6

0x410cd0 LDP	D9, D8, [SP, #48]

0x410cd4 LDP	D11, D10, [SP, #32]

0x410cd8 LDP	D13, D12, [SP, #16]

0x410cdc LDR	X29, [SP, #64]

0x410ce0 LDP	D15, D14, [SP], #80

0x410ce4 STR	S16, [X5]

0x410ce8 STR	S7, [X6]

0x410cec STR	S6, [X7]

0x410cf0 RET

0x410cf4 ADD	X10, X4, X9,LSL #2

0x410cf8 ADD	X11, X3, X9,LSL #2

0x410cfc ADD	X12, X2, X9,LSL #2

0x410d00 ADD	X13, X1, X9,LSL #2

0x410d04 FMOV	D17, #1.0000000

0x410d08 SUB	X8, X8, X9

0x410d0c MOVZ	W9, #63002

0x410d10 MOVK	W9, #47229

0x410d14 FMOV	S18, W9

0x410d18 MOVZ	W9, #35234

0x410d1c MOVK	W9, #13765

0x410d20 FMOV	S19, W9

0x410d24 MOVZ	W9, #18267

0x410d28 MOVK	W9, #14991

0x410d2c FMOV	S20, W9

0x410d30 MOVZ	W9, #6647

0x410d34 MOVK	W9, #48188

0x410d38 FMOV	S21, W9

0x410d3c MOVZ	W9, #52448

0x410d40 MOVK	W9, #15769

0x410d44 FMOV	S22, W9

0x410d48 MOVZ	W9, #58683

0x410d4c MOVK	W9, #48777

0x410d50 FMOV	S23, W9

0x410d54 B	410db8

0x410d58 HINT	#0

0x410d5c HINT	#0

(4) 0x410d60 FADD	S0, S27, S4

(4) 0x410d64 FMADD	S5, S27, S19, S18

(4) 0x410d68 FCMP	S27, #0

(4) 0x410d6c ADD	X10, X10, #4

(4) 0x410d70 FCVT	D0, S0

(4) 0x410d74 FMADD	S5, S5, S27, S20

(4) 0x410d78 FSQRT	D29, D0

(4) 0x410d7c FMUL	D0, D0, D0

(4) 0x410d80 FDIV	D0, D17, D0

(4) 0x410d84 FMADD	S5, S5, S27, S21

(4) 0x410d88 FMADD	S5, S5, S27, S22

(4) 0x410d8c FMADD	S5, S5, S27, S23

(4) 0x410d90 FCVT	D5, S5

(4) 0x410d94 FMADD	D0, D0, D29, D5

(4) 0x410d98 FCVT	S0, D0

(4) 0x410d9c FMUL	S0, S28, S0

(4) 0x410da0 FCSEL	S0, S0, S13, #12

(4) 0x410da4 SUBS	X8, X8, #1

(4) 0x410da8 FMADD	S16, S0, S24, S16

(4) 0x410dac FMADD	S7, S0, S25, S7

(4) 0x410db0 FMADD	S6, S0, S26, S6

(4) 0x410db4 B.EQ	410ccc

(4) 0x410db8 LDR	S0, [X13], #4

(4) 0x410dbc MOVI	D28, #0

(4) 0x410dc0 FSUB	S24, S0, S12

(4) 0x410dc4 LDR	S0, [X12], #4

(4) 0x410dc8 FSUB	S25, S0, S1

(4) 0x410dcc LDR	S0, [X11], #4

(4) 0x410dd0 FSUB	S26, S0, S2

(4) 0x410dd4 FMUL	S0, S24, S24

(4) 0x410dd8 FMADD	S0, S25, S25, S0

(4) 0x410ddc FMADD	S27, S26, S26, S0

(4) 0x410de0 FCMP	S27, S3

(4) 0x410de4 B.GE	410d60

(4) 0x410de8 LDR	S28, [X10]

(4) 0x410dec B	410d60

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	main.c:155	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.05% of application time for run armclang_7

Source file and lines	Step10_orig.c:19-41
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-41.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.38 to 17.00 cycles (1.26x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 41% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 21.38 to 16.81 cycles (1.27x speedup).

Details

32% of VPU instructions are used in vector version (process two or more data elements in vector registers):

90% of VPU loads are used in vector version.
71% of VPU stores are used in vector version.
40% of VPU addition or subtraction instructions are used in vector version.
19% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 72 FP arithmetical operations:

72: addition or subtraction

The binary function is loading 160 bytes. The binary function is storing 201 bytes.

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	173
nb uops	171
loop length	692
used w registers	6
used x registers	17
used b registers	0
used h registers	0
used s registers	12
used d registers	12
used q registers	0
used v registers	23
used z registers	25
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.38 cycles
front end	21.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	21.00	21.00	21.00	21.00	18.25	18.25	18.25	18.25	9.50	9.50	5.00	0.50	0.50
cycles	5.50	5.50	21.00	21.00	21.00	21.00	18.25	18.25	18.25	18.25	9.50	9.50	5.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.38
Dispatch	21.00
Overall L1	21.38

Vectorization ratios

INT

all	30%
load	90%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	47%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	32%
load	90%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Vector efficiency ratios

INT

all	39%
load	72%
store	61%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	53%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

INT+FP

all	41%
load	72%
store	61%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	55%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.38 cycles. At this rate:

7% of peak load performance is reached (7.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 410840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 410888 <Step10_orig+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D15, D14, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADDVL SP, SP, #58	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMOV S12, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI D13, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.CS 410898 <Step10_orig+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 410cf4 <Step10_orig+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 410ce4 <Step10_orig+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 4108b4 <Step10_orig+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 410b68 <Step10_orig+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W15, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W13, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR Z1, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z7.S, Z1.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z0.S, Z12.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI V19.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVK W15, #14461	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W13, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z16.S, Z2.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z17.S, Z3.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI V31.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V28.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V30.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP Z22.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W15, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z20.S, Z4.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V27.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V29.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP Z1.S, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
AND X10, X8, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK W15, #47759	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND X9, X8, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X4, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X2, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X3, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR Z12, [SP, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z23.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W15, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR Z0, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z2, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z3, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVK W15, #15420	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P2.S, VL4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
STR Z4, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z24.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W15, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #48537	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z25.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W15, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #16009	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z26.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
AND X15, X8, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FADD Z0.S, Z31.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FADDV S6, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADD Z0.S, Z30.S, Z28.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S7, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADD Z0.S, Z29.S, Z27.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S16, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
B.EQ 410ccc <Step10_orig+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Z4, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z3, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
MOVI D13, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Z2, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z1, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z12, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
CBZ X10, 410cf4 <Step10_orig+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V19.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ W15, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVI V17.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V18.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X14, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X9, X8, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V20.4S, V12.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
PTRUE P0.S, VL4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVK W15, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP V21.4S, V1.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
DUP V22.4S, V2.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
DUP V23.4S, V3.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ORR Z8.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X10, X14, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X4, X14,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOV V19.S[0], V7.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
DUP V7.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
MOVZ W15, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV V17.S[0], V16.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
DUP V24.4S, V4.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
MOV V18.S[0], V6.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FDUP Z6.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
ADD X12, X3, X14,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK W15, #47229	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X13, X2, X14,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X1, X14,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP V16.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
MOVZ W15, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #14991	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP V25.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
MOVZ W15, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #48188	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP V26.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
MOVZ W15, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #15769	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP V27.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
MOVZ W15, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #48777	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP V28.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
FADDV S6, P0, Z18.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR Z4.D, Z8.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S7, P0, Z19.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADDV S16, P0, Z17.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
B.NE 410cf4 <Step10_orig+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP D15, D14, [SP], #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
STR S16, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S7, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S6, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X4, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X3, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X2, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X1, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D17, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W9, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #47229	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S18, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S19, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #14991	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S20, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #48188	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S21, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #15769	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S22, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #48777	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S23, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
B 410db8 <Step10_orig+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.05% of application time for run armclang_7

Source file and lines	Step10_orig.c:19-41
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-177-5622/intel/HACCmk/build/HACCmk/src/Step10_orig.c:19-41.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

32% of VPU instructions are used in vector version (process two or more data elements in vector registers):

90% of VPU loads are used in vector version.
71% of VPU stores are used in vector version.
40% of VPU addition or subtraction instructions are used in vector version.
19% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 72 FP arithmetical operations:

72: addition or subtraction

The binary function is loading 160 bytes. The binary function is storing 201 bytes.

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	173
nb uops	171
loop length	692
used w registers	6
used x registers	17
used b registers	0
used h registers	0
used s registers	12
used d registers	12
used q registers	0
used v registers	23
used z registers	25
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.38 cycles
front end	21.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	21.00	21.00	21.00	21.00	18.25	18.25	18.25	18.25	9.50	9.50	5.00	0.50	0.50
cycles	5.50	5.50	21.00	21.00	21.00	21.00	18.25	18.25	18.25	18.25	9.50	9.50	5.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.38
Dispatch	21.00
Overall L1	21.38

Vectorization ratios

INT

all	30%
load	90%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	47%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	32%
load	90%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Vector efficiency ratios

INT

all	39%
load	72%
store	61%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	53%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

INT+FP

all	41%
load	72%
store	61%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	55%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.38 cycles. At this rate:

7% of peak load performance is reached (7.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 410840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.LT 410888 <Step10_orig+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D15, D14, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADDVL SP, SP, #58	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMOV S12, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVI D13, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.CS 410898 <Step10_orig+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 410cf4 <Step10_orig+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 410ce4 <Step10_orig+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 4108b4 <Step10_orig+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 410b68 <Step10_orig+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W15, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVZ W13, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR Z1, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z7.S, Z1.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z0.S, Z12.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P0.S, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI V19.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVK W15, #14461	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W13, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z16.S, Z2.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z17.S, Z3.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI V31.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V28.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V30.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP Z22.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W15, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z20.S, Z4.S[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FDUP Z21.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V27.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V29.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP Z1.S, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
AND X10, X8, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK W15, #47759	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND X9, X8, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X4, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X2, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X3, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR Z12, [SP, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z23.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W15, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR Z0, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z2, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z3, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVK W15, #15420	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P2.S, VL4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
STR Z4, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z24.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W15, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #48537	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z25.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOVZ W15, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #16009	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z26.S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
AND X15, X8, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FADD Z0.S, Z31.S, Z19.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FADDV S6, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADD Z0.S, Z30.S, Z28.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S7, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADD Z0.S, Z29.S, Z27.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S16, P0, Z0.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
B.EQ 410ccc <Step10_orig+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Z4, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z3, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
MOVI D13, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Z2, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z1, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z12, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
CBZ X10, 410cf4 <Step10_orig+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V19.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ W15, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVI V17.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V18.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X14, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X9, X8, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V20.4S, V12.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
PTRUE P0.S, VL4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVK W15, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP V21.4S, V1.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
DUP V22.4S, V2.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
DUP V23.4S, V3.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ORR Z8.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X10, X14, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X4, X14,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOV V19.S[0], V7.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
DUP V7.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
MOVZ W15, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV V17.S[0], V16.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
DUP V24.4S, V4.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
MOV V18.S[0], V6.S[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
FDUP Z6.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
ADD X12, X3, X14,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVK W15, #47229	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X13, X2, X14,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X1, X14,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP V16.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
MOVZ W15, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #14991	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP V25.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
MOVZ W15, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #48188	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP V26.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
MOVZ W15, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #15769	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP V27.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
MOVZ W15, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK W15, #48777	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP V28.4S, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (50.0%)
FADDV S6, P0, Z18.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR Z4.D, Z8.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDV S7, P0, Z19.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
FADDV S16, P0, Z17.S	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	11	2.50	vect (100.0%)
B.NE 410cf4 <Step10_orig+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP D15, D14, [SP], #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
STR S16, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S7, [X6]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
STR S6, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X4, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X3, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X2, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X1, X9,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D17, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W9, #63002	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #47229	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S18, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #35234	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #13765	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S19, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #18267	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #14991	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S20, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #6647	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #48188	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S21, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #52448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #15769	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S22, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
MOVZ W9, #58683	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK W9, #48777	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV S23, W9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
B 410db8 <Step10_orig+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼Step10_orig–	97.69	27.28
○Loop 5 - Step10_orig.c:19-35 - exec	97.62	27.12
○Loop 6 - Step10_orig.c:19-35 - exec	0.02	0.01
○Loop 4 - Step10_orig.c:19-35 - exec	0.00	0.00

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Vectorization

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Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

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ASM code